Lines Matching +full:pins +full:- +full:are +full:- +full:numbered
7 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
38 #include <linux/can/rx-offload.h>
46 #define HECC_MAX_MAILBOXES 32 /* hardware mailboxes - do not change */
47 #define MAX_TX_PRIO 0x3F /* hardware value - do not change */
52 * for the mailbox logic to work. Top mailbox numbers are reserved for RX
65 #define HECC_TX_MB_MASK (HECC_MAX_TX_MBOX - 1)
66 #define HECC_TX_MASK ((HECC_MAX_TX_MBOX - 1) | HECC_TX_PRIO_MASK)
70 * The remaining mailboxes are used for reception and are delivered
72 * changed while CAN-bus traffic is being received.
74 #define HECC_MAX_RX_MBOX (HECC_MAX_MAILBOXES - HECC_MAX_TX_MBOX)
75 #define HECC_RX_FIRST_MBOX (HECC_MAX_MAILBOXES - 1)
103 #define HECC_CANTOC 0x60 /* HECC only: Time-out control */
104 #define HECC_CANTOS 0x64 /* HECC only: Time-out status */
123 #define HECC_CANMC_PDR BIT(11) /* Local Power down - for sleep mode */
125 #define HECC_CANMC_STM BIT(6) /* Self test mode - loopback */
204 return priv->tx_head & HECC_TX_MB_MASK; in get_tx_head_mb()
209 return priv->tx_tail & HECC_TX_MB_MASK; in get_tx_tail_mb()
214 return (priv->tx_head >> HECC_TX_PRIO_SHIFT) & MAX_TX_PRIO; in get_tx_head_prio()
219 __raw_writel(val, priv->hecc_ram + mbxno * 4); in hecc_write_lam()
224 return __raw_readl(priv->hecc_ram + HECC_CANMOTS + mbxno * 4); in hecc_read_stamp()
230 __raw_writel(val, priv->mbx + mbxno * 0x10 + reg); in hecc_write_mbx()
235 return __raw_readl(priv->mbx + mbxno * 0x10 + reg); in hecc_read_mbx()
240 __raw_writel(val, priv->base + reg); in hecc_write()
245 return __raw_readl(priv->base + reg); in hecc_read()
267 struct can_bittiming *bit_timing = &priv->can.bittiming; in ti_hecc_set_btc()
270 can_btc = (bit_timing->phase_seg2 - 1) & 0x7; in ti_hecc_set_btc()
271 can_btc |= ((bit_timing->phase_seg1 + bit_timing->prop_seg - 1) in ti_hecc_set_btc()
273 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) { in ti_hecc_set_btc()
274 if (bit_timing->brp > 4) in ti_hecc_set_btc()
277 netdev_warn(priv->ndev, in ti_hecc_set_btc()
280 can_btc |= ((bit_timing->sjw - 1) & 0x3) << 8; in ti_hecc_set_btc()
281 can_btc |= ((bit_timing->brp - 1) & 0xFF) << 16; in ti_hecc_set_btc()
286 netdev_info(priv->ndev, "setting CANBTC=%#x\n", can_btc); in ti_hecc_set_btc()
294 if (!priv->reg_xceiver) in ti_hecc_transceiver_switch()
298 return regulator_enable(priv->reg_xceiver); in ti_hecc_transceiver_switch()
300 return regulator_disable(priv->reg_xceiver); in ti_hecc_transceiver_switch()
320 --cnt; in ti_hecc_reset()
325 * it is expected that the can bittiming parameters are set via ip in ti_hecc_reset()
333 /* INFO: CAN net stack handles bus off and hence disabling auto-bus-on in ti_hecc_reset()
342 --cnt; in ti_hecc_reset()
346 /* Enable TX and RX I/O Control pins */ in ti_hecc_reset()
370 priv->tx_head = HECC_TX_MASK; in ti_hecc_start()
371 priv->tx_tail = HECC_TX_MASK; in ti_hecc_start()
378 mbxno = HECC_MAX_MAILBOXES - 1 - cnt; in ti_hecc_start()
389 hecc_set_bit(priv, HECC_CANMIM, BIT(HECC_MAX_TX_MBOX) - 1); in ti_hecc_start()
391 /* Prevent message over-write to create a rx fifo, but not for in ti_hecc_start()
400 if (priv->use_hecc1int) { in ti_hecc_start()
409 priv->can.state = CAN_STATE_ERROR_ACTIVE; in ti_hecc_start()
423 priv->can.state = CAN_STATE_STOPPED; in ti_hecc_stop()
436 ret = -EOPNOTSUPP; in ti_hecc_do_set_mode()
448 bec->txerr = hecc_read(priv, HECC_CANTEC); in ti_hecc_get_berr_counter()
449 bec->rxerr = hecc_read(priv, HECC_CANREC); in ti_hecc_get_berr_counter()
460 * priority field the highest numbered mailbox is transmitted first.
463 * highest numbered mailbox with highest priority level and move on to the next
466 * until we reach the lowest priority level on the lowest numbered mailbox
467 * when we stop transmission until all mailboxes are transmitted and then
468 * restart at highest numbered mailbox with highest priority.
470 * Two counters (head and tail) are used to track the next mailbox to transmit
472 * is stopped when all the mailboxes are busy or when there is a priority
473 * value roll-over happens.
478 struct can_frame *cf = (struct can_frame *)skb->data; in ti_hecc_xmit()
487 spin_lock_irqsave(&priv->mbx_lock, flags); in ti_hecc_xmit()
489 spin_unlock_irqrestore(&priv->mbx_lock, flags); in ti_hecc_xmit()
491 netdev_err(priv->ndev, in ti_hecc_xmit()
493 priv->tx_head, priv->tx_tail); in ti_hecc_xmit()
496 spin_unlock_irqrestore(&priv->mbx_lock, flags); in ti_hecc_xmit()
499 data = cf->len | (get_tx_head_prio(priv) << 8); in ti_hecc_xmit()
500 if (cf->can_id & CAN_RTR_FLAG) /* Remote transmission request */ in ti_hecc_xmit()
504 if (cf->can_id & CAN_EFF_FLAG) /* Extended frame format */ in ti_hecc_xmit()
505 data = (cf->can_id & CAN_EFF_MASK) | HECC_CANMID_IDE; in ti_hecc_xmit()
507 data = (cf->can_id & CAN_SFF_MASK) << 18; in ti_hecc_xmit()
510 be32_to_cpu(*(__be32 *)(cf->data))); in ti_hecc_xmit()
511 if (cf->len > 4) in ti_hecc_xmit()
513 be32_to_cpu(*(__be32 *)(cf->data + 4))); in ti_hecc_xmit()
515 *(u32 *)(cf->data + 4) = 0; in ti_hecc_xmit()
518 spin_lock_irqsave(&priv->mbx_lock, flags); in ti_hecc_xmit()
519 --priv->tx_head; in ti_hecc_xmit()
521 (priv->tx_head & HECC_TX_MASK) == HECC_TX_MASK) { in ti_hecc_xmit()
525 spin_unlock_irqrestore(&priv->mbx_lock, flags); in ti_hecc_xmit()
550 skb = ERR_PTR(-ENOBUFS); in ti_hecc_mailbox_read()
554 skb = alloc_can_skb(offload->dev, &cf); in ti_hecc_mailbox_read()
556 skb = ERR_PTR(-ENOMEM); in ti_hecc_mailbox_read()
562 cf->can_id = (data & CAN_EFF_MASK) | CAN_EFF_FLAG; in ti_hecc_mailbox_read()
564 cf->can_id = (data >> 18) & CAN_SFF_MASK; in ti_hecc_mailbox_read()
568 cf->can_id |= CAN_RTR_FLAG; in ti_hecc_mailbox_read()
569 cf->len = can_cc_dlc2len(data & 0xF); in ti_hecc_mailbox_read()
572 *(__be32 *)(cf->data) = cpu_to_be32(data); in ti_hecc_mailbox_read()
573 if (cf->len > 4) { in ti_hecc_mailbox_read()
575 *(__be32 *)(cf->data + 4) = cpu_to_be32(data); in ti_hecc_mailbox_read()
590 * Return an error to let rx-offload discard this CAN frame. in ti_hecc_mailbox_read()
594 skb = ERR_PTR(-ENOBUFS); in ti_hecc_mailbox_read()
616 netdev_err(priv->ndev, in ti_hecc_error()
619 return -ENOMEM; in ti_hecc_error()
622 ++priv->can.can_stats.bus_error; in ti_hecc_error()
623 cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT; in ti_hecc_error()
625 cf->data[2] |= CAN_ERR_PROT_FORM; in ti_hecc_error()
627 cf->data[2] |= CAN_ERR_PROT_BIT; in ti_hecc_error()
629 cf->data[2] |= CAN_ERR_PROT_STUFF; in ti_hecc_error()
631 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ; in ti_hecc_error()
633 cf->data[3] = CAN_ERR_PROT_LOC_ACK; in ti_hecc_error()
636 err = can_rx_offload_queue_sorted(&priv->offload, skb, in ti_hecc_error()
639 ndev->stats.rx_fifo_errors++; in ti_hecc_error()
657 skb = alloc_can_err_skb(priv->ndev, &cf); in ti_hecc_change_state()
659 priv->can.state = max(tx_state, rx_state); in ti_hecc_change_state()
663 can_change_state(priv->ndev, cf, tx_state, rx_state); in ti_hecc_change_state()
666 cf->data[6] = hecc_read(priv, HECC_CANTEC); in ti_hecc_change_state()
667 cf->data[7] = hecc_read(priv, HECC_CANREC); in ti_hecc_change_state()
671 err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp); in ti_hecc_change_state()
673 ndev->stats.rx_fifo_errors++; in ti_hecc_change_state()
680 struct net_device_stats *stats = &ndev->stats; in ti_hecc_interrupt()
686 priv->use_hecc1int ? in ti_hecc_interrupt()
705 netdev_dbg(priv->ndev, "Error Warning interrupt\n"); in ti_hecc_interrupt()
713 netdev_dbg(priv->ndev, "Error passive interrupt\n"); in ti_hecc_interrupt()
721 netdev_dbg(priv->ndev, "Bus off interrupt\n"); in ti_hecc_interrupt()
728 } else if (unlikely(priv->can.state != CAN_STATE_ERROR_ACTIVE)) { in ti_hecc_interrupt()
740 if (new_state < priv->can.state) { in ti_hecc_interrupt()
748 while (priv->tx_tail - priv->tx_head > 0) { in ti_hecc_interrupt()
754 spin_lock_irqsave(&priv->mbx_lock, flags); in ti_hecc_interrupt()
756 spin_unlock_irqrestore(&priv->mbx_lock, flags); in ti_hecc_interrupt()
758 stats->tx_bytes += in ti_hecc_interrupt()
759 can_rx_offload_get_echo_skb(&priv->offload, in ti_hecc_interrupt()
761 stats->tx_packets++; in ti_hecc_interrupt()
763 --priv->tx_tail; in ti_hecc_interrupt()
766 /* restart queue if wrap-up or if queue stalled on last pkt */ in ti_hecc_interrupt()
767 if ((priv->tx_head == priv->tx_tail && in ti_hecc_interrupt()
768 ((priv->tx_head & HECC_TX_MASK) != HECC_TX_MASK)) || in ti_hecc_interrupt()
769 (((priv->tx_tail & HECC_TX_MASK) == HECC_TX_MASK) && in ti_hecc_interrupt()
770 ((priv->tx_head & HECC_TX_MASK) == HECC_TX_MASK))) in ti_hecc_interrupt()
775 can_rx_offload_irq_offload_timestamp(&priv->offload, in ti_hecc_interrupt()
780 /* clear all interrupt conditions - read back to avoid spurious ints */ in ti_hecc_interrupt()
781 if (priv->use_hecc1int) { in ti_hecc_interrupt()
789 can_rx_offload_irq_finish(&priv->offload); in ti_hecc_interrupt()
799 err = request_irq(ndev->irq, ti_hecc_interrupt, IRQF_SHARED, in ti_hecc_open()
800 ndev->name, ndev); in ti_hecc_open()
813 free_irq(ndev->irq, ndev); in ti_hecc_open()
820 can_rx_offload_enable(&priv->offload); in ti_hecc_open()
831 can_rx_offload_disable(&priv->offload); in ti_hecc_close()
833 free_irq(ndev->irq, ndev); in ti_hecc_close()
851 .compatible = "ti,am3517-hecc",
861 struct device_node *np = pdev->dev.of_node; in ti_hecc_probe()
864 int err = -ENODEV; in ti_hecc_probe()
867 return -EINVAL; in ti_hecc_probe()
869 reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver"); in ti_hecc_probe()
870 if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER) in ti_hecc_probe()
871 return -EPROBE_DEFER; in ti_hecc_probe()
877 dev_err(&pdev->dev, "alloc_candev failed\n"); in ti_hecc_probe()
878 return -ENOMEM; in ti_hecc_probe()
883 priv->base = devm_platform_ioremap_resource_byname(pdev, "hecc"); in ti_hecc_probe()
884 if (IS_ERR(priv->base)) { in ti_hecc_probe()
885 dev_err(&pdev->dev, "hecc ioremap failed\n"); in ti_hecc_probe()
886 err = PTR_ERR(priv->base); in ti_hecc_probe()
890 /* handle hecc-ram memory */ in ti_hecc_probe()
891 priv->hecc_ram = devm_platform_ioremap_resource_byname(pdev, in ti_hecc_probe()
892 "hecc-ram"); in ti_hecc_probe()
893 if (IS_ERR(priv->hecc_ram)) { in ti_hecc_probe()
894 dev_err(&pdev->dev, "hecc-ram ioremap failed\n"); in ti_hecc_probe()
895 err = PTR_ERR(priv->hecc_ram); in ti_hecc_probe()
900 priv->mbx = devm_platform_ioremap_resource_byname(pdev, "mbx"); in ti_hecc_probe()
901 if (IS_ERR(priv->mbx)) { in ti_hecc_probe()
902 dev_err(&pdev->dev, "mbx ioremap failed\n"); in ti_hecc_probe()
903 err = PTR_ERR(priv->mbx); in ti_hecc_probe()
909 dev_err(&pdev->dev, "No irq resource\n"); in ti_hecc_probe()
913 priv->ndev = ndev; in ti_hecc_probe()
914 priv->reg_xceiver = reg_xceiver; in ti_hecc_probe()
915 priv->use_hecc1int = of_property_read_bool(np, "ti,use-hecc1int"); in ti_hecc_probe()
917 priv->can.bittiming_const = &ti_hecc_bittiming_const; in ti_hecc_probe()
918 priv->can.do_set_mode = ti_hecc_do_set_mode; in ti_hecc_probe()
919 priv->can.do_get_berr_counter = ti_hecc_get_berr_counter; in ti_hecc_probe()
920 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES; in ti_hecc_probe()
922 spin_lock_init(&priv->mbx_lock); in ti_hecc_probe()
923 ndev->irq = irq->start; in ti_hecc_probe()
924 ndev->flags |= IFF_ECHO; in ti_hecc_probe()
926 SET_NETDEV_DEV(ndev, &pdev->dev); in ti_hecc_probe()
927 ndev->netdev_ops = &ti_hecc_netdev_ops; in ti_hecc_probe()
929 priv->clk = clk_get(&pdev->dev, "hecc_ck"); in ti_hecc_probe()
930 if (IS_ERR(priv->clk)) { in ti_hecc_probe()
931 dev_err(&pdev->dev, "No clock available\n"); in ti_hecc_probe()
932 err = PTR_ERR(priv->clk); in ti_hecc_probe()
933 priv->clk = NULL; in ti_hecc_probe()
936 priv->can.clock.freq = clk_get_rate(priv->clk); in ti_hecc_probe()
938 err = clk_prepare_enable(priv->clk); in ti_hecc_probe()
940 dev_err(&pdev->dev, "clk_prepare_enable() failed\n"); in ti_hecc_probe()
944 priv->offload.mailbox_read = ti_hecc_mailbox_read; in ti_hecc_probe()
945 priv->offload.mb_first = HECC_RX_FIRST_MBOX; in ti_hecc_probe()
946 priv->offload.mb_last = HECC_RX_LAST_MBOX; in ti_hecc_probe()
947 err = can_rx_offload_add_timestamp(ndev, &priv->offload); in ti_hecc_probe()
949 dev_err(&pdev->dev, "can_rx_offload_add_timestamp() failed\n"); in ti_hecc_probe()
955 dev_err(&pdev->dev, "register_candev() failed\n"); in ti_hecc_probe()
961 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%u)\n", in ti_hecc_probe()
962 priv->base, (u32)ndev->irq); in ti_hecc_probe()
967 can_rx_offload_del(&priv->offload); in ti_hecc_probe()
969 clk_disable_unprepare(priv->clk); in ti_hecc_probe()
971 clk_put(priv->clk); in ti_hecc_probe()
984 clk_disable_unprepare(priv->clk); in ti_hecc_remove()
985 clk_put(priv->clk); in ti_hecc_remove()
986 can_rx_offload_del(&priv->offload); in ti_hecc_remove()
1004 priv->can.state = CAN_STATE_SLEEPING; in ti_hecc_suspend()
1006 clk_disable_unprepare(priv->clk); in ti_hecc_suspend()
1017 err = clk_prepare_enable(priv->clk); in ti_hecc_resume()
1022 priv->can.state = CAN_STATE_ERROR_ACTIVE; in ti_hecc_resume()