Lines Matching refs:cdev
321 static inline u32 m_can_read(struct m_can_classdev *cdev, enum m_can_reg reg) in m_can_read() argument
323 return cdev->ops->read_reg(cdev, reg); in m_can_read()
326 static inline void m_can_write(struct m_can_classdev *cdev, enum m_can_reg reg, in m_can_write() argument
329 cdev->ops->write_reg(cdev, reg, val); in m_can_write()
333 m_can_fifo_read(struct m_can_classdev *cdev, in m_can_fifo_read() argument
336 u32 addr_offset = cdev->mcfg[MRAM_RXF0].off + fgi * RXF0_ELEMENT_SIZE + in m_can_fifo_read()
339 return cdev->ops->read_fifo(cdev, addr_offset, val, val_count); in m_can_fifo_read()
343 m_can_fifo_write(struct m_can_classdev *cdev, in m_can_fifo_write() argument
346 u32 addr_offset = cdev->mcfg[MRAM_TXB].off + fpi * TXB_ELEMENT_SIZE + in m_can_fifo_write()
349 return cdev->ops->write_fifo(cdev, addr_offset, val, val_count); in m_can_fifo_write()
352 static inline int m_can_fifo_write_no_off(struct m_can_classdev *cdev, in m_can_fifo_write_no_off() argument
355 return cdev->ops->write_fifo(cdev, fpi, &val, 1); in m_can_fifo_write_no_off()
359 m_can_txe_fifo_read(struct m_can_classdev *cdev, u32 fgi, u32 offset, u32 *val) in m_can_txe_fifo_read() argument
361 u32 addr_offset = cdev->mcfg[MRAM_TXE].off + fgi * TXE_ELEMENT_SIZE + in m_can_txe_fifo_read()
364 return cdev->ops->read_fifo(cdev, addr_offset, val, 1); in m_can_txe_fifo_read()
367 static inline bool m_can_tx_fifo_full(struct m_can_classdev *cdev) in m_can_tx_fifo_full() argument
369 return !!(m_can_read(cdev, M_CAN_TXFQS) & TXFQS_TFQF); in m_can_tx_fifo_full()
372 static void m_can_config_endisable(struct m_can_classdev *cdev, bool enable) in m_can_config_endisable() argument
374 u32 cccr = m_can_read(cdev, M_CAN_CCCR); in m_can_config_endisable()
384 m_can_write(cdev, M_CAN_CCCR, cccr | CCCR_INIT); in m_can_config_endisable()
387 m_can_write(cdev, M_CAN_CCCR, cccr | CCCR_INIT | CCCR_CCE); in m_can_config_endisable()
389 m_can_write(cdev, M_CAN_CCCR, cccr & ~(CCCR_INIT | CCCR_CCE)); in m_can_config_endisable()
396 while ((m_can_read(cdev, M_CAN_CCCR) & (CCCR_INIT | CCCR_CCE)) != val) { in m_can_config_endisable()
398 netdev_warn(cdev->net, "Failed to init module\n"); in m_can_config_endisable()
406 static inline void m_can_enable_all_interrupts(struct m_can_classdev *cdev) in m_can_enable_all_interrupts() argument
409 m_can_write(cdev, M_CAN_ILE, ILE_EINT0); in m_can_enable_all_interrupts()
412 static inline void m_can_disable_all_interrupts(struct m_can_classdev *cdev) in m_can_disable_all_interrupts() argument
414 m_can_write(cdev, M_CAN_ILE, 0x0); in m_can_disable_all_interrupts()
420 static u32 m_can_get_timestamp(struct m_can_classdev *cdev) in m_can_get_timestamp() argument
425 tscv = m_can_read(cdev, M_CAN_TSCV); in m_can_get_timestamp()
433 struct m_can_classdev *cdev = netdev_priv(net); in m_can_clean() local
435 if (cdev->tx_skb) { in m_can_clean()
439 if (cdev->version > 30) in m_can_clean()
441 m_can_read(cdev, M_CAN_TXFQS)); in m_can_clean()
443 can_free_echo_skb(cdev->net, putidx, NULL); in m_can_clean()
444 cdev->tx_skb = NULL; in m_can_clean()
453 static void m_can_receive_skb(struct m_can_classdev *cdev, in m_can_receive_skb() argument
457 if (cdev->is_peripheral) { in m_can_receive_skb()
458 struct net_device_stats *stats = &cdev->net->stats; in m_can_receive_skb()
461 err = can_rx_offload_queue_sorted(&cdev->offload, skb, in m_can_receive_skb()
473 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_read_fifo() local
483 err = m_can_fifo_read(cdev, fgi, M_CAN_FIFO_ID, &fifo_header, 2); in m_can_read_fifo()
517 err = m_can_fifo_read(cdev, fgi, M_CAN_FIFO_DATA, in m_can_read_fifo()
524 m_can_write(cdev, M_CAN_RXF0A, fgi); in m_can_read_fifo()
531 m_can_receive_skb(cdev, skb, timestamp); in m_can_read_fifo()
542 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_do_rx_poll() local
547 rxfs = m_can_read(cdev, M_CAN_RXF0S); in m_can_do_rx_poll()
560 rxfs = m_can_read(cdev, M_CAN_RXF0S); in m_can_do_rx_poll()
571 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_handle_lost_msg() local
589 if (cdev->is_peripheral) in m_can_handle_lost_msg()
590 timestamp = m_can_get_timestamp(cdev); in m_can_handle_lost_msg()
592 m_can_receive_skb(cdev, skb, timestamp); in m_can_handle_lost_msg()
600 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_handle_lec_err() local
606 cdev->can.can_stats.bus_error++; in m_can_handle_lec_err()
651 if (cdev->is_peripheral) in m_can_handle_lec_err()
652 timestamp = m_can_get_timestamp(cdev); in m_can_handle_lec_err()
654 m_can_receive_skb(cdev, skb, timestamp); in m_can_handle_lec_err()
662 struct m_can_classdev *cdev = netdev_priv(dev); in __m_can_get_berr_counter() local
665 ecr = m_can_read(cdev, M_CAN_ECR); in __m_can_get_berr_counter()
672 static int m_can_clk_start(struct m_can_classdev *cdev) in m_can_clk_start() argument
674 if (cdev->pm_clock_support == 0) in m_can_clk_start()
677 return pm_runtime_resume_and_get(cdev->dev); in m_can_clk_start()
680 static void m_can_clk_stop(struct m_can_classdev *cdev) in m_can_clk_stop() argument
682 if (cdev->pm_clock_support) in m_can_clk_stop()
683 pm_runtime_put_sync(cdev->dev); in m_can_clk_stop()
689 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_get_berr_counter() local
692 err = m_can_clk_start(cdev); in m_can_get_berr_counter()
698 m_can_clk_stop(cdev); in m_can_get_berr_counter()
706 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_handle_state_change() local
717 cdev->can.can_stats.error_warning++; in m_can_handle_state_change()
718 cdev->can.state = CAN_STATE_ERROR_WARNING; in m_can_handle_state_change()
722 cdev->can.can_stats.error_passive++; in m_can_handle_state_change()
723 cdev->can.state = CAN_STATE_ERROR_PASSIVE; in m_can_handle_state_change()
727 cdev->can.state = CAN_STATE_BUS_OFF; in m_can_handle_state_change()
728 m_can_disable_all_interrupts(cdev); in m_can_handle_state_change()
729 cdev->can.can_stats.bus_off++; in m_can_handle_state_change()
756 ecr = m_can_read(cdev, M_CAN_ECR); in m_can_handle_state_change()
775 if (cdev->is_peripheral) in m_can_handle_state_change()
776 timestamp = m_can_get_timestamp(cdev); in m_can_handle_state_change()
778 m_can_receive_skb(cdev, skb, timestamp); in m_can_handle_state_change()
785 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_handle_state_errors() local
788 if (psr & PSR_EW && cdev->can.state != CAN_STATE_ERROR_WARNING) { in m_can_handle_state_errors()
794 if (psr & PSR_EP && cdev->can.state != CAN_STATE_ERROR_PASSIVE) { in m_can_handle_state_errors()
800 if (psr & PSR_BO && cdev->can.state != CAN_STATE_BUS_OFF) { in m_can_handle_state_errors()
840 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_handle_protocol_error() local
852 if (cdev->version >= 31 && (irqstatus & IR_PEA)) { in m_can_handle_protocol_error()
854 cdev->can.can_stats.arbitration_lost++; in m_can_handle_protocol_error()
866 if (cdev->is_peripheral) in m_can_handle_protocol_error()
867 timestamp = m_can_get_timestamp(cdev); in m_can_handle_protocol_error()
869 m_can_receive_skb(cdev, skb, timestamp); in m_can_handle_protocol_error()
877 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_handle_bus_errors() local
884 if ((cdev->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) && in m_can_handle_bus_errors()
889 if ((cdev->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) && in m_can_handle_bus_errors()
901 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_rx_handler() local
906 irqstatus = cdev->irqstatus | m_can_read(cdev, M_CAN_IR); in m_can_rx_handler()
920 if (cdev->version <= 31 && irqstatus & IR_MRAF && in m_can_rx_handler()
921 m_can_read(cdev, M_CAN_ECR) & ECR_RP) { in m_can_rx_handler()
926 m_can_write(cdev, M_CAN_IR, IR_MRAF); in m_can_rx_handler()
931 psr = m_can_read(cdev, M_CAN_PSR); in m_can_rx_handler()
952 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_rx_peripheral() local
961 m_can_enable_all_interrupts(cdev); in m_can_rx_peripheral()
969 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_poll() local
979 m_can_enable_all_interrupts(cdev); in m_can_poll()
989 static void m_can_tx_update_stats(struct m_can_classdev *cdev, in m_can_tx_update_stats() argument
993 struct net_device *dev = cdev->net; in m_can_tx_update_stats()
996 if (cdev->is_peripheral) in m_can_tx_update_stats()
998 can_rx_offload_get_echo_skb(&cdev->offload, in m_can_tx_update_stats()
1016 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_echo_tx_event() local
1019 m_can_txefs = m_can_read(cdev, M_CAN_TXEFS); in m_can_echo_tx_event()
1030 fgi = FIELD_GET(TXEFS_EFGI_MASK, m_can_read(cdev, M_CAN_TXEFS)); in m_can_echo_tx_event()
1033 err = m_can_txe_fifo_read(cdev, fgi, 4, &txe); in m_can_echo_tx_event()
1043 m_can_write(cdev, M_CAN_TXEFA, FIELD_PREP(TXEFA_EFAI_MASK, in m_can_echo_tx_event()
1047 m_can_tx_update_stats(cdev, msg_mark, timestamp); in m_can_echo_tx_event()
1056 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_isr() local
1059 if (pm_runtime_suspended(cdev->dev)) in m_can_isr()
1061 ir = m_can_read(cdev, M_CAN_IR); in m_can_isr()
1067 m_can_write(cdev, M_CAN_IR, ir); in m_can_isr()
1069 if (cdev->ops->clear_interrupts) in m_can_isr()
1070 cdev->ops->clear_interrupts(cdev); in m_can_isr()
1078 cdev->irqstatus = ir; in m_can_isr()
1079 m_can_disable_all_interrupts(cdev); in m_can_isr()
1080 if (!cdev->is_peripheral) in m_can_isr()
1081 napi_schedule(&cdev->napi); in m_can_isr()
1086 if (cdev->version == 30) { in m_can_isr()
1091 if (cdev->is_peripheral) in m_can_isr()
1092 timestamp = m_can_get_timestamp(cdev); in m_can_isr()
1093 m_can_tx_update_stats(cdev, 0, timestamp); in m_can_isr()
1106 !m_can_tx_fifo_full(cdev)) in m_can_isr()
1111 if (cdev->is_peripheral) in m_can_isr()
1112 can_rx_offload_threaded_irq_finish(&cdev->offload); in m_can_isr()
1117 m_can_disable_all_interrupts(cdev); in m_can_isr()
1171 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_set_bittiming() local
1172 const struct can_bittiming *bt = &cdev->can.bittiming; in m_can_set_bittiming()
1173 const struct can_bittiming *dbt = &cdev->can.data_bittiming; in m_can_set_bittiming()
1185 m_can_write(cdev, M_CAN_NBTP, reg_btp); in m_can_set_bittiming()
1187 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) { in m_can_set_bittiming()
1209 tdco = (cdev->can.clock.freq / 1000) * in m_can_set_bittiming()
1220 m_can_write(cdev, M_CAN_TDCR, in m_can_set_bittiming()
1229 m_can_write(cdev, M_CAN_DBTP, reg_btp); in m_can_set_bittiming()
1247 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_chip_config() local
1250 m_can_config_endisable(cdev, true); in m_can_chip_config()
1253 m_can_write(cdev, M_CAN_RXESC, in m_can_chip_config()
1259 m_can_write(cdev, M_CAN_GFC, 0x0); in m_can_chip_config()
1261 if (cdev->version == 30) { in m_can_chip_config()
1263 m_can_write(cdev, M_CAN_TXBC, FIELD_PREP(TXBC_NDTB_MASK, 1) | in m_can_chip_config()
1264 cdev->mcfg[MRAM_TXB].off); in m_can_chip_config()
1267 m_can_write(cdev, M_CAN_TXBC, in m_can_chip_config()
1269 cdev->mcfg[MRAM_TXB].num) | in m_can_chip_config()
1270 cdev->mcfg[MRAM_TXB].off); in m_can_chip_config()
1274 m_can_write(cdev, M_CAN_TXESC, in m_can_chip_config()
1278 if (cdev->version == 30) { in m_can_chip_config()
1279 m_can_write(cdev, M_CAN_TXEFC, in m_can_chip_config()
1281 cdev->mcfg[MRAM_TXE].off); in m_can_chip_config()
1284 m_can_write(cdev, M_CAN_TXEFC, in m_can_chip_config()
1286 cdev->mcfg[MRAM_TXE].num) | in m_can_chip_config()
1287 cdev->mcfg[MRAM_TXE].off); in m_can_chip_config()
1291 m_can_write(cdev, M_CAN_RXF0C, in m_can_chip_config()
1292 FIELD_PREP(RXFC_FS_MASK, cdev->mcfg[MRAM_RXF0].num) | in m_can_chip_config()
1293 cdev->mcfg[MRAM_RXF0].off); in m_can_chip_config()
1295 m_can_write(cdev, M_CAN_RXF1C, in m_can_chip_config()
1296 FIELD_PREP(RXFC_FS_MASK, cdev->mcfg[MRAM_RXF1].num) | in m_can_chip_config()
1297 cdev->mcfg[MRAM_RXF1].off); in m_can_chip_config()
1299 cccr = m_can_read(cdev, M_CAN_CCCR); in m_can_chip_config()
1300 test = m_can_read(cdev, M_CAN_TEST); in m_can_chip_config()
1302 if (cdev->version == 30) { in m_can_chip_config()
1309 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) in m_can_chip_config()
1318 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO) in m_can_chip_config()
1321 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) in m_can_chip_config()
1326 if (cdev->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) { in m_can_chip_config()
1332 if (cdev->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) in m_can_chip_config()
1336 if (cdev->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT) in m_can_chip_config()
1340 m_can_write(cdev, M_CAN_CCCR, cccr); in m_can_chip_config()
1341 m_can_write(cdev, M_CAN_TEST, test); in m_can_chip_config()
1344 m_can_write(cdev, M_CAN_IR, IR_ALL_INT); in m_can_chip_config()
1345 if (!(cdev->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) in m_can_chip_config()
1346 if (cdev->version == 30) in m_can_chip_config()
1347 m_can_write(cdev, M_CAN_IE, IR_ALL_INT & in m_can_chip_config()
1350 m_can_write(cdev, M_CAN_IE, IR_ALL_INT & in m_can_chip_config()
1353 m_can_write(cdev, M_CAN_IE, IR_ALL_INT); in m_can_chip_config()
1356 m_can_write(cdev, M_CAN_ILS, ILS_ALL_INT0); in m_can_chip_config()
1364 m_can_write(cdev, M_CAN_TSCC, FIELD_PREP(TSCC_TCP_MASK, 0xf)); in m_can_chip_config()
1366 m_can_config_endisable(cdev, false); in m_can_chip_config()
1368 if (cdev->ops->init) in m_can_chip_config()
1369 cdev->ops->init(cdev); in m_can_chip_config()
1374 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_start() local
1379 cdev->can.state = CAN_STATE_ERROR_ACTIVE; in m_can_start()
1381 m_can_enable_all_interrupts(cdev); in m_can_start()
1404 static int m_can_check_core_release(struct m_can_classdev *cdev) in m_can_check_core_release() argument
1414 crel_reg = m_can_read(cdev, M_CAN_CREL); in m_can_check_core_release()
1432 static bool m_can_niso_supported(struct m_can_classdev *cdev) in m_can_niso_supported() argument
1438 m_can_config_endisable(cdev, true); in m_can_niso_supported()
1439 cccr_reg = m_can_read(cdev, M_CAN_CCCR); in m_can_niso_supported()
1441 m_can_write(cdev, M_CAN_CCCR, cccr_reg); in m_can_niso_supported()
1444 cccr_poll = m_can_read(cdev, M_CAN_CCCR); in m_can_niso_supported()
1455 m_can_write(cdev, M_CAN_CCCR, cccr_reg); in m_can_niso_supported()
1457 m_can_config_endisable(cdev, false); in m_can_niso_supported()
1463 static int m_can_dev_setup(struct m_can_classdev *cdev) in m_can_dev_setup() argument
1465 struct net_device *dev = cdev->net; in m_can_dev_setup()
1468 m_can_version = m_can_check_core_release(cdev); in m_can_dev_setup()
1471 dev_err(cdev->dev, "Unsupported version number: %2d", in m_can_dev_setup()
1476 if (!cdev->is_peripheral) in m_can_dev_setup()
1477 netif_napi_add(dev, &cdev->napi, in m_can_dev_setup()
1481 cdev->version = m_can_version; in m_can_dev_setup()
1482 cdev->can.do_set_mode = m_can_set_mode; in m_can_dev_setup()
1483 cdev->can.do_get_berr_counter = m_can_get_berr_counter; in m_can_dev_setup()
1486 cdev->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | in m_can_dev_setup()
1493 switch (cdev->version) { in m_can_dev_setup()
1497 cdev->can.bittiming_const = &m_can_bittiming_const_30X; in m_can_dev_setup()
1498 cdev->can.data_bittiming_const = &m_can_data_bittiming_const_30X; in m_can_dev_setup()
1503 cdev->can.bittiming_const = &m_can_bittiming_const_31X; in m_can_dev_setup()
1504 cdev->can.data_bittiming_const = &m_can_data_bittiming_const_31X; in m_can_dev_setup()
1509 cdev->can.bittiming_const = &m_can_bittiming_const_31X; in m_can_dev_setup()
1510 cdev->can.data_bittiming_const = &m_can_data_bittiming_const_31X; in m_can_dev_setup()
1512 cdev->can.ctrlmode_supported |= in m_can_dev_setup()
1513 (m_can_niso_supported(cdev) ? in m_can_dev_setup()
1517 dev_err(cdev->dev, "Unsupported version number: %2d", in m_can_dev_setup()
1518 cdev->version); in m_can_dev_setup()
1522 if (cdev->ops->init) in m_can_dev_setup()
1523 cdev->ops->init(cdev); in m_can_dev_setup()
1530 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_stop() local
1533 m_can_disable_all_interrupts(cdev); in m_can_stop()
1536 m_can_config_endisable(cdev, true); in m_can_stop()
1539 cdev->can.state = CAN_STATE_STOPPED; in m_can_stop()
1544 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_close() local
1548 if (!cdev->is_peripheral) in m_can_close()
1549 napi_disable(&cdev->napi); in m_can_close()
1552 m_can_clk_stop(cdev); in m_can_close()
1555 if (cdev->is_peripheral) { in m_can_close()
1556 cdev->tx_skb = NULL; in m_can_close()
1557 destroy_workqueue(cdev->tx_wq); in m_can_close()
1558 cdev->tx_wq = NULL; in m_can_close()
1561 if (cdev->is_peripheral) in m_can_close()
1562 can_rx_offload_disable(&cdev->offload); in m_can_close()
1567 phy_power_off(cdev->transceiver); in m_can_close()
1574 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_next_echo_skb_occupied() local
1576 unsigned int wrap = cdev->can.echo_skb_max; in m_can_next_echo_skb_occupied()
1583 return !!cdev->can.echo_skb[next_idx]; in m_can_next_echo_skb_occupied()
1586 static netdev_tx_t m_can_tx_handler(struct m_can_classdev *cdev) in m_can_tx_handler() argument
1588 struct canfd_frame *cf = (struct canfd_frame *)cdev->tx_skb->data; in m_can_tx_handler()
1589 struct net_device *dev = cdev->net; in m_can_tx_handler()
1590 struct sk_buff *skb = cdev->tx_skb; in m_can_tx_handler()
1596 cdev->tx_skb = NULL; in m_can_tx_handler()
1610 if (cdev->version == 30) { in m_can_tx_handler()
1616 err = m_can_fifo_write(cdev, 0, M_CAN_FIFO_ID, &fifo_header, 2); in m_can_tx_handler()
1620 err = m_can_fifo_write(cdev, 0, M_CAN_FIFO_DATA, in m_can_tx_handler()
1627 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) { in m_can_tx_handler()
1628 cccr = m_can_read(cdev, M_CAN_CCCR); in m_can_tx_handler()
1640 m_can_write(cdev, M_CAN_CCCR, cccr); in m_can_tx_handler()
1642 m_can_write(cdev, M_CAN_TXBTIE, 0x1); in m_can_tx_handler()
1643 m_can_write(cdev, M_CAN_TXBAR, 0x1); in m_can_tx_handler()
1649 if (m_can_tx_fifo_full(cdev)) { in m_can_tx_handler()
1655 if (cdev->is_peripheral) { in m_can_tx_handler()
1666 m_can_read(cdev, M_CAN_TXFQS)); in m_can_tx_handler()
1684 err = m_can_fifo_write(cdev, putidx, M_CAN_FIFO_ID, &fifo_header, 2); in m_can_tx_handler()
1688 err = m_can_fifo_write(cdev, putidx, M_CAN_FIFO_DATA, in m_can_tx_handler()
1699 m_can_write(cdev, M_CAN_TXBAR, (1 << putidx)); in m_can_tx_handler()
1702 if (m_can_tx_fifo_full(cdev) || in m_can_tx_handler()
1711 m_can_disable_all_interrupts(cdev); in m_can_tx_handler()
1717 struct m_can_classdev *cdev = container_of(ws, struct m_can_classdev, in m_can_tx_work_queue() local
1720 m_can_tx_handler(cdev); in m_can_tx_work_queue()
1726 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_start_xmit() local
1731 if (cdev->is_peripheral) { in m_can_start_xmit()
1732 if (cdev->tx_skb) { in m_can_start_xmit()
1737 if (cdev->can.state == CAN_STATE_BUS_OFF) { in m_can_start_xmit()
1745 cdev->tx_skb = skb; in m_can_start_xmit()
1746 netif_stop_queue(cdev->net); in m_can_start_xmit()
1747 queue_work(cdev->tx_wq, &cdev->tx_work); in m_can_start_xmit()
1750 cdev->tx_skb = skb; in m_can_start_xmit()
1751 return m_can_tx_handler(cdev); in m_can_start_xmit()
1759 struct m_can_classdev *cdev = netdev_priv(dev); in m_can_open() local
1762 err = phy_power_on(cdev->transceiver); in m_can_open()
1766 err = m_can_clk_start(cdev); in m_can_open()
1777 if (cdev->is_peripheral) in m_can_open()
1778 can_rx_offload_enable(&cdev->offload); in m_can_open()
1781 if (cdev->is_peripheral) { in m_can_open()
1782 cdev->tx_skb = NULL; in m_can_open()
1783 cdev->tx_wq = alloc_workqueue("mcan_wq", in m_can_open()
1785 if (!cdev->tx_wq) { in m_can_open()
1790 INIT_WORK(&cdev->tx_work, m_can_tx_work_queue); in m_can_open()
1810 if (!cdev->is_peripheral) in m_can_open()
1811 napi_enable(&cdev->napi); in m_can_open()
1818 if (cdev->is_peripheral) in m_can_open()
1819 destroy_workqueue(cdev->tx_wq); in m_can_open()
1821 if (cdev->is_peripheral) in m_can_open()
1822 can_rx_offload_disable(&cdev->offload); in m_can_open()
1825 m_can_clk_stop(cdev); in m_can_open()
1827 phy_power_off(cdev->transceiver); in m_can_open()
1846 static void m_can_of_parse_mram(struct m_can_classdev *cdev, in m_can_of_parse_mram() argument
1849 cdev->mcfg[MRAM_SIDF].off = mram_config_vals[0]; in m_can_of_parse_mram()
1850 cdev->mcfg[MRAM_SIDF].num = mram_config_vals[1]; in m_can_of_parse_mram()
1851 cdev->mcfg[MRAM_XIDF].off = cdev->mcfg[MRAM_SIDF].off + in m_can_of_parse_mram()
1852 cdev->mcfg[MRAM_SIDF].num * SIDF_ELEMENT_SIZE; in m_can_of_parse_mram()
1853 cdev->mcfg[MRAM_XIDF].num = mram_config_vals[2]; in m_can_of_parse_mram()
1854 cdev->mcfg[MRAM_RXF0].off = cdev->mcfg[MRAM_XIDF].off + in m_can_of_parse_mram()
1855 cdev->mcfg[MRAM_XIDF].num * XIDF_ELEMENT_SIZE; in m_can_of_parse_mram()
1856 cdev->mcfg[MRAM_RXF0].num = mram_config_vals[3] & in m_can_of_parse_mram()
1858 cdev->mcfg[MRAM_RXF1].off = cdev->mcfg[MRAM_RXF0].off + in m_can_of_parse_mram()
1859 cdev->mcfg[MRAM_RXF0].num * RXF0_ELEMENT_SIZE; in m_can_of_parse_mram()
1860 cdev->mcfg[MRAM_RXF1].num = mram_config_vals[4] & in m_can_of_parse_mram()
1862 cdev->mcfg[MRAM_RXB].off = cdev->mcfg[MRAM_RXF1].off + in m_can_of_parse_mram()
1863 cdev->mcfg[MRAM_RXF1].num * RXF1_ELEMENT_SIZE; in m_can_of_parse_mram()
1864 cdev->mcfg[MRAM_RXB].num = mram_config_vals[5]; in m_can_of_parse_mram()
1865 cdev->mcfg[MRAM_TXE].off = cdev->mcfg[MRAM_RXB].off + in m_can_of_parse_mram()
1866 cdev->mcfg[MRAM_RXB].num * RXB_ELEMENT_SIZE; in m_can_of_parse_mram()
1867 cdev->mcfg[MRAM_TXE].num = mram_config_vals[6]; in m_can_of_parse_mram()
1868 cdev->mcfg[MRAM_TXB].off = cdev->mcfg[MRAM_TXE].off + in m_can_of_parse_mram()
1869 cdev->mcfg[MRAM_TXE].num * TXE_ELEMENT_SIZE; in m_can_of_parse_mram()
1870 cdev->mcfg[MRAM_TXB].num = mram_config_vals[7] & in m_can_of_parse_mram()
1873 dev_dbg(cdev->dev, in m_can_of_parse_mram()
1875 cdev->mcfg[MRAM_SIDF].off, cdev->mcfg[MRAM_SIDF].num, in m_can_of_parse_mram()
1876 cdev->mcfg[MRAM_XIDF].off, cdev->mcfg[MRAM_XIDF].num, in m_can_of_parse_mram()
1877 cdev->mcfg[MRAM_RXF0].off, cdev->mcfg[MRAM_RXF0].num, in m_can_of_parse_mram()
1878 cdev->mcfg[MRAM_RXF1].off, cdev->mcfg[MRAM_RXF1].num, in m_can_of_parse_mram()
1879 cdev->mcfg[MRAM_RXB].off, cdev->mcfg[MRAM_RXB].num, in m_can_of_parse_mram()
1880 cdev->mcfg[MRAM_TXE].off, cdev->mcfg[MRAM_TXE].num, in m_can_of_parse_mram()
1881 cdev->mcfg[MRAM_TXB].off, cdev->mcfg[MRAM_TXB].num); in m_can_of_parse_mram()
1884 int m_can_init_ram(struct m_can_classdev *cdev) in m_can_init_ram() argument
1892 start = cdev->mcfg[MRAM_SIDF].off; in m_can_init_ram()
1893 end = cdev->mcfg[MRAM_TXB].off + in m_can_init_ram()
1894 cdev->mcfg[MRAM_TXB].num * TXB_ELEMENT_SIZE; in m_can_init_ram()
1897 err = m_can_fifo_write_no_off(cdev, i, 0x0); in m_can_init_ram()
1906 int m_can_class_get_clocks(struct m_can_classdev *cdev) in m_can_class_get_clocks() argument
1910 cdev->hclk = devm_clk_get(cdev->dev, "hclk"); in m_can_class_get_clocks()
1911 cdev->cclk = devm_clk_get(cdev->dev, "cclk"); in m_can_class_get_clocks()
1913 if (IS_ERR(cdev->cclk)) { in m_can_class_get_clocks()
1914 dev_err(cdev->dev, "no clock found\n"); in m_can_class_get_clocks()
1969 int m_can_class_register(struct m_can_classdev *cdev) in m_can_class_register() argument
1973 if (cdev->pm_clock_support) { in m_can_class_register()
1974 ret = m_can_clk_start(cdev); in m_can_class_register()
1979 if (cdev->is_peripheral) { in m_can_class_register()
1980 ret = can_rx_offload_add_manual(cdev->net, &cdev->offload, in m_can_class_register()
1986 ret = m_can_dev_setup(cdev); in m_can_class_register()
1990 ret = register_m_can_dev(cdev->net); in m_can_class_register()
1992 dev_err(cdev->dev, "registering %s failed (err=%d)\n", in m_can_class_register()
1993 cdev->net->name, ret); in m_can_class_register()
1997 devm_can_led_init(cdev->net); in m_can_class_register()
1999 of_can_transceiver(cdev->net); in m_can_class_register()
2001 dev_info(cdev->dev, "%s device registered (irq=%d, version=%d)\n", in m_can_class_register()
2002 KBUILD_MODNAME, cdev->net->irq, cdev->version); in m_can_class_register()
2007 m_can_clk_stop(cdev); in m_can_class_register()
2012 if (cdev->is_peripheral) in m_can_class_register()
2013 can_rx_offload_del(&cdev->offload); in m_can_class_register()
2015 m_can_clk_stop(cdev); in m_can_class_register()
2021 void m_can_class_unregister(struct m_can_classdev *cdev) in m_can_class_unregister() argument
2023 if (cdev->is_peripheral) in m_can_class_unregister()
2024 can_rx_offload_del(&cdev->offload); in m_can_class_unregister()
2025 unregister_candev(cdev->net); in m_can_class_unregister()
2031 struct m_can_classdev *cdev = dev_get_drvdata(dev); in m_can_class_suspend() local
2032 struct net_device *ndev = cdev->net; in m_can_class_suspend()
2038 m_can_clk_stop(cdev); in m_can_class_suspend()
2043 cdev->can.state = CAN_STATE_SLEEPING; in m_can_class_suspend()
2051 struct m_can_classdev *cdev = dev_get_drvdata(dev); in m_can_class_resume() local
2052 struct net_device *ndev = cdev->net; in m_can_class_resume()
2056 cdev->can.state = CAN_STATE_ERROR_ACTIVE; in m_can_class_resume()
2061 ret = m_can_clk_start(cdev); in m_can_class_resume()
2065 m_can_init_ram(cdev); in m_can_class_resume()