1284 		u32 reg_fdcbt, reg_ctrl2;  in flexcan_set_bittiming_cbt()  local
1320 		reg_ctrl2 = priv->read(&regs->ctrl2);  in flexcan_set_bittiming_cbt()
1321 		reg_ctrl2 &= ~FLEXCAN_CTRL2_ISOCANFDEN;  in flexcan_set_bittiming_cbt()
1323 			reg_ctrl2 |= FLEXCAN_CTRL2_ISOCANFDEN;  in flexcan_set_bittiming_cbt()
1325 		netdev_dbg(dev, "writing ctrl2=0x%08x\n", reg_ctrl2);  in flexcan_set_bittiming_cbt()
1326 		priv->write(reg_ctrl2, &regs->ctrl2);  in flexcan_set_bittiming_cbt()
1389 	u32 reg_ctrl2;  in flexcan_ram_init()  local
1399 	reg_ctrl2 = priv->read(&regs->ctrl2);  in flexcan_ram_init()
1400 	reg_ctrl2 |= FLEXCAN_CTRL2_WRMFRZ;  in flexcan_ram_init()
1401 	priv->write(reg_ctrl2, &regs->ctrl2);  in flexcan_ram_init()
1412 	reg_ctrl2 &= ~FLEXCAN_CTRL2_WRMFRZ;  in flexcan_ram_init()
1413 	priv->write(reg_ctrl2, &regs->ctrl2);  in flexcan_ram_init()
1495 	u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr;  in flexcan_chip_start()  local
1603 		reg_ctrl2 = priv->read(&regs->ctrl2);  in flexcan_chip_start()
1604 		reg_ctrl2 |= FLEXCAN_CTRL2_EACEN | FLEXCAN_CTRL2_RRS;  in flexcan_chip_start()
1605 		priv->write(reg_ctrl2, &regs->ctrl2);  in flexcan_chip_start()
1684 		reg_ctrl2 = priv->read(&regs->ctrl2);  in flexcan_chip_start()
1685 		reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE;  in flexcan_chip_start()
1686 		priv->write(reg_ctrl2, &regs->ctrl2);  in flexcan_chip_start()
1704 		reg_ctrl2 &= ~FLEXCAN_CTRL2_ECRWRE;  in flexcan_chip_start()
1705 		priv->write(reg_ctrl2, &regs->ctrl2);  in flexcan_chip_start()