Lines Matching +full:p1010 +full:- +full:flexcan
1 // SPDX-License-Identifier: GPL-2.0
3 // flexcan.c - FLEXCAN CAN controller driver
5 // Copyright (c) 2005-2006 Varma Electronics Oy
7 // Copyright (c) 2010-2017 Pengutronix, Marc Kleine-Budde <kernel@pengutronix.de>
10 // Based on code originally by Andrey Volkov <avolkov@varma-el.com>
12 #include <dt-bindings/firmware/imx/rsrc.h>
18 #include <linux/can/rx-offload.h>
31 #include <linux/can/platform/flexcan.h>
36 #define DRV_NAME "flexcan"
41 /* FLEXCAN module configuration register (CANMCR) bits */
68 /* FLEXCAN control register (CANCTRL) bits */
92 /* FLEXCAN control register 2 (CTRL2) bits */
102 /* FLEXCAN memory error control register (MECR) bits */
114 /* FLEXCAN error and status register (ESR) bits */
146 /* FLEXCAN Bit Timing register (CBT) bits */
154 /* FLEXCAN FD control register (FDCTRL) bits */
167 /* FLEXCAN FD Bit Timing register (FDCBT) bits */
174 /* FLEXCAN interrupt flag register (IFLAG) bits */
184 /* FLEXCAN message buffers */
209 /* FLEXCAN hardware feature flags
212 * SOC Version IP-Version Glitch- [TR]WRN_INT IRQ Err Memory err RTR rece- FD Mode MB
235 /* Disable non-correctable errors interrupt and freeze mode */
245 /* Support CAN-FD mode */
266 u32 ctrl; /* 0x04 - Not affected by Soft Reset */
269 u32 rxgmask; /* 0x10 - Not affected by Soft Reset */
270 u32 rx14mask; /* 0x14 - Not affected by Soft Reset */
271 u32 rx15mask; /* 0x18 - Not affected by Soft Reset */
280 u32 ctrl2; /* MX6, VF610 - Not affected by Soft Reset */
287 u32 rxfir; /* 0x4c - Not affected by Soft Reset */
288 u32 cbt; /* 0x50 - Not affected by Soft Reset */
293 u8 mb[2][512]; /* 0x80 - Not affected by Soft Reset */
294 /* FIFO-mode:
297 * 0x090...0x0df 1-5 reserved
298 * 0x0e0...0x0ff 6-7 8 entry ID table
300 * 0x0e0...0x2df 6-7..37 8..128 entry ID table
305 u32 rximr[64]; /* 0x880 - Not affected by Soft Reset */
307 u32 gfwr_mx6; /* 0x9e0 - MX6 */
327 u32 fdctrl; /* 0xc00 - Not affected by Soft Reset */
328 u32 fdcbt; /* 0xc04 - Not affected by Soft Reset */
476 /* FlexCAN module is essentially modelled as a little-endian IP in most
478 * implemented in a little-endian fashion.
480 * However there are some SoCs (e.g. LS1021A) which implement the FlexCAN
481 * module in a big-endian fashion (i.e the registers as well as the
482 * message buffer areas are implemented in a big-endian way).
484 * In addition, the FlexCAN module can be found on SoCs having ARM or
515 if (WARN_ON(mb_index >= priv->mb_count)) in flexcan_get_mb()
518 bank_size = sizeof(priv->regs->mb[0]) / priv->mb_size; in flexcan_get_mb()
522 mb_index -= bank_size; in flexcan_get_mb()
525 (&priv->regs->mb[bank][priv->mb_size * mb_index]); in flexcan_get_mb()
530 struct flexcan_regs __iomem *regs = priv->regs; in flexcan_low_power_enter_ack()
533 while (timeout-- && !(priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)) in flexcan_low_power_enter_ack()
536 if (!(priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)) in flexcan_low_power_enter_ack()
537 return -ETIMEDOUT; in flexcan_low_power_enter_ack()
544 struct flexcan_regs __iomem *regs = priv->regs; in flexcan_low_power_exit_ack()
547 while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)) in flexcan_low_power_exit_ack()
550 if (priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK) in flexcan_low_power_exit_ack()
551 return -ETIMEDOUT; in flexcan_low_power_exit_ack()
558 struct flexcan_regs __iomem *regs = priv->regs; in flexcan_enable_wakeup_irq()
561 reg_mcr = priv->read(®s->mcr); in flexcan_enable_wakeup_irq()
568 priv->write(reg_mcr, ®s->mcr); in flexcan_enable_wakeup_irq()
573 u8 idx = priv->scu_idx; in flexcan_stop_mode_enable_scfw()
584 return imx_sc_misc_set_control(priv->sc_ipc_handle, rsrc_id, in flexcan_stop_mode_enable_scfw()
590 struct flexcan_regs __iomem *regs = priv->regs; in flexcan_enter_stop_mode()
594 reg_mcr = priv->read(®s->mcr); in flexcan_enter_stop_mode()
596 priv->write(reg_mcr, ®s->mcr); in flexcan_enter_stop_mode()
599 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW) { in flexcan_enter_stop_mode()
604 regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr, in flexcan_enter_stop_mode()
605 1 << priv->stm.req_bit, 1 << priv->stm.req_bit); in flexcan_enter_stop_mode()
613 struct flexcan_regs __iomem *regs = priv->regs; in flexcan_exit_stop_mode()
618 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW) { in flexcan_exit_stop_mode()
623 regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr, in flexcan_exit_stop_mode()
624 1 << priv->stm.req_bit, 0); in flexcan_exit_stop_mode()
627 reg_mcr = priv->read(®s->mcr); in flexcan_exit_stop_mode()
629 priv->write(reg_mcr, ®s->mcr); in flexcan_exit_stop_mode()
636 struct flexcan_regs __iomem *regs = priv->regs; in flexcan_error_irq_enable()
637 u32 reg_ctrl = (priv->reg_ctrl_default | FLEXCAN_CTRL_ERR_MSK); in flexcan_error_irq_enable()
639 priv->write(reg_ctrl, ®s->ctrl); in flexcan_error_irq_enable()
644 struct flexcan_regs __iomem *regs = priv->regs; in flexcan_error_irq_disable()
645 u32 reg_ctrl = (priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_MSK); in flexcan_error_irq_disable()
647 priv->write(reg_ctrl, ®s->ctrl); in flexcan_error_irq_disable()
654 if (priv->clk_ipg) { in flexcan_clks_enable()
655 err = clk_prepare_enable(priv->clk_ipg); in flexcan_clks_enable()
660 if (priv->clk_per) { in flexcan_clks_enable()
661 err = clk_prepare_enable(priv->clk_per); in flexcan_clks_enable()
663 clk_disable_unprepare(priv->clk_ipg); in flexcan_clks_enable()
671 clk_disable_unprepare(priv->clk_per); in flexcan_clks_disable()
672 clk_disable_unprepare(priv->clk_ipg); in flexcan_clks_disable()
677 if (!priv->reg_xceiver) in flexcan_transceiver_enable()
680 return regulator_enable(priv->reg_xceiver); in flexcan_transceiver_enable()
685 if (!priv->reg_xceiver) in flexcan_transceiver_disable()
688 return regulator_disable(priv->reg_xceiver); in flexcan_transceiver_disable()
693 struct flexcan_regs __iomem *regs = priv->regs; in flexcan_chip_enable()
696 reg = priv->read(®s->mcr); in flexcan_chip_enable()
698 priv->write(reg, ®s->mcr); in flexcan_chip_enable()
705 struct flexcan_regs __iomem *regs = priv->regs; in flexcan_chip_disable()
708 reg = priv->read(®s->mcr); in flexcan_chip_disable()
710 priv->write(reg, ®s->mcr); in flexcan_chip_disable()
717 struct flexcan_regs __iomem *regs = priv->regs; in flexcan_chip_freeze()
719 u32 bitrate = priv->can.bittiming.bitrate; in flexcan_chip_freeze()
727 reg = priv->read(®s->mcr); in flexcan_chip_freeze()
729 priv->write(reg, ®s->mcr); in flexcan_chip_freeze()
731 while (timeout-- && !(priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK)) in flexcan_chip_freeze()
734 if (!(priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK)) in flexcan_chip_freeze()
735 return -ETIMEDOUT; in flexcan_chip_freeze()
742 struct flexcan_regs __iomem *regs = priv->regs; in flexcan_chip_unfreeze()
746 reg = priv->read(®s->mcr); in flexcan_chip_unfreeze()
748 priv->write(reg, ®s->mcr); in flexcan_chip_unfreeze()
750 while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK)) in flexcan_chip_unfreeze()
753 if (priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK) in flexcan_chip_unfreeze()
754 return -ETIMEDOUT; in flexcan_chip_unfreeze()
761 struct flexcan_regs __iomem *regs = priv->regs; in flexcan_chip_softreset()
764 priv->write(FLEXCAN_MCR_SOFTRST, ®s->mcr); in flexcan_chip_softreset()
765 while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_SOFTRST)) in flexcan_chip_softreset()
768 if (priv->read(®s->mcr) & FLEXCAN_MCR_SOFTRST) in flexcan_chip_softreset()
769 return -ETIMEDOUT; in flexcan_chip_softreset()
778 struct flexcan_regs __iomem *regs = priv->regs; in __flexcan_get_berr_counter()
779 u32 reg = priv->read(®s->ecr); in __flexcan_get_berr_counter()
781 bec->txerr = (reg >> 0) & 0xff; in __flexcan_get_berr_counter()
782 bec->rxerr = (reg >> 8) & 0xff; in __flexcan_get_berr_counter()
793 err = pm_runtime_get_sync(priv->dev); in flexcan_get_berr_counter()
795 pm_runtime_put_noidle(priv->dev); in flexcan_get_berr_counter()
801 pm_runtime_put(priv->dev); in flexcan_get_berr_counter()
809 struct canfd_frame *cfd = (struct canfd_frame *)skb->data; in flexcan_start_xmit()
812 u32 ctrl = FLEXCAN_MB_CODE_TX_DATA | ((can_fd_len2dlc(cfd->len)) << 16); in flexcan_start_xmit()
820 if (cfd->can_id & CAN_EFF_FLAG) { in flexcan_start_xmit()
821 can_id = cfd->can_id & CAN_EFF_MASK; in flexcan_start_xmit()
824 can_id = (cfd->can_id & CAN_SFF_MASK) << 18; in flexcan_start_xmit()
827 if (cfd->can_id & CAN_RTR_FLAG) in flexcan_start_xmit()
833 if (cfd->flags & CANFD_BRS) in flexcan_start_xmit()
837 for (i = 0; i < cfd->len; i += sizeof(u32)) { in flexcan_start_xmit()
838 data = be32_to_cpup((__be32 *)&cfd->data[i]); in flexcan_start_xmit()
839 priv->write(data, &priv->tx_mb->data[i / sizeof(u32)]); in flexcan_start_xmit()
844 priv->write(can_id, &priv->tx_mb->can_id); in flexcan_start_xmit()
845 priv->write(ctrl, &priv->tx_mb->can_ctrl); in flexcan_start_xmit()
850 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE, in flexcan_start_xmit()
851 &priv->tx_mb_reserved->can_ctrl); in flexcan_start_xmit()
852 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE, in flexcan_start_xmit()
853 &priv->tx_mb_reserved->can_ctrl); in flexcan_start_xmit()
861 struct flexcan_regs __iomem *regs = priv->regs; in flexcan_irq_bus_err()
868 timestamp = priv->read(®s->timer) << 16; in flexcan_irq_bus_err()
874 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; in flexcan_irq_bus_err()
878 cf->data[2] |= CAN_ERR_PROT_BIT1; in flexcan_irq_bus_err()
883 cf->data[2] |= CAN_ERR_PROT_BIT0; in flexcan_irq_bus_err()
888 cf->can_id |= CAN_ERR_ACK; in flexcan_irq_bus_err()
889 cf->data[3] = CAN_ERR_PROT_LOC_ACK; in flexcan_irq_bus_err()
894 cf->data[2] |= CAN_ERR_PROT_BIT; in flexcan_irq_bus_err()
895 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ; in flexcan_irq_bus_err()
900 cf->data[2] |= CAN_ERR_PROT_FORM; in flexcan_irq_bus_err()
905 cf->data[2] |= CAN_ERR_PROT_STUFF; in flexcan_irq_bus_err()
909 priv->can.can_stats.bus_error++; in flexcan_irq_bus_err()
911 dev->stats.rx_errors++; in flexcan_irq_bus_err()
913 dev->stats.tx_errors++; in flexcan_irq_bus_err()
915 err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp); in flexcan_irq_bus_err()
917 dev->stats.rx_fifo_errors++; in flexcan_irq_bus_err()
923 struct flexcan_regs __iomem *regs = priv->regs; in flexcan_irq_state()
948 if (likely(new_state == priv->can.state)) in flexcan_irq_state()
951 timestamp = priv->read(®s->timer) << 16; in flexcan_irq_state()
962 err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp); in flexcan_irq_state()
964 dev->stats.rx_fifo_errors++; in flexcan_irq_state()
972 reg = (u64)priv->read(addr - 4) << 32; in flexcan_read64_mask()
974 reg |= priv->read(addr); in flexcan_read64_mask()
982 priv->write(upper_32_bits(val), addr - 4); in flexcan_write64()
984 priv->write(lower_32_bits(val), addr); in flexcan_write64()
989 return flexcan_read64_mask(priv, &priv->regs->iflag1, priv->rx_mask); in flexcan_read_reg_iflag_rx()
994 return flexcan_read64_mask(priv, &priv->regs->iflag1, priv->tx_mask); in flexcan_read_reg_iflag_tx()
1007 struct flexcan_regs __iomem *regs = priv->regs; in flexcan_mailbox_read()
1015 skb = ERR_PTR(-ENOBUFS); in flexcan_mailbox_read()
1021 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) { in flexcan_mailbox_read()
1025 reg_ctrl = priv->read(&mb->can_ctrl); in flexcan_mailbox_read()
1036 offload->dev->stats.rx_over_errors++; in flexcan_mailbox_read()
1037 offload->dev->stats.rx_errors++; in flexcan_mailbox_read()
1040 reg_iflag1 = priv->read(®s->iflag1); in flexcan_mailbox_read()
1044 reg_ctrl = priv->read(&mb->can_ctrl); in flexcan_mailbox_read()
1048 skb = alloc_canfd_skb(offload->dev, &cfd); in flexcan_mailbox_read()
1050 skb = alloc_can_skb(offload->dev, (struct can_frame **)&cfd); in flexcan_mailbox_read()
1052 skb = ERR_PTR(-ENOMEM); in flexcan_mailbox_read()
1059 reg_id = priv->read(&mb->can_id); in flexcan_mailbox_read()
1061 cfd->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG; in flexcan_mailbox_read()
1063 cfd->can_id = (reg_id >> 18) & CAN_SFF_MASK; in flexcan_mailbox_read()
1066 cfd->len = can_fd_dlc2len((reg_ctrl >> 16) & 0xf); in flexcan_mailbox_read()
1069 cfd->flags |= CANFD_BRS; in flexcan_mailbox_read()
1071 cfd->len = can_cc_dlc2len((reg_ctrl >> 16) & 0xf); in flexcan_mailbox_read()
1074 cfd->can_id |= CAN_RTR_FLAG; in flexcan_mailbox_read()
1078 cfd->flags |= CANFD_ESI; in flexcan_mailbox_read()
1080 for (i = 0; i < cfd->len; i += sizeof(u32)) { in flexcan_mailbox_read()
1081 __be32 data = cpu_to_be32(priv->read(&mb->data[i / sizeof(u32)])); in flexcan_mailbox_read()
1082 *(__be32 *)(cfd->data + i) = data; in flexcan_mailbox_read()
1086 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) in flexcan_mailbox_read()
1087 flexcan_write64(priv, FLEXCAN_IFLAG_MB(n), ®s->iflag1); in flexcan_mailbox_read()
1089 priv->write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->iflag1); in flexcan_mailbox_read()
1095 priv->read(®s->timer); in flexcan_mailbox_read()
1103 struct net_device_stats *stats = &dev->stats; in flexcan_irq()
1105 struct flexcan_regs __iomem *regs = priv->regs; in flexcan_irq()
1109 enum can_state last_state = priv->can.state; in flexcan_irq()
1112 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) { in flexcan_irq()
1118 ret = can_rx_offload_irq_offload_timestamp(&priv->offload, in flexcan_irq()
1126 reg_iflag1 = priv->read(®s->iflag1); in flexcan_irq()
1129 can_rx_offload_irq_offload_fifo(&priv->offload); in flexcan_irq()
1135 priv->write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, in flexcan_irq()
1136 ®s->iflag1); in flexcan_irq()
1137 dev->stats.rx_over_errors++; in flexcan_irq()
1138 dev->stats.rx_errors++; in flexcan_irq()
1145 if (reg_iflag_tx & priv->tx_mask) { in flexcan_irq()
1146 u32 reg_ctrl = priv->read(&priv->tx_mb->can_ctrl); in flexcan_irq()
1149 stats->tx_bytes += in flexcan_irq()
1150 can_rx_offload_get_echo_skb(&priv->offload, 0, in flexcan_irq()
1152 stats->tx_packets++; in flexcan_irq()
1156 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE, in flexcan_irq()
1157 &priv->tx_mb->can_ctrl); in flexcan_irq()
1158 flexcan_write64(priv, priv->tx_mask, ®s->iflag1); in flexcan_irq()
1162 reg_esr = priv->read(®s->esr); in flexcan_irq()
1167 priv->write(reg_esr & (FLEXCAN_ESR_ALL_INT | FLEXCAN_ESR_WAK_INT), ®s->esr); in flexcan_irq()
1172 (priv->devtype_data->quirks & (FLEXCAN_QUIRK_BROKEN_WERR_STATE | in flexcan_irq()
1176 /* bus error IRQ - handle if bus error reporting is activated */ in flexcan_irq()
1178 (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) in flexcan_irq()
1182 * bus error reporting is de-activated and in flexcan_irq()
1184 * +--------------------------------------------------------------+ in flexcan_irq()
1185 * | +----------------------------------------------+ [stopped / | in flexcan_irq()
1186 * | | | sleeping] -+ in flexcan_irq()
1187 * +-+-> active <-> warning <-> passive -> bus off -+ in flexcan_irq()
1193 if ((last_state != priv->can.state) && in flexcan_irq()
1194 (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_PERR_STATE) && in flexcan_irq()
1195 !(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) { in flexcan_irq()
1196 switch (priv->can.state) { in flexcan_irq()
1198 if (priv->devtype_data->quirks & in flexcan_irq()
1220 can_rx_offload_irq_finish(&priv->offload); in flexcan_irq()
1228 const struct can_bittiming *bt = &priv->can.bittiming; in flexcan_set_bittiming_ctrl()
1229 struct flexcan_regs __iomem *regs = priv->regs; in flexcan_set_bittiming_ctrl()
1232 reg = priv->read(®s->ctrl); in flexcan_set_bittiming_ctrl()
1239 reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) | in flexcan_set_bittiming_ctrl()
1240 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) | in flexcan_set_bittiming_ctrl()
1241 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) | in flexcan_set_bittiming_ctrl()
1242 FLEXCAN_CTRL_RJW(bt->sjw - 1) | in flexcan_set_bittiming_ctrl()
1243 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1); in flexcan_set_bittiming_ctrl()
1246 priv->write(reg, ®s->ctrl); in flexcan_set_bittiming_ctrl()
1250 priv->read(®s->mcr), priv->read(®s->ctrl)); in flexcan_set_bittiming_ctrl()
1256 struct can_bittiming *bt = &priv->can.bittiming; in flexcan_set_bittiming_cbt()
1257 struct can_bittiming *dbt = &priv->can.data_bittiming; in flexcan_set_bittiming_cbt()
1258 struct flexcan_regs __iomem *regs = priv->regs; in flexcan_set_bittiming_cbt()
1268 if (bt->phase_seg1 > 0x20) { in flexcan_set_bittiming_cbt()
1269 bt->prop_seg += (bt->phase_seg1 - 0x20); in flexcan_set_bittiming_cbt()
1270 bt->phase_seg1 = 0x20; in flexcan_set_bittiming_cbt()
1274 FIELD_PREP(FLEXCAN_CBT_EPRESDIV_MASK, bt->brp - 1) | in flexcan_set_bittiming_cbt()
1275 FIELD_PREP(FLEXCAN_CBT_ERJW_MASK, bt->sjw - 1) | in flexcan_set_bittiming_cbt()
1276 FIELD_PREP(FLEXCAN_CBT_EPROPSEG_MASK, bt->prop_seg - 1) | in flexcan_set_bittiming_cbt()
1277 FIELD_PREP(FLEXCAN_CBT_EPSEG1_MASK, bt->phase_seg1 - 1) | in flexcan_set_bittiming_cbt()
1278 FIELD_PREP(FLEXCAN_CBT_EPSEG2_MASK, bt->phase_seg2 - 1); in flexcan_set_bittiming_cbt()
1281 priv->write(reg_cbt, ®s->cbt); in flexcan_set_bittiming_cbt()
1283 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) { in flexcan_set_bittiming_cbt()
1286 if (bt->brp != dbt->brp) in flexcan_set_bittiming_cbt()
1288 dbt->brp, bt->brp); in flexcan_set_bittiming_cbt()
1298 if (dbt->phase_seg1 > 0x8) { in flexcan_set_bittiming_cbt()
1299 dbt->prop_seg += (dbt->phase_seg1 - 0x8); in flexcan_set_bittiming_cbt()
1300 dbt->phase_seg1 = 0x8; in flexcan_set_bittiming_cbt()
1303 reg_fdcbt = priv->read(®s->fdcbt); in flexcan_set_bittiming_cbt()
1310 reg_fdcbt |= FIELD_PREP(FLEXCAN_FDCBT_FPRESDIV_MASK, dbt->brp - 1) | in flexcan_set_bittiming_cbt()
1311 FIELD_PREP(FLEXCAN_FDCBT_FRJW_MASK, dbt->sjw - 1) | in flexcan_set_bittiming_cbt()
1312 FIELD_PREP(FLEXCAN_FDCBT_FPROPSEG_MASK, dbt->prop_seg) | in flexcan_set_bittiming_cbt()
1313 FIELD_PREP(FLEXCAN_FDCBT_FPSEG1_MASK, dbt->phase_seg1 - 1) | in flexcan_set_bittiming_cbt()
1314 FIELD_PREP(FLEXCAN_FDCBT_FPSEG2_MASK, dbt->phase_seg2 - 1); in flexcan_set_bittiming_cbt()
1317 priv->write(reg_fdcbt, ®s->fdcbt); in flexcan_set_bittiming_cbt()
1320 reg_ctrl2 = priv->read(®s->ctrl2); in flexcan_set_bittiming_cbt()
1322 if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO)) in flexcan_set_bittiming_cbt()
1326 priv->write(reg_ctrl2, ®s->ctrl2); in flexcan_set_bittiming_cbt()
1330 reg_fdctrl = priv->read(®s->fdctrl); in flexcan_set_bittiming_cbt()
1334 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) { in flexcan_set_bittiming_cbt()
1337 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) { in flexcan_set_bittiming_cbt()
1343 ((dbt->phase_seg1 - 1) + in flexcan_set_bittiming_cbt()
1344 dbt->prop_seg + 2) * in flexcan_set_bittiming_cbt()
1345 ((dbt->brp - 1 ) + 1)); in flexcan_set_bittiming_cbt()
1350 priv->write(reg_fdctrl, ®s->fdctrl); in flexcan_set_bittiming_cbt()
1354 priv->read(®s->mcr), priv->read(®s->ctrl), in flexcan_set_bittiming_cbt()
1355 priv->read(®s->ctrl2), priv->read(®s->fdctrl), in flexcan_set_bittiming_cbt()
1356 priv->read(®s->cbt), priv->read(®s->fdcbt)); in flexcan_set_bittiming_cbt()
1362 struct flexcan_regs __iomem *regs = priv->regs; in flexcan_set_bittiming()
1365 reg = priv->read(®s->ctrl); in flexcan_set_bittiming()
1369 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) in flexcan_set_bittiming()
1371 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) in flexcan_set_bittiming()
1373 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) in flexcan_set_bittiming()
1377 priv->write(reg, ®s->ctrl); in flexcan_set_bittiming()
1379 if (priv->can.ctrlmode_supported & CAN_CTRLMODE_FD) in flexcan_set_bittiming()
1388 struct flexcan_regs __iomem *regs = priv->regs; in flexcan_ram_init()
1399 reg_ctrl2 = priv->read(®s->ctrl2); in flexcan_ram_init()
1401 priv->write(reg_ctrl2, ®s->ctrl2); in flexcan_ram_init()
1403 memset_io(®s->mb[0][0], 0, in flexcan_ram_init()
1404 offsetof(struct flexcan_regs, rx_smb1[3]) - in flexcan_ram_init()
1407 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) in flexcan_ram_init()
1408 memset_io(®s->tx_smb_fd[0], 0, in flexcan_ram_init()
1409 offsetof(struct flexcan_regs, rx_smb1_fd[17]) - in flexcan_ram_init()
1413 priv->write(reg_ctrl2, ®s->ctrl2); in flexcan_ram_init()
1421 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) in flexcan_rx_offload_setup()
1422 priv->mb_size = sizeof(struct flexcan_mb) + CANFD_MAX_DLEN; in flexcan_rx_offload_setup()
1424 priv->mb_size = sizeof(struct flexcan_mb) + CAN_MAX_DLEN; in flexcan_rx_offload_setup()
1426 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_NR_MB_16) in flexcan_rx_offload_setup()
1427 priv->mb_count = 16; in flexcan_rx_offload_setup()
1429 priv->mb_count = (sizeof(priv->regs->mb[0]) / priv->mb_size) + in flexcan_rx_offload_setup()
1430 (sizeof(priv->regs->mb[1]) / priv->mb_size); in flexcan_rx_offload_setup()
1432 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) in flexcan_rx_offload_setup()
1433 priv->tx_mb_reserved = in flexcan_rx_offload_setup()
1436 priv->tx_mb_reserved = in flexcan_rx_offload_setup()
1438 priv->tx_mb_idx = priv->mb_count - 1; in flexcan_rx_offload_setup()
1439 priv->tx_mb = flexcan_get_mb(priv, priv->tx_mb_idx); in flexcan_rx_offload_setup()
1440 priv->tx_mask = FLEXCAN_IFLAG_MB(priv->tx_mb_idx); in flexcan_rx_offload_setup()
1442 priv->offload.mailbox_read = flexcan_mailbox_read; in flexcan_rx_offload_setup()
1444 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) { in flexcan_rx_offload_setup()
1445 priv->offload.mb_first = FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST; in flexcan_rx_offload_setup()
1446 priv->offload.mb_last = priv->mb_count - 2; in flexcan_rx_offload_setup()
1448 priv->rx_mask = GENMASK_ULL(priv->offload.mb_last, in flexcan_rx_offload_setup()
1449 priv->offload.mb_first); in flexcan_rx_offload_setup()
1450 err = can_rx_offload_add_timestamp(dev, &priv->offload); in flexcan_rx_offload_setup()
1452 priv->rx_mask = FLEXCAN_IFLAG_RX_FIFO_OVERFLOW | in flexcan_rx_offload_setup()
1454 err = can_rx_offload_add_fifo(dev, &priv->offload, in flexcan_rx_offload_setup()
1464 struct flexcan_regs __iomem *regs = priv->regs; in flexcan_chip_interrupts_enable()
1467 disable_irq(dev->irq); in flexcan_chip_interrupts_enable()
1468 priv->write(priv->reg_ctrl_default, ®s->ctrl); in flexcan_chip_interrupts_enable()
1469 reg_imask = priv->rx_mask | priv->tx_mask; in flexcan_chip_interrupts_enable()
1470 priv->write(upper_32_bits(reg_imask), ®s->imask2); in flexcan_chip_interrupts_enable()
1471 priv->write(lower_32_bits(reg_imask), ®s->imask1); in flexcan_chip_interrupts_enable()
1472 enable_irq(dev->irq); in flexcan_chip_interrupts_enable()
1478 struct flexcan_regs __iomem *regs = priv->regs; in flexcan_chip_interrupts_disable()
1480 priv->write(0, ®s->imask2); in flexcan_chip_interrupts_disable()
1481 priv->write(0, ®s->imask1); in flexcan_chip_interrupts_disable()
1482 priv->write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL, in flexcan_chip_interrupts_disable()
1483 ®s->ctrl); in flexcan_chip_interrupts_disable()
1494 struct flexcan_regs __iomem *regs = priv->regs; in flexcan_chip_start()
1509 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_SUPPORT_ECC) in flexcan_chip_start()
1527 reg_mcr = priv->read(®s->mcr); in flexcan_chip_start()
1530 FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_MAXMB(priv->tx_mb_idx); in flexcan_chip_start()
1535 * - disable for timestamp mode in flexcan_chip_start()
1536 * - enable for FIFO mode in flexcan_chip_start()
1538 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) in flexcan_chip_start()
1548 * earlier versions of flexcan block guide. in flexcan_chip_start()
1551 * - enable Self Reception for loopback mode in flexcan_chip_start()
1553 * - disable for normal operation in flexcan_chip_start()
1555 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) in flexcan_chip_start()
1560 /* MCR - CAN-FD */ in flexcan_chip_start()
1561 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) in flexcan_chip_start()
1567 priv->write(reg_mcr, ®s->mcr); in flexcan_chip_start()
1580 reg_ctrl = priv->read(®s->ctrl); in flexcan_chip_start()
1586 * on most Flexcan cores, too. Otherwise we don't get in flexcan_chip_start()
1589 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_WERR_STATE || in flexcan_chip_start()
1590 priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) in flexcan_chip_start()
1596 priv->reg_ctrl_default = reg_ctrl; in flexcan_chip_start()
1600 priv->write(reg_ctrl, ®s->ctrl); in flexcan_chip_start()
1602 if ((priv->devtype_data->quirks & FLEXCAN_QUIRK_ENABLE_EACEN_RRS)) { in flexcan_chip_start()
1603 reg_ctrl2 = priv->read(®s->ctrl2); in flexcan_chip_start()
1605 priv->write(reg_ctrl2, ®s->ctrl2); in flexcan_chip_start()
1608 if (priv->can.ctrlmode_supported & CAN_CTRLMODE_FD) { in flexcan_chip_start()
1611 reg_fdctrl = priv->read(®s->fdctrl); in flexcan_chip_start()
1615 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) { in flexcan_chip_start()
1631 priv->write(reg_fdctrl, ®s->fdctrl); in flexcan_chip_start()
1634 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) { in flexcan_chip_start()
1635 for (i = priv->offload.mb_first; i <= priv->offload.mb_last; i++) { in flexcan_chip_start()
1637 priv->write(FLEXCAN_MB_CODE_RX_EMPTY, in flexcan_chip_start()
1638 &mb->can_ctrl); in flexcan_chip_start()
1642 for (i = FLEXCAN_TX_MB_RESERVED_OFF_FIFO; i < priv->mb_count; i++) { in flexcan_chip_start()
1644 priv->write(FLEXCAN_MB_CODE_RX_INACTIVE, in flexcan_chip_start()
1645 &mb->can_ctrl); in flexcan_chip_start()
1650 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE, in flexcan_chip_start()
1651 &priv->tx_mb_reserved->can_ctrl); in flexcan_chip_start()
1654 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE, in flexcan_chip_start()
1655 &priv->tx_mb->can_ctrl); in flexcan_chip_start()
1658 priv->write(0x0, ®s->rxgmask); in flexcan_chip_start()
1659 priv->write(0x0, ®s->rx14mask); in flexcan_chip_start()
1660 priv->write(0x0, ®s->rx15mask); in flexcan_chip_start()
1662 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_RXFG) in flexcan_chip_start()
1663 priv->write(0x0, ®s->rxfgmask); in flexcan_chip_start()
1666 for (i = 0; i < priv->mb_count; i++) in flexcan_chip_start()
1667 priv->write(0, ®s->rximr[i]); in flexcan_chip_start()
1669 /* On Vybrid, disable non-correctable errors interrupt and in flexcan_chip_start()
1676 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_MECR) { in flexcan_chip_start()
1679 * MECR register (step 1 - 5) in flexcan_chip_start()
1684 reg_ctrl2 = priv->read(®s->ctrl2); in flexcan_chip_start()
1686 priv->write(reg_ctrl2, ®s->ctrl2); in flexcan_chip_start()
1689 reg_mecr = priv->read(®s->mecr); in flexcan_chip_start()
1691 priv->write(reg_mecr, ®s->mecr); in flexcan_chip_start()
1696 priv->write(reg_mecr, ®s->mecr); in flexcan_chip_start()
1702 priv->write(reg_mecr, ®s->mecr); in flexcan_chip_start()
1705 priv->write(reg_ctrl2, ®s->ctrl2); in flexcan_chip_start()
1713 priv->can.state = CAN_STATE_ERROR_ACTIVE; in flexcan_chip_start()
1717 priv->read(®s->mcr), priv->read(®s->ctrl)); in flexcan_chip_start()
1743 priv->can.state = CAN_STATE_STOPPED; in __flexcan_chip_stop()
1768 if ((priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) && in flexcan_open()
1769 (priv->can.ctrlmode & CAN_CTRLMODE_FD)) { in flexcan_open()
1770 netdev_err(dev, "Three Samples mode and CAN-FD mode can't be used together\n"); in flexcan_open()
1771 return -EINVAL; in flexcan_open()
1774 err = pm_runtime_get_sync(priv->dev); in flexcan_open()
1776 pm_runtime_put_noidle(priv->dev); in flexcan_open()
1796 can_rx_offload_enable(&priv->offload); in flexcan_open()
1798 err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev); in flexcan_open()
1802 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_NR_IRQ_3) { in flexcan_open()
1803 err = request_irq(priv->irq_boff, in flexcan_open()
1804 flexcan_irq, IRQF_SHARED, dev->name, dev); in flexcan_open()
1808 err = request_irq(priv->irq_err, in flexcan_open()
1809 flexcan_irq, IRQF_SHARED, dev->name, dev); in flexcan_open()
1823 free_irq(priv->irq_boff, dev); in flexcan_open()
1825 free_irq(dev->irq, dev); in flexcan_open()
1827 can_rx_offload_disable(&priv->offload); in flexcan_open()
1830 can_rx_offload_del(&priv->offload); in flexcan_open()
1836 pm_runtime_put(priv->dev); in flexcan_open()
1848 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_NR_IRQ_3) { in flexcan_close()
1849 free_irq(priv->irq_err, dev); in flexcan_close()
1850 free_irq(priv->irq_boff, dev); in flexcan_close()
1853 free_irq(dev->irq, dev); in flexcan_close()
1854 can_rx_offload_disable(&priv->offload); in flexcan_close()
1857 can_rx_offload_del(&priv->offload); in flexcan_close()
1861 pm_runtime_put(priv->dev); in flexcan_close()
1884 return -EOPNOTSUPP; in flexcan_set_mode()
1900 struct flexcan_regs __iomem *regs = priv->regs; in register_flexcandev()
1912 reg = priv->read(®s->ctrl); in register_flexcandev()
1913 if (priv->clk_src) in register_flexcandev()
1917 priv->write(reg, ®s->ctrl); in register_flexcandev()
1929 reg = priv->read(®s->mcr); in register_flexcandev()
1931 priv->write(reg, ®s->mcr); in register_flexcandev()
1938 reg = priv->read(®s->mcr); in register_flexcandev()
1941 err = -ENODEV; in register_flexcandev()
1953 pm_runtime_put(priv->dev); in register_flexcandev()
1972 struct device_node *np = pdev->dev.of_node; in flexcan_setup_stop_mode_gpr()
1980 return -EINVAL; in flexcan_setup_stop_mode_gpr()
1985 ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val, in flexcan_setup_stop_mode_gpr()
1988 dev_dbg(&pdev->dev, "no stop-mode property\n"); in flexcan_setup_stop_mode_gpr()
1995 dev_dbg(&pdev->dev, "could not find gpr node by phandle\n"); in flexcan_setup_stop_mode_gpr()
1996 return -ENODEV; in flexcan_setup_stop_mode_gpr()
2000 priv->stm.gpr = syscon_node_to_regmap(gpr_np); in flexcan_setup_stop_mode_gpr()
2001 if (IS_ERR(priv->stm.gpr)) { in flexcan_setup_stop_mode_gpr()
2002 dev_dbg(&pdev->dev, "could not find gpr regmap\n"); in flexcan_setup_stop_mode_gpr()
2003 ret = PTR_ERR(priv->stm.gpr); in flexcan_setup_stop_mode_gpr()
2007 priv->stm.req_gpr = out_val[1]; in flexcan_setup_stop_mode_gpr()
2008 priv->stm.req_bit = out_val[2]; in flexcan_setup_stop_mode_gpr()
2010 dev_dbg(&pdev->dev, in flexcan_setup_stop_mode_gpr()
2012 gpr_np->full_name, priv->stm.req_gpr, priv->stm.req_bit); in flexcan_setup_stop_mode_gpr()
2028 ret = of_property_read_u8(pdev->dev.of_node, "fsl,scu-index", &scu_idx); in flexcan_setup_stop_mode_scfw()
2030 dev_dbg(&pdev->dev, "failed to get scu index\n"); in flexcan_setup_stop_mode_scfw()
2035 priv->scu_idx = scu_idx; in flexcan_setup_stop_mode_scfw()
2037 /* this function could be deferred probe, return -EPROBE_DEFER */ in flexcan_setup_stop_mode_scfw()
2038 return imx_scu_get_handle(&priv->sc_ipc_handle); in flexcan_setup_stop_mode_scfw()
2041 /* flexcan_setup_stop_mode - Setup stop mode for wakeup
2054 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW) in flexcan_setup_stop_mode()
2056 else if (priv->devtype_data->quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR) in flexcan_setup_stop_mode()
2065 device_set_wakeup_capable(&pdev->dev, true); in flexcan_setup_stop_mode()
2067 if (of_property_read_bool(pdev->dev.of_node, "wakeup-source")) in flexcan_setup_stop_mode()
2068 device_set_wakeup_enable(&pdev->dev, true); in flexcan_setup_stop_mode()
2074 { .compatible = "fsl,imx8qm-flexcan", .data = &fsl_imx8qm_devtype_data, },
2075 { .compatible = "fsl,imx8mp-flexcan", .data = &fsl_imx8mp_devtype_data, },
2076 { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
2077 { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
2078 { .compatible = "fsl,imx53-flexcan", .data = &fsl_imx25_devtype_data, },
2079 { .compatible = "fsl,imx35-flexcan", .data = &fsl_imx25_devtype_data, },
2080 { .compatible = "fsl,imx25-flexcan", .data = &fsl_imx25_devtype_data, },
2081 { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
2082 { .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
2083 { .compatible = "fsl,ls1021ar2-flexcan", .data = &fsl_ls1021a_r2_devtype_data, },
2084 { .compatible = "fsl,lx2160ar1-flexcan", .data = &fsl_lx2160a_r1_devtype_data, },
2091 .name = "flexcan-mcf5441x",
2113 reg_xceiver = devm_regulator_get_optional(&pdev->dev, "xceiver"); in flexcan_probe()
2114 if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER) in flexcan_probe()
2115 return -EPROBE_DEFER; in flexcan_probe()
2116 else if (PTR_ERR(reg_xceiver) == -ENODEV) in flexcan_probe()
2121 if (pdev->dev.of_node) { in flexcan_probe()
2122 of_property_read_u32(pdev->dev.of_node, in flexcan_probe()
2123 "clock-frequency", &clock_freq); in flexcan_probe()
2124 of_property_read_u8(pdev->dev.of_node, in flexcan_probe()
2125 "fsl,clk-source", &clk_src); in flexcan_probe()
2127 pdata = dev_get_platdata(&pdev->dev); in flexcan_probe()
2129 clock_freq = pdata->clock_frequency; in flexcan_probe()
2130 clk_src = pdata->clk_src; in flexcan_probe()
2135 clk_ipg = devm_clk_get(&pdev->dev, "ipg"); in flexcan_probe()
2137 dev_err(&pdev->dev, "no ipg clock defined\n"); in flexcan_probe()
2141 clk_per = devm_clk_get(&pdev->dev, "per"); in flexcan_probe()
2143 dev_err(&pdev->dev, "no per clock defined\n"); in flexcan_probe()
2151 return -ENODEV; in flexcan_probe()
2157 of_id = of_match_device(flexcan_of_match, &pdev->dev); in flexcan_probe()
2159 devtype_data = of_id->data; in flexcan_probe()
2160 else if (platform_get_device_id(pdev)->driver_data) in flexcan_probe()
2162 platform_get_device_id(pdev)->driver_data; in flexcan_probe()
2164 return -ENODEV; in flexcan_probe()
2166 if ((devtype_data->quirks & FLEXCAN_QUIRK_SUPPORT_FD) && in flexcan_probe()
2167 !(devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)) { in flexcan_probe()
2168 dev_err(&pdev->dev, "CAN-FD mode doesn't work with FIFO mode!\n"); in flexcan_probe()
2169 return -EINVAL; in flexcan_probe()
2174 return -ENOMEM; in flexcan_probe()
2177 SET_NETDEV_DEV(dev, &pdev->dev); in flexcan_probe()
2179 dev->netdev_ops = &flexcan_netdev_ops; in flexcan_probe()
2180 dev->irq = irq; in flexcan_probe()
2181 dev->flags |= IFF_ECHO; in flexcan_probe()
2185 if (of_property_read_bool(pdev->dev.of_node, "big-endian") || in flexcan_probe()
2186 devtype_data->quirks & FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN) { in flexcan_probe()
2187 priv->read = flexcan_read_be; in flexcan_probe()
2188 priv->write = flexcan_write_be; in flexcan_probe()
2190 priv->read = flexcan_read_le; in flexcan_probe()
2191 priv->write = flexcan_write_le; in flexcan_probe()
2194 priv->dev = &pdev->dev; in flexcan_probe()
2195 priv->can.clock.freq = clock_freq; in flexcan_probe()
2196 priv->can.do_set_mode = flexcan_set_mode; in flexcan_probe()
2197 priv->can.do_get_berr_counter = flexcan_get_berr_counter; in flexcan_probe()
2198 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | in flexcan_probe()
2201 priv->regs = regs; in flexcan_probe()
2202 priv->clk_ipg = clk_ipg; in flexcan_probe()
2203 priv->clk_per = clk_per; in flexcan_probe()
2204 priv->clk_src = clk_src; in flexcan_probe()
2205 priv->devtype_data = devtype_data; in flexcan_probe()
2206 priv->reg_xceiver = reg_xceiver; in flexcan_probe()
2208 if (devtype_data->quirks & FLEXCAN_QUIRK_NR_IRQ_3) { in flexcan_probe()
2209 priv->irq_boff = platform_get_irq(pdev, 1); in flexcan_probe()
2210 if (priv->irq_boff <= 0) { in flexcan_probe()
2211 err = -ENODEV; in flexcan_probe()
2214 priv->irq_err = platform_get_irq(pdev, 2); in flexcan_probe()
2215 if (priv->irq_err <= 0) { in flexcan_probe()
2216 err = -ENODEV; in flexcan_probe()
2221 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_SUPPORT_FD) { in flexcan_probe()
2222 priv->can.ctrlmode_supported |= CAN_CTRLMODE_FD | in flexcan_probe()
2224 priv->can.bittiming_const = &flexcan_fd_bittiming_const; in flexcan_probe()
2225 priv->can.data_bittiming_const = in flexcan_probe()
2228 priv->can.bittiming_const = &flexcan_bittiming_const; in flexcan_probe()
2231 pm_runtime_get_noresume(&pdev->dev); in flexcan_probe()
2232 pm_runtime_set_active(&pdev->dev); in flexcan_probe()
2233 pm_runtime_enable(&pdev->dev); in flexcan_probe()
2237 dev_err(&pdev->dev, "registering netdev failed\n"); in flexcan_probe()
2243 if (err != -EPROBE_DEFER) in flexcan_probe()
2244 dev_err(&pdev->dev, "setup stop mode failed\n"); in flexcan_probe()
2256 pm_runtime_put_noidle(&pdev->dev); in flexcan_probe()
2257 pm_runtime_disable(&pdev->dev); in flexcan_probe()
2267 device_set_wakeup_enable(&pdev->dev, false); in flexcan_remove()
2268 device_set_wakeup_capable(&pdev->dev, false); in flexcan_remove()
2270 pm_runtime_disable(&pdev->dev); in flexcan_remove()
2287 enable_irq_wake(dev->irq); in flexcan_suspend()
2305 priv->can.state = CAN_STATE_SLEEPING; in flexcan_suspend()
2316 priv->can.state = CAN_STATE_ERROR_ACTIVE; in flexcan_resume()
2321 disable_irq_wake(dev->irq); in flexcan_resume()
2417 "Marc Kleine-Budde <kernel@pengutronix.de>");
2419 MODULE_DESCRIPTION("CAN port driver for flexcan based chip");