Lines Matching defs:flexcan_regs
264 struct flexcan_regs { struct
265 u32 mcr; /* 0x00 */
266 u32 ctrl; /* 0x04 - Not affected by Soft Reset */
267 u32 timer; /* 0x08 */
268 u32 tcr; /* 0x0c */
269 u32 rxgmask; /* 0x10 - Not affected by Soft Reset */
270 u32 rx14mask; /* 0x14 - Not affected by Soft Reset */
271 u32 rx15mask; /* 0x18 - Not affected by Soft Reset */
272 u32 ecr; /* 0x1c */
273 u32 esr; /* 0x20 */
274 u32 imask2; /* 0x24 */
275 u32 imask1; /* 0x28 */
276 u32 iflag2; /* 0x2c */
277 u32 iflag1; /* 0x30 */
278 union { /* 0x34 */
282 u32 esr2; /* 0x38 */
283 u32 imeur; /* 0x3c */
284 u32 lrfr; /* 0x40 */
285 u32 crcr; /* 0x44 */
286 u32 rxfgmask; /* 0x48 */
287 u32 rxfir; /* 0x4c - Not affected by Soft Reset */
288 u32 cbt; /* 0x50 - Not affected by Soft Reset */
289 u32 _reserved2; /* 0x54 */
290 u32 dbg1; /* 0x58 */
291 u32 dbg2; /* 0x5c */
292 u32 _reserved3[8]; /* 0x60 */
293 u8 mb[2][512]; /* 0x80 - Not affected by Soft Reset */
304 u32 _reserved4[256]; /* 0x480 */
305 u32 rximr[64]; /* 0x880 - Not affected by Soft Reset */
306 u32 _reserved5[24]; /* 0x980 */
307 u32 gfwr_mx6; /* 0x9e0 - MX6 */
308 u32 _reserved6[39]; /* 0x9e4 */
309 u32 _rxfir[6]; /* 0xa80 */
310 u32 _reserved8[2]; /* 0xa98 */
311 u32 _rxmgmask; /* 0xaa0 */
312 u32 _rxfgmask; /* 0xaa4 */
336 static_assert(sizeof(struct flexcan_regs) == 0x4 * 18 + 0xfb8); argument