Lines Matching refs:nandc
203 #define dev_cmd_reg_addr(nandc, reg) ((nandc)->props->dev_cmd_reg_start + (reg)) argument
489 static void free_bam_transaction(struct qcom_nand_controller *nandc) in free_bam_transaction() argument
491 struct bam_transaction *bam_txn = nandc->bam_txn; in free_bam_transaction()
493 devm_kfree(nandc->dev, bam_txn); in free_bam_transaction()
498 alloc_bam_transaction(struct qcom_nand_controller *nandc) in alloc_bam_transaction() argument
502 unsigned int num_cw = nandc->max_cwperpage; in alloc_bam_transaction()
511 bam_txn_buf = devm_kzalloc(nandc->dev, bam_txn_size, GFP_KERNEL); in alloc_bam_transaction()
534 static void clear_bam_transaction(struct qcom_nand_controller *nandc) in clear_bam_transaction() argument
536 struct bam_transaction *bam_txn = nandc->bam_txn; in clear_bam_transaction()
538 if (!nandc->props->is_bam) in clear_bam_transaction()
552 sg_init_table(bam_txn->cmd_sgl, nandc->max_cwperpage * in clear_bam_transaction()
554 sg_init_table(bam_txn->data_sgl, nandc->max_cwperpage * in clear_bam_transaction()
590 static inline u32 nandc_read(struct qcom_nand_controller *nandc, int offset) in nandc_read() argument
592 return ioread32(nandc->base + offset); in nandc_read()
595 static inline void nandc_write(struct qcom_nand_controller *nandc, int offset, in nandc_write() argument
598 iowrite32(val, nandc->base + offset); in nandc_write()
601 static inline void nandc_read_buffer_sync(struct qcom_nand_controller *nandc, in nandc_read_buffer_sync() argument
604 if (!nandc->props->is_bam) in nandc_read_buffer_sync()
608 dma_sync_single_for_cpu(nandc->dev, nandc->reg_read_dma, in nandc_read_buffer_sync()
610 sizeof(*nandc->reg_read_buf), in nandc_read_buffer_sync()
613 dma_sync_single_for_device(nandc->dev, nandc->reg_read_dma, in nandc_read_buffer_sync()
615 sizeof(*nandc->reg_read_buf), in nandc_read_buffer_sync()
676 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in nandc_set_reg() local
677 struct nandc_regs *regs = nandc->regs; in nandc_set_reg()
696 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in nandc_set_read_loc() local
700 if (nandc->props->qpic_v2 && qcom_nandc_is_last_cw(ecc, cw)) in nandc_set_read_loc()
705 if (nandc->props->qpic_v2 && qcom_nandc_is_last_cw(ecc, cw)) in nandc_set_read_loc()
737 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in update_rw_regs() local
766 if (!nandc->props->qpic_v2) in update_rw_regs()
782 static int prepare_bam_async_desc(struct qcom_nand_controller *nandc, in prepare_bam_async_desc() argument
790 struct bam_transaction *bam_txn = nandc->bam_txn; in prepare_bam_async_desc()
798 if (chan == nandc->cmd_chan) { in prepare_bam_async_desc()
804 } else if (chan == nandc->tx_chan) { in prepare_bam_async_desc()
819 ret = dma_map_sg(nandc->dev, sgl, sgl_cnt, desc->dir); in prepare_bam_async_desc()
821 dev_err(nandc->dev, "failure in mapping desc\n"); in prepare_bam_async_desc()
833 dev_err(nandc->dev, "failure in prep desc\n"); in prepare_bam_async_desc()
834 dma_unmap_sg(nandc->dev, sgl, sgl_cnt, desc->dir); in prepare_bam_async_desc()
842 if (chan == nandc->cmd_chan) in prepare_bam_async_desc()
847 list_add_tail(&desc->node, &nandc->desc_list); in prepare_bam_async_desc()
861 static int prep_bam_dma_desc_cmd(struct qcom_nand_controller *nandc, bool read, in prep_bam_dma_desc_cmd() argument
868 struct bam_transaction *bam_txn = nandc->bam_txn; in prep_bam_dma_desc_cmd()
876 nandc_reg_phys(nandc, reg_off + 4 * i), in prep_bam_dma_desc_cmd()
878 reg_buf_dma_addr(nandc, in prep_bam_dma_desc_cmd()
882 nandc_reg_phys(nandc, reg_off + 4 * i), in prep_bam_dma_desc_cmd()
901 ret = prepare_bam_async_desc(nandc, nandc->cmd_chan, in prep_bam_dma_desc_cmd()
916 static int prep_bam_dma_desc_data(struct qcom_nand_controller *nandc, bool read, in prep_bam_dma_desc_data() argument
921 struct bam_transaction *bam_txn = nandc->bam_txn; in prep_bam_dma_desc_data()
937 ret = prepare_bam_async_desc(nandc, nandc->tx_chan, in prep_bam_dma_desc_data()
947 static int prep_adm_dma_desc(struct qcom_nand_controller *nandc, bool read, in prep_adm_dma_desc() argument
974 ret = dma_map_sg(nandc->dev, sgl, 1, desc->dir); in prep_adm_dma_desc()
985 slave_conf.src_addr = nandc->base_dma + reg_off; in prep_adm_dma_desc()
986 slave_conf.slave_id = nandc->data_crci; in prep_adm_dma_desc()
989 slave_conf.dst_addr = nandc->base_dma + reg_off; in prep_adm_dma_desc()
990 slave_conf.slave_id = nandc->cmd_crci; in prep_adm_dma_desc()
993 ret = dmaengine_slave_config(nandc->chan, &slave_conf); in prep_adm_dma_desc()
995 dev_err(nandc->dev, "failed to configure dma channel\n"); in prep_adm_dma_desc()
999 dma_desc = dmaengine_prep_slave_sg(nandc->chan, sgl, 1, dir_eng, 0); in prep_adm_dma_desc()
1001 dev_err(nandc->dev, "failed to prepare desc\n"); in prep_adm_dma_desc()
1008 list_add_tail(&desc->node, &nandc->desc_list); in prep_adm_dma_desc()
1025 static int read_reg_dma(struct qcom_nand_controller *nandc, int first, in read_reg_dma() argument
1031 vaddr = nandc->reg_read_buf + nandc->reg_read_pos; in read_reg_dma()
1032 nandc->reg_read_pos += num_regs; in read_reg_dma()
1035 first = dev_cmd_reg_addr(nandc, first); in read_reg_dma()
1037 if (nandc->props->is_bam) in read_reg_dma()
1038 return prep_bam_dma_desc_cmd(nandc, true, first, vaddr, in read_reg_dma()
1044 return prep_adm_dma_desc(nandc, true, first, vaddr, in read_reg_dma()
1056 static int write_reg_dma(struct qcom_nand_controller *nandc, int first, in write_reg_dma() argument
1060 struct nandc_regs *regs = nandc->regs; in write_reg_dma()
1076 first = dev_cmd_reg_addr(nandc, NAND_DEV_CMD1); in write_reg_dma()
1079 first = dev_cmd_reg_addr(nandc, NAND_DEV_CMD_VLD); in write_reg_dma()
1081 if (nandc->props->is_bam) in write_reg_dma()
1082 return prep_bam_dma_desc_cmd(nandc, false, first, vaddr, in write_reg_dma()
1088 return prep_adm_dma_desc(nandc, false, first, vaddr, in write_reg_dma()
1101 static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off, in read_data_dma() argument
1104 if (nandc->props->is_bam) in read_data_dma()
1105 return prep_bam_dma_desc_data(nandc, true, vaddr, size, flags); in read_data_dma()
1107 return prep_adm_dma_desc(nandc, true, reg_off, vaddr, size, false); in read_data_dma()
1119 static int write_data_dma(struct qcom_nand_controller *nandc, int reg_off, in write_data_dma() argument
1122 if (nandc->props->is_bam) in write_data_dma()
1123 return prep_bam_dma_desc_data(nandc, false, vaddr, size, flags); in write_data_dma()
1125 return prep_adm_dma_desc(nandc, false, reg_off, vaddr, size, false); in write_data_dma()
1134 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in config_nand_page_read() local
1136 write_reg_dma(nandc, NAND_ADDR0, 2, 0); in config_nand_page_read()
1137 write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0); in config_nand_page_read()
1138 if (!nandc->props->qpic_v2) in config_nand_page_read()
1139 write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0); in config_nand_page_read()
1140 write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, 0); in config_nand_page_read()
1141 write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, in config_nand_page_read()
1152 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in config_nand_cw_read() local
1157 if (nandc->props->qpic_v2 && qcom_nandc_is_last_cw(ecc, cw)) in config_nand_cw_read()
1160 if (nandc->props->is_bam) in config_nand_cw_read()
1161 write_reg_dma(nandc, reg, 4, NAND_BAM_NEXT_SGL); in config_nand_cw_read()
1163 write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL); in config_nand_cw_read()
1164 write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); in config_nand_cw_read()
1167 read_reg_dma(nandc, NAND_FLASH_STATUS, 2, 0); in config_nand_cw_read()
1168 read_reg_dma(nandc, NAND_ERASED_CW_DETECT_STATUS, 1, in config_nand_cw_read()
1171 read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL); in config_nand_cw_read()
1193 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in config_nand_page_write() local
1195 write_reg_dma(nandc, NAND_ADDR0, 2, 0); in config_nand_page_write()
1196 write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0); in config_nand_page_write()
1197 if (!nandc->props->qpic_v2) in config_nand_page_write()
1198 write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, in config_nand_page_write()
1208 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in config_nand_cw_write() local
1210 write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL); in config_nand_cw_write()
1211 write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); in config_nand_cw_write()
1213 read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL); in config_nand_cw_write()
1215 write_reg_dma(nandc, NAND_FLASH_STATUS, 1, 0); in config_nand_cw_write()
1216 write_reg_dma(nandc, NAND_READ_STATUS, 1, NAND_BAM_NEXT_SGL); in config_nand_cw_write()
1228 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in nandc_param() local
1235 if (nandc->props->qpic_v2) in nandc_param()
1255 if (!nandc->props->qpic_v2) in nandc_param()
1259 if (!nandc->props->qpic_v2) { in nandc_param()
1261 (nandc->vld & ~READ_START_VLD)); in nandc_param()
1263 (nandc->cmd1 & ~(0xFF << READ_ADDR)) in nandc_param()
1269 if (!nandc->props->qpic_v2) { in nandc_param()
1270 nandc_set_reg(chip, NAND_DEV_CMD1_RESTORE, nandc->cmd1); in nandc_param()
1271 nandc_set_reg(chip, NAND_DEV_CMD_VLD_RESTORE, nandc->vld); in nandc_param()
1276 if (!nandc->props->qpic_v2) { in nandc_param()
1277 write_reg_dma(nandc, NAND_DEV_CMD_VLD, 1, 0); in nandc_param()
1278 write_reg_dma(nandc, NAND_DEV_CMD1, 1, NAND_BAM_NEXT_SGL); in nandc_param()
1281 nandc->buf_count = 512; in nandc_param()
1282 memset(nandc->data_buffer, 0xff, nandc->buf_count); in nandc_param()
1286 read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, in nandc_param()
1287 nandc->buf_count, 0); in nandc_param()
1290 if (!nandc->props->qpic_v2) { in nandc_param()
1291 write_reg_dma(nandc, NAND_DEV_CMD1_RESTORE, 1, 0); in nandc_param()
1292 write_reg_dma(nandc, NAND_DEV_CMD_VLD_RESTORE, 1, NAND_BAM_NEXT_SGL); in nandc_param()
1302 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in erase_block() local
1315 write_reg_dma(nandc, NAND_FLASH_CMD, 3, NAND_BAM_NEXT_SGL); in erase_block()
1316 write_reg_dma(nandc, NAND_DEV0_CFG0, 2, NAND_BAM_NEXT_SGL); in erase_block()
1317 write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); in erase_block()
1319 read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL); in erase_block()
1321 write_reg_dma(nandc, NAND_FLASH_STATUS, 1, 0); in erase_block()
1322 write_reg_dma(nandc, NAND_READ_STATUS, 1, NAND_BAM_NEXT_SGL); in erase_block()
1331 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in read_id() local
1340 nandc->props->is_bam ? 0 : DM_EN); in read_id()
1343 write_reg_dma(nandc, NAND_FLASH_CMD, 4, NAND_BAM_NEXT_SGL); in read_id()
1344 write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); in read_id()
1346 read_reg_dma(nandc, NAND_READ_ID, 1, NAND_BAM_NEXT_SGL); in read_id()
1355 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in reset() local
1360 write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL); in reset()
1361 write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); in reset()
1363 read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL); in reset()
1369 static int submit_descs(struct qcom_nand_controller *nandc) in submit_descs() argument
1373 struct bam_transaction *bam_txn = nandc->bam_txn; in submit_descs()
1376 if (nandc->props->is_bam) { in submit_descs()
1378 r = prepare_bam_async_desc(nandc, nandc->rx_chan, 0); in submit_descs()
1384 r = prepare_bam_async_desc(nandc, nandc->tx_chan, in submit_descs()
1391 r = prepare_bam_async_desc(nandc, nandc->cmd_chan, in submit_descs()
1398 list_for_each_entry(desc, &nandc->desc_list, node) in submit_descs()
1401 if (nandc->props->is_bam) { in submit_descs()
1410 dma_async_issue_pending(nandc->tx_chan); in submit_descs()
1411 dma_async_issue_pending(nandc->rx_chan); in submit_descs()
1412 dma_async_issue_pending(nandc->cmd_chan); in submit_descs()
1418 if (dma_sync_wait(nandc->chan, cookie) != DMA_COMPLETE) in submit_descs()
1425 static void free_descs(struct qcom_nand_controller *nandc) in free_descs() argument
1429 list_for_each_entry_safe(desc, n, &nandc->desc_list, node) { in free_descs()
1432 if (nandc->props->is_bam) in free_descs()
1433 dma_unmap_sg(nandc->dev, desc->bam_sgl, in free_descs()
1436 dma_unmap_sg(nandc->dev, &desc->adm_sgl, 1, in free_descs()
1444 static void clear_read_regs(struct qcom_nand_controller *nandc) in clear_read_regs() argument
1446 nandc->reg_read_pos = 0; in clear_read_regs()
1447 nandc_read_buffer_sync(nandc, false); in clear_read_regs()
1453 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in pre_command() local
1455 nandc->buf_count = 0; in pre_command()
1456 nandc->buf_start = 0; in pre_command()
1460 clear_read_regs(nandc); in pre_command()
1464 clear_bam_transaction(nandc); in pre_command()
1475 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in parse_erase_write_errors() local
1481 nandc_read_buffer_sync(nandc, true); in parse_erase_write_errors()
1484 u32 flash_status = le32_to_cpu(nandc->reg_read_buf[i]); in parse_erase_write_errors()
1499 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in post_command() local
1503 nandc_read_buffer_sync(nandc, true); in post_command()
1504 memcpy(nandc->data_buffer, nandc->reg_read_buf, in post_command()
1505 nandc->buf_count); in post_command()
1527 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_command() local
1540 nandc->buf_count = 4; in qcom_nandc_command()
1577 dev_err(nandc->dev, "failure executing command %d\n", in qcom_nandc_command()
1579 free_descs(nandc); in qcom_nandc_command()
1584 ret = submit_descs(nandc); in qcom_nandc_command()
1586 dev_err(nandc->dev, in qcom_nandc_command()
1591 free_descs(nandc); in qcom_nandc_command()
1654 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in check_flash_errors() local
1657 nandc_read_buffer_sync(nandc, true); in check_flash_errors()
1660 u32 flash = le32_to_cpu(nandc->reg_read_buf[i]); in check_flash_errors()
1675 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_read_cw_raw() local
1684 if (nandc->props->qpic_v2) in qcom_nandc_read_cw_raw()
1687 clear_bam_transaction(nandc); in qcom_nandc_read_cw_raw()
1705 if (nandc->props->is_bam) { in qcom_nandc_read_cw_raw()
1720 read_data_dma(nandc, reg_off, data_buf, data_size1, 0); in qcom_nandc_read_cw_raw()
1723 read_data_dma(nandc, reg_off, oob_buf, oob_size1, 0); in qcom_nandc_read_cw_raw()
1726 read_data_dma(nandc, reg_off, data_buf + data_size1, data_size2, 0); in qcom_nandc_read_cw_raw()
1729 read_data_dma(nandc, reg_off, oob_buf + oob_size1, oob_size2, 0); in qcom_nandc_read_cw_raw()
1731 ret = submit_descs(nandc); in qcom_nandc_read_cw_raw()
1732 free_descs(nandc); in qcom_nandc_read_cw_raw()
1734 dev_err(nandc->dev, "failure to read raw cw %d\n", cw); in qcom_nandc_read_cw_raw()
1820 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in parse_read_errors() local
1829 buf = (struct read_stats *)nandc->reg_read_buf; in parse_read_errors()
1830 nandc_read_buffer_sync(nandc, true); in parse_read_errors()
1923 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in read_page_ecc() local
1943 if (nandc->props->is_bam) { in read_page_ecc()
1959 read_data_dma(nandc, FLASH_BUF_ACC, data_buf, in read_page_ecc()
1975 read_data_dma(nandc, FLASH_BUF_ACC + data_size, in read_page_ecc()
1985 ret = submit_descs(nandc); in read_page_ecc()
1986 free_descs(nandc); in read_page_ecc()
1989 dev_err(nandc->dev, "failure to read page/oob\n"); in read_page_ecc()
2003 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in copy_last_cw() local
2008 clear_read_regs(nandc); in copy_last_cw()
2013 memset(nandc->data_buffer, 0xff, size); in copy_last_cw()
2020 read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, size, 0); in copy_last_cw()
2022 ret = submit_descs(nandc); in copy_last_cw()
2024 dev_err(nandc->dev, "failed to copy last codeword\n"); in copy_last_cw()
2026 free_descs(nandc); in copy_last_cw()
2036 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_read_page() local
2043 clear_bam_transaction(nandc); in qcom_nandc_read_page()
2075 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_read_oob() local
2078 clear_read_regs(nandc); in qcom_nandc_read_oob()
2079 clear_bam_transaction(nandc); in qcom_nandc_read_oob()
2093 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_write_page() local
2100 clear_read_regs(nandc); in qcom_nandc_write_page()
2101 clear_bam_transaction(nandc); in qcom_nandc_write_page()
2123 write_data_dma(nandc, FLASH_BUF_ACC, data_buf, data_size, in qcom_nandc_write_page()
2136 write_data_dma(nandc, FLASH_BUF_ACC + data_size, in qcom_nandc_write_page()
2146 ret = submit_descs(nandc); in qcom_nandc_write_page()
2148 dev_err(nandc->dev, "failure to write page\n"); in qcom_nandc_write_page()
2150 free_descs(nandc); in qcom_nandc_write_page()
2165 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_write_page_raw() local
2171 clear_read_regs(nandc); in qcom_nandc_write_page_raw()
2172 clear_bam_transaction(nandc); in qcom_nandc_write_page_raw()
2198 write_data_dma(nandc, reg_off, data_buf, data_size1, in qcom_nandc_write_page_raw()
2203 write_data_dma(nandc, reg_off, oob_buf, oob_size1, in qcom_nandc_write_page_raw()
2208 write_data_dma(nandc, reg_off, data_buf, data_size2, in qcom_nandc_write_page_raw()
2213 write_data_dma(nandc, reg_off, oob_buf, oob_size2, 0); in qcom_nandc_write_page_raw()
2219 ret = submit_descs(nandc); in qcom_nandc_write_page_raw()
2221 dev_err(nandc->dev, "failure to write raw page\n"); in qcom_nandc_write_page_raw()
2223 free_descs(nandc); in qcom_nandc_write_page_raw()
2242 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_write_oob() local
2249 clear_bam_transaction(nandc); in qcom_nandc_write_oob()
2255 memset(nandc->data_buffer, 0xff, host->cw_data); in qcom_nandc_write_oob()
2257 mtd_ooblayout_get_databytes(mtd, nandc->data_buffer + data_size, oob, in qcom_nandc_write_oob()
2264 write_data_dma(nandc, FLASH_BUF_ACC, in qcom_nandc_write_oob()
2265 nandc->data_buffer, data_size + oob_size, 0); in qcom_nandc_write_oob()
2268 ret = submit_descs(nandc); in qcom_nandc_write_oob()
2270 free_descs(nandc); in qcom_nandc_write_oob()
2273 dev_err(nandc->dev, "failure to write oob\n"); in qcom_nandc_write_oob()
2284 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_block_bad() local
2298 clear_bam_transaction(nandc); in qcom_nandc_block_bad()
2304 dev_warn(nandc->dev, "error when trying to read BBM\n"); in qcom_nandc_block_bad()
2310 bad = nandc->data_buffer[bbpos] != 0xff; in qcom_nandc_block_bad()
2313 bad = bad || (nandc->data_buffer[bbpos + 1] != 0xff); in qcom_nandc_block_bad()
2321 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_block_markbad() local
2325 clear_read_regs(nandc); in qcom_nandc_block_markbad()
2326 clear_bam_transaction(nandc); in qcom_nandc_block_markbad()
2333 memset(nandc->data_buffer, 0x00, host->cw_size); in qcom_nandc_block_markbad()
2343 write_data_dma(nandc, FLASH_BUF_ACC, in qcom_nandc_block_markbad()
2344 nandc->data_buffer, host->cw_size, 0); in qcom_nandc_block_markbad()
2347 ret = submit_descs(nandc); in qcom_nandc_block_markbad()
2349 free_descs(nandc); in qcom_nandc_block_markbad()
2352 dev_err(nandc->dev, "failure to update BBM\n"); in qcom_nandc_block_markbad()
2368 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_read_byte() local
2369 u8 *buf = nandc->data_buffer; in qcom_nandc_read_byte()
2380 if (nandc->buf_start < nandc->buf_count) in qcom_nandc_read_byte()
2381 ret = buf[nandc->buf_start++]; in qcom_nandc_read_byte()
2388 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_read_buf() local
2389 int real_len = min_t(size_t, len, nandc->buf_count - nandc->buf_start); in qcom_nandc_read_buf()
2391 memcpy(buf, nandc->data_buffer + nandc->buf_start, real_len); in qcom_nandc_read_buf()
2392 nandc->buf_start += real_len; in qcom_nandc_read_buf()
2398 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_write_buf() local
2399 int real_len = min_t(size_t, len, nandc->buf_count - nandc->buf_start); in qcom_nandc_write_buf()
2401 memcpy(nandc->data_buffer + nandc->buf_start, buf, real_len); in qcom_nandc_write_buf()
2403 nandc->buf_start += real_len; in qcom_nandc_write_buf()
2409 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_select_chip() local
2414 dev_warn(nandc->dev, "invalid chip select\n"); in qcom_nandc_select_chip()
2558 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nand_attach_chip() local
2575 dev_err(nandc->dev, "No valid ECC settings possible\n"); in qcom_nand_attach_chip()
2599 if (nandc->props->ecc_modes & ECC_BCH_4BIT) { in qcom_nand_attach_chip()
2646 nandc->max_cwperpage = max_t(unsigned int, nandc->max_cwperpage, in qcom_nand_attach_chip()
2700 if (!nandc->props->qpic_v2) in qcom_nand_attach_chip()
2705 nandc->regs->erased_cw_detect_cfg_clr = in qcom_nand_attach_chip()
2707 nandc->regs->erased_cw_detect_cfg_set = in qcom_nand_attach_chip()
2710 dev_dbg(nandc->dev, in qcom_nand_attach_chip()
2723 static void qcom_nandc_unalloc(struct qcom_nand_controller *nandc) in qcom_nandc_unalloc() argument
2725 if (nandc->props->is_bam) { in qcom_nandc_unalloc()
2726 if (!dma_mapping_error(nandc->dev, nandc->reg_read_dma)) in qcom_nandc_unalloc()
2727 dma_unmap_single(nandc->dev, nandc->reg_read_dma, in qcom_nandc_unalloc()
2729 sizeof(*nandc->reg_read_buf), in qcom_nandc_unalloc()
2732 if (nandc->tx_chan) in qcom_nandc_unalloc()
2733 dma_release_channel(nandc->tx_chan); in qcom_nandc_unalloc()
2735 if (nandc->rx_chan) in qcom_nandc_unalloc()
2736 dma_release_channel(nandc->rx_chan); in qcom_nandc_unalloc()
2738 if (nandc->cmd_chan) in qcom_nandc_unalloc()
2739 dma_release_channel(nandc->cmd_chan); in qcom_nandc_unalloc()
2741 if (nandc->chan) in qcom_nandc_unalloc()
2742 dma_release_channel(nandc->chan); in qcom_nandc_unalloc()
2746 static int qcom_nandc_alloc(struct qcom_nand_controller *nandc) in qcom_nandc_alloc() argument
2750 ret = dma_set_coherent_mask(nandc->dev, DMA_BIT_MASK(32)); in qcom_nandc_alloc()
2752 dev_err(nandc->dev, "failed to set DMA mask\n"); in qcom_nandc_alloc()
2762 nandc->buf_size = 532; in qcom_nandc_alloc()
2764 nandc->data_buffer = devm_kzalloc(nandc->dev, nandc->buf_size, in qcom_nandc_alloc()
2766 if (!nandc->data_buffer) in qcom_nandc_alloc()
2769 nandc->regs = devm_kzalloc(nandc->dev, sizeof(*nandc->regs), in qcom_nandc_alloc()
2771 if (!nandc->regs) in qcom_nandc_alloc()
2774 nandc->reg_read_buf = devm_kcalloc(nandc->dev, in qcom_nandc_alloc()
2775 MAX_REG_RD, sizeof(*nandc->reg_read_buf), in qcom_nandc_alloc()
2777 if (!nandc->reg_read_buf) in qcom_nandc_alloc()
2780 if (nandc->props->is_bam) { in qcom_nandc_alloc()
2781 nandc->reg_read_dma = in qcom_nandc_alloc()
2782 dma_map_single(nandc->dev, nandc->reg_read_buf, in qcom_nandc_alloc()
2784 sizeof(*nandc->reg_read_buf), in qcom_nandc_alloc()
2786 if (dma_mapping_error(nandc->dev, nandc->reg_read_dma)) { in qcom_nandc_alloc()
2787 dev_err(nandc->dev, "failed to DMA MAP reg buffer\n"); in qcom_nandc_alloc()
2791 nandc->tx_chan = dma_request_chan(nandc->dev, "tx"); in qcom_nandc_alloc()
2792 if (IS_ERR(nandc->tx_chan)) { in qcom_nandc_alloc()
2793 ret = PTR_ERR(nandc->tx_chan); in qcom_nandc_alloc()
2794 nandc->tx_chan = NULL; in qcom_nandc_alloc()
2795 dev_err_probe(nandc->dev, ret, in qcom_nandc_alloc()
2800 nandc->rx_chan = dma_request_chan(nandc->dev, "rx"); in qcom_nandc_alloc()
2801 if (IS_ERR(nandc->rx_chan)) { in qcom_nandc_alloc()
2802 ret = PTR_ERR(nandc->rx_chan); in qcom_nandc_alloc()
2803 nandc->rx_chan = NULL; in qcom_nandc_alloc()
2804 dev_err_probe(nandc->dev, ret, in qcom_nandc_alloc()
2809 nandc->cmd_chan = dma_request_chan(nandc->dev, "cmd"); in qcom_nandc_alloc()
2810 if (IS_ERR(nandc->cmd_chan)) { in qcom_nandc_alloc()
2811 ret = PTR_ERR(nandc->cmd_chan); in qcom_nandc_alloc()
2812 nandc->cmd_chan = NULL; in qcom_nandc_alloc()
2813 dev_err_probe(nandc->dev, ret, in qcom_nandc_alloc()
2824 nandc->max_cwperpage = 1; in qcom_nandc_alloc()
2825 nandc->bam_txn = alloc_bam_transaction(nandc); in qcom_nandc_alloc()
2826 if (!nandc->bam_txn) { in qcom_nandc_alloc()
2827 dev_err(nandc->dev, in qcom_nandc_alloc()
2833 nandc->chan = dma_request_chan(nandc->dev, "rxtx"); in qcom_nandc_alloc()
2834 if (IS_ERR(nandc->chan)) { in qcom_nandc_alloc()
2835 ret = PTR_ERR(nandc->chan); in qcom_nandc_alloc()
2836 nandc->chan = NULL; in qcom_nandc_alloc()
2837 dev_err_probe(nandc->dev, ret, in qcom_nandc_alloc()
2843 INIT_LIST_HEAD(&nandc->desc_list); in qcom_nandc_alloc()
2844 INIT_LIST_HEAD(&nandc->host_list); in qcom_nandc_alloc()
2846 nand_controller_init(&nandc->controller); in qcom_nandc_alloc()
2847 nandc->controller.ops = &qcom_nandc_ops; in qcom_nandc_alloc()
2851 qcom_nandc_unalloc(nandc); in qcom_nandc_alloc()
2856 static int qcom_nandc_setup(struct qcom_nand_controller *nandc) in qcom_nandc_setup() argument
2861 if (!nandc->props->is_qpic) in qcom_nandc_setup()
2862 nandc_write(nandc, SFLASHC_BURST_CFG, 0); in qcom_nandc_setup()
2864 if (!nandc->props->qpic_v2) in qcom_nandc_setup()
2865 nandc_write(nandc, dev_cmd_reg_addr(nandc, NAND_DEV_CMD_VLD), in qcom_nandc_setup()
2869 if (nandc->props->is_bam) { in qcom_nandc_setup()
2870 nand_ctrl = nandc_read(nandc, NAND_CTRL); in qcom_nandc_setup()
2880 nandc_write(nandc, NAND_CTRL, nand_ctrl | BAM_MODE_EN); in qcom_nandc_setup()
2882 nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN); in qcom_nandc_setup()
2886 if (!nandc->props->qpic_v2) { in qcom_nandc_setup()
2887 nandc->cmd1 = nandc_read(nandc, dev_cmd_reg_addr(nandc, NAND_DEV_CMD1)); in qcom_nandc_setup()
2888 nandc->vld = NAND_DEV_CMD_VLD_VAL; in qcom_nandc_setup()
2896 static int qcom_nand_host_init_and_register(struct qcom_nand_controller *nandc, in qcom_nand_host_init_and_register() argument
2902 struct device *dev = nandc->dev; in qcom_nand_host_init_and_register()
2938 chip->controller = &nandc->controller; in qcom_nand_host_init_and_register()
2949 if (nandc->props->is_bam) { in qcom_nand_host_init_and_register()
2950 free_bam_transaction(nandc); in qcom_nand_host_init_and_register()
2951 nandc->bam_txn = alloc_bam_transaction(nandc); in qcom_nand_host_init_and_register()
2952 if (!nandc->bam_txn) { in qcom_nand_host_init_and_register()
2953 dev_err(nandc->dev, in qcom_nand_host_init_and_register()
2967 static int qcom_probe_nand_devices(struct qcom_nand_controller *nandc) in qcom_probe_nand_devices() argument
2969 struct device *dev = nandc->dev; in qcom_probe_nand_devices()
2981 ret = qcom_nand_host_init_and_register(nandc, host, child); in qcom_probe_nand_devices()
2987 list_add_tail(&host->node, &nandc->host_list); in qcom_probe_nand_devices()
2996 struct qcom_nand_controller *nandc = platform_get_drvdata(pdev); in qcom_nandc_parse_dt() local
2997 struct device_node *np = nandc->dev->of_node; in qcom_nandc_parse_dt()
3000 if (!nandc->props->is_bam) { in qcom_nandc_parse_dt()
3002 &nandc->cmd_crci); in qcom_nandc_parse_dt()
3004 dev_err(nandc->dev, "command CRCI unspecified\n"); in qcom_nandc_parse_dt()
3009 &nandc->data_crci); in qcom_nandc_parse_dt()
3011 dev_err(nandc->dev, "data CRCI unspecified\n"); in qcom_nandc_parse_dt()
3021 struct qcom_nand_controller *nandc; in qcom_nandc_probe() local
3027 nandc = devm_kzalloc(&pdev->dev, sizeof(*nandc), GFP_KERNEL); in qcom_nandc_probe()
3028 if (!nandc) in qcom_nandc_probe()
3031 platform_set_drvdata(pdev, nandc); in qcom_nandc_probe()
3032 nandc->dev = dev; in qcom_nandc_probe()
3040 nandc->props = dev_data; in qcom_nandc_probe()
3042 nandc->core_clk = devm_clk_get(dev, "core"); in qcom_nandc_probe()
3043 if (IS_ERR(nandc->core_clk)) in qcom_nandc_probe()
3044 return PTR_ERR(nandc->core_clk); in qcom_nandc_probe()
3046 nandc->aon_clk = devm_clk_get(dev, "aon"); in qcom_nandc_probe()
3047 if (IS_ERR(nandc->aon_clk)) in qcom_nandc_probe()
3048 return PTR_ERR(nandc->aon_clk); in qcom_nandc_probe()
3055 nandc->base = devm_ioremap_resource(dev, res); in qcom_nandc_probe()
3056 if (IS_ERR(nandc->base)) in qcom_nandc_probe()
3057 return PTR_ERR(nandc->base); in qcom_nandc_probe()
3059 nandc->base_phys = res->start; in qcom_nandc_probe()
3060 nandc->base_dma = dma_map_resource(dev, res->start, in qcom_nandc_probe()
3063 if (dma_mapping_error(dev, nandc->base_dma)) in qcom_nandc_probe()
3066 ret = qcom_nandc_alloc(nandc); in qcom_nandc_probe()
3070 ret = clk_prepare_enable(nandc->core_clk); in qcom_nandc_probe()
3074 ret = clk_prepare_enable(nandc->aon_clk); in qcom_nandc_probe()
3078 ret = qcom_nandc_setup(nandc); in qcom_nandc_probe()
3082 ret = qcom_probe_nand_devices(nandc); in qcom_nandc_probe()
3089 clk_disable_unprepare(nandc->aon_clk); in qcom_nandc_probe()
3091 clk_disable_unprepare(nandc->core_clk); in qcom_nandc_probe()
3093 qcom_nandc_unalloc(nandc); in qcom_nandc_probe()
3103 struct qcom_nand_controller *nandc = platform_get_drvdata(pdev); in qcom_nandc_remove() local
3109 list_for_each_entry(host, &nandc->host_list, node) { in qcom_nandc_remove()
3116 qcom_nandc_unalloc(nandc); in qcom_nandc_remove()
3118 clk_disable_unprepare(nandc->aon_clk); in qcom_nandc_remove()
3119 clk_disable_unprepare(nandc->core_clk); in qcom_nandc_remove()
3121 dma_unmap_resource(&pdev->dev, nandc->base_dma, resource_size(res), in qcom_nandc_remove()