168  * the NAND controller performs reads/writes with ECC in 516 byte chunks.
182 /* ECC modes supported by the controller */
430  *				of a page, consisting of all data, ecc, spare
433  *				by ECC
434  * @use_ecc:			request the controller to use ECC for the
436  * @bch_enabled:		flag to tell whether BCH ECC mode is used
437  * @ecc_bytes_hw:		ECC bytes used by controller hardware for this
445  *				ecc/non-ecc mode for the current nand flash
474  * @ecc_modes - ecc mode for NAND
687 static bool qcom_nandc_is_last_cw(struct nand_ecc_ctrl *ecc, int cw)  in qcom_nandc_is_last_cw()  argument
689 	return cw == (ecc->steps - 1);  in qcom_nandc_is_last_cw()
697 	struct nand_ecc_ctrl *ecc = &chip->ecc;  in nandc_set_read_loc()  local
700 	if (nandc->props->qpic_v2 && qcom_nandc_is_last_cw(ecc, cw))  in nandc_set_read_loc()
705 	if (nandc->props->qpic_v2 && qcom_nandc_is_last_cw(ecc, cw))  in nandc_set_read_loc()
1153 	struct nand_ecc_ctrl *ecc = &chip->ecc;  in config_nand_cw_read()  local
1157 	if (nandc->props->qpic_v2 && qcom_nandc_is_last_cw(ecc, cw))  in config_nand_cw_read()
1476 	struct nand_ecc_ctrl *ecc = &chip->ecc;  in parse_erase_write_errors()  local
1480 	num_cw = command == NAND_CMD_PAGEPROG ? ecc->steps : 1;  in parse_erase_write_errors()
1526 	struct nand_ecc_ctrl *ecc = &chip->ecc;  in qcom_nandc_command()  local
1561 		update_rw_regs(host, ecc->steps, true, 0);  in qcom_nandc_command()
1597  * when using BCH ECC, the HW flags an error in NAND_FLASH_STATUS if it read
1600  * when using RS ECC, the HW reports the same erros when reading an erased CW,
1604  * verify if the page is erased or not, and fix up the page for RS ECC by
1676 	struct nand_ecc_ctrl *ecc = &chip->ecc;  in qcom_nandc_read_cw_raw()  local
1685 		raw_cw = ecc->steps - 1;  in qcom_nandc_read_cw_raw()
1692 	data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1);  in qcom_nandc_read_cw_raw()
1695 	if (qcom_nandc_is_last_cw(ecc, cw)) {  in qcom_nandc_read_cw_raw()
1696 		data_size2 = ecc->size - data_size1 -  in qcom_nandc_read_cw_raw()
1697 			     ((ecc->steps - 1) * 4);  in qcom_nandc_read_cw_raw()
1698 		oob_size2 = (ecc->steps * 4) + host->ecc_bytes_hw +  in qcom_nandc_read_cw_raw()
1743  * number of 0 in each CW for which ECC engine returns the uncorrectable
1745  * equal to the ecc->strength for each CW.
1753  *    The BBM and spare bytes bit flip won’t affect the ECC so don’t check
1763 	struct nand_ecc_ctrl *ecc = &chip->ecc;  in check_for_erased_page()  local
1775 	for_each_set_bit(cw, &uncorrectable_cws, ecc->steps) {  in check_for_erased_page()
1776 		if (qcom_nandc_is_last_cw(ecc, cw)) {  in check_for_erased_page()
1777 			data_size = ecc->size - ((ecc->steps - 1) * 4);  in check_for_erased_page()
1778 			oob_size = (ecc->steps * 4) + host->ecc_bytes_hw;  in check_for_erased_page()
1786 		cw_oob_buf = oob_buf + (cw * ecc->bytes);  in check_for_erased_page()
1800 						  0, ecc->strength);  in check_for_erased_page()
1814  * errors. this is equivalent to what 'ecc->correct()' would do.
1822 	struct nand_ecc_ctrl *ecc = &chip->ecc;  in parse_read_errors()  local
1832 	for (i = 0; i < ecc->steps; i++, buf++) {  in parse_read_errors()
1836 		if (qcom_nandc_is_last_cw(ecc, i)) {  in parse_read_errors()
1837 			data_len = ecc->size - ((ecc->steps - 1) << 2);  in parse_read_errors()
1838 			oob_len = ecc->steps << 2;  in parse_read_errors()
1849 		 * Check ECC failure for each codeword. ECC failure can  in parse_read_errors()
1851 		 * 1. If number of bitflips are greater than ECC engine  in parse_read_errors()
1858 			 * For BCH ECC, ignore erased codeword errors, if  in parse_read_errors()
1864 			 * For RS ECC, HW reports the erased CW by placing  in parse_read_errors()
1887 		 * No ECC or operational errors happened. Check the number of  in parse_read_errors()
1901 			oob_buf += oob_len + ecc->bytes;  in parse_read_errors()
1916  * helper to perform the actual page read operation, used by ecc->read_page(),
1917  * ecc->read_oob()
1924 	struct nand_ecc_ctrl *ecc = &chip->ecc;  in read_page_ecc()  local
1931 	for (i = 0; i < ecc->steps; i++) {  in read_page_ecc()
1934 		if (qcom_nandc_is_last_cw(ecc, i)) {  in read_page_ecc()
1935 			data_size = ecc->size - ((ecc->steps - 1) << 2);  in read_page_ecc()
1936 			oob_size = (ecc->steps << 2) + host->ecc_bytes_hw +  in read_page_ecc()
1963 		 * when ecc is enabled, the controller doesn't read the real  in read_page_ecc()
1965 		 * consistent layout across RAW and ECC reads, we just  in read_page_ecc()
2004 	struct nand_ecc_ctrl *ecc = &chip->ecc;  in copy_last_cw()  local
2015 	set_address(host, host->cw_size * (ecc->steps - 1), page);  in copy_last_cw()
2016 	update_rw_regs(host, 1, true, ecc->steps - 1);  in copy_last_cw()
2018 	config_nand_single_cw_page_read(chip, host->use_ecc, ecc->steps - 1);  in copy_last_cw()
2031 /* implements ecc->read_page() */
2048 /* implements ecc->read_page_raw() */
2054 	struct nand_ecc_ctrl *ecc = &chip->ecc;  in qcom_nandc_read_page_raw()  local
2058 	for (cw = 0; cw < ecc->steps; cw++) {  in qcom_nandc_read_page_raw()
2065 		oob_buf += ecc->bytes;  in qcom_nandc_read_page_raw()
2071 /* implements ecc->read_oob() */
2076 	struct nand_ecc_ctrl *ecc = &chip->ecc;  in qcom_nandc_read_oob()  local
2083 	update_rw_regs(host, ecc->steps, true, 0);  in qcom_nandc_read_oob()
2088 /* implements ecc->write_page() */
2094 	struct nand_ecc_ctrl *ecc = &chip->ecc;  in qcom_nandc_write_page()  local
2107 	update_rw_regs(host, ecc->steps, false, 0);  in qcom_nandc_write_page()
2110 	for (i = 0; i < ecc->steps; i++) {  in qcom_nandc_write_page()
2113 		if (qcom_nandc_is_last_cw(ecc, i)) {  in qcom_nandc_write_page()
2114 			data_size = ecc->size - ((ecc->steps - 1) << 2);  in qcom_nandc_write_page()
2115 			oob_size = (ecc->steps << 2) + host->ecc_bytes_hw +  in qcom_nandc_write_page()
2119 			oob_size = ecc->bytes;  in qcom_nandc_write_page()
2124 			       i == (ecc->steps - 1) ? NAND_BAM_NO_EOT : 0);  in qcom_nandc_write_page()
2127 		 * when ECC is enabled, we don't really need to write anything  in qcom_nandc_write_page()
2129 		 * just contain ECC bytes that's written by the controller  in qcom_nandc_write_page()
2133 		if (qcom_nandc_is_last_cw(ecc, i)) {  in qcom_nandc_write_page()
2158 /* implements ecc->write_page_raw() */
2166 	struct nand_ecc_ctrl *ecc = &chip->ecc;  in qcom_nandc_write_page_raw()  local
2178 	update_rw_regs(host, ecc->steps, false, 0);  in qcom_nandc_write_page_raw()
2181 	for (i = 0; i < ecc->steps; i++) {  in qcom_nandc_write_page_raw()
2185 		data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1);  in qcom_nandc_write_page_raw()
2188 		if (qcom_nandc_is_last_cw(ecc, i)) {  in qcom_nandc_write_page_raw()
2189 			data_size2 = ecc->size - data_size1 -  in qcom_nandc_write_page_raw()
2190 				     ((ecc->steps - 1) << 2);  in qcom_nandc_write_page_raw()
2191 			oob_size2 = (ecc->steps << 2) + host->ecc_bytes_hw +  in qcom_nandc_write_page_raw()
2232  * implements ecc->write_oob()
2235  * since ECC is calculated for the combined codeword. So update the OOB from
2243 	struct nand_ecc_ctrl *ecc = &chip->ecc;  in qcom_nandc_write_oob()  local
2252 	data_size = ecc->size - ((ecc->steps - 1) << 2);  in qcom_nandc_write_oob()
2260 	set_address(host, host->cw_size * (ecc->steps - 1), page);  in qcom_nandc_write_oob()
2285 	struct nand_ecc_ctrl *ecc = &chip->ecc;  in qcom_nandc_block_bad()  local
2292 	 * the beginning of the last codeword, we don't care about reading ecc  in qcom_nandc_block_bad()
2308 	bbpos = mtd->writesize - host->cw_size * (ecc->steps - 1);  in qcom_nandc_block_bad()
2322 	struct nand_ecc_ctrl *ecc = &chip->ecc;  in qcom_nandc_block_markbad()  local
2339 	set_address(host, host->cw_size * (ecc->steps - 1), page);  in qcom_nandc_block_markbad()
2340 	update_rw_regs(host, 1, false, ecc->steps - 1);  in qcom_nandc_block_markbad()
2420  * Layout with ECC enabled:
2424  * |    DATA   xx..ECC..yy|  |    DATA     **SPARE**xx..ECC..yy|
2432  * . = ECC bytes
2442  * codeword is 528 and 532 bytes for 4 bit and 8 bit ECC modes respectively.
2443  * the number of ECC bytes vary based on the ECC strength and the bus width.
2446  * 12/16 bytes consist of ECC and reserved data. The nth codeword contains
2449  * When we access a page with ECC enabled, the reserved bytes(s) are not
2454  * Layout with ECC disabled:
2458  * |  DATA1  yy  DATA2   xx..ECC..|  |  DATA1  bb  DATA2   **SPARE**xx..ECC..|
2466  * . = ECC bytes
2473  * when the ECC block is disabled, one reserved byte (or two for 16 bit bus
2477  * In order to have a consistent layout between RAW and ECC modes, we assume
2482  * |yyxx..ECC..|  |bb*FREEOOB*xx..ECC..|
2490  * . = ECC bytes
2492  * y = Dummy bad block byte(s) (inaccessible when ECC enabled)
2494  * b = Real bad block byte(s) (inaccessible when ECC enabled)
2496  * This layout is read as is when ECC is disabled. When ECC is enabled, the
2498  * and assumed as 0xffs when we read a page/oob. The ECC, unused and
2499  * dummy/real bad block bytes are grouped as ecc bytes (i.e, ecc->bytes is
2507 	struct nand_ecc_ctrl *ecc = &chip->ecc;  in qcom_nand_ooblayout_ecc()  local
2513 		oobregion->length = (ecc->bytes * (ecc->steps - 1)) +  in qcom_nand_ooblayout_ecc()
2529 	struct nand_ecc_ctrl *ecc = &chip->ecc;  in qcom_nand_ooblayout_free()  local
2534 	oobregion->length = ecc->steps * 4;  in qcom_nand_ooblayout_free()
2535 	oobregion->offset = ((ecc->steps - 1) * ecc->bytes) + host->bbm_size;  in qcom_nand_ooblayout_free()
2541 	.ecc = qcom_nand_ooblayout_ecc,
2557 	struct nand_ecc_ctrl *ecc = &chip->ecc;  in qcom_nand_attach_chip()  local
2564 	ecc->size = NANDC_STEP_SIZE;  in qcom_nand_attach_chip()
2569 	 * Each CW has 4 available OOB bytes which will be protected with ECC  in qcom_nand_attach_chip()
2570 	 * so remaining bytes can be used for ECC.  in qcom_nand_attach_chip()
2575 		dev_err(nandc->dev, "No valid ECC settings possible\n");  in qcom_nand_attach_chip()
2579 	if (ecc->strength >= 8) {  in qcom_nand_attach_chip()
2580 		/* 8 bit ECC defaults to BCH ECC on all platforms */  in qcom_nand_attach_chip()
2595 		 * if the controller supports BCH for 4 bit ECC, the controller  in qcom_nand_attach_chip()
2596 		 * uses lesser bytes for ECC. If RS is used, the ECC bytes is  in qcom_nand_attach_chip()
2628 	 * we consider ecc->bytes as the sum of all the non-data content in a  in qcom_nand_attach_chip()
2630 	 * all the bytes aren't used for ECC).It is always 16 bytes for 8 bit  in qcom_nand_attach_chip()
2631 	 * ECC and 12 bytes for 4 bit ECC  in qcom_nand_attach_chip()
2633 	ecc->bytes = host->ecc_bytes_hw + host->spare_bytes + host->bbm_size;  in qcom_nand_attach_chip()
2635 	ecc->read_page		= qcom_nandc_read_page;  in qcom_nand_attach_chip()
2636 	ecc->read_page_raw	= qcom_nandc_read_page_raw;  in qcom_nand_attach_chip()
2637 	ecc->read_oob		= qcom_nandc_read_oob;  in qcom_nand_attach_chip()
2638 	ecc->write_page		= qcom_nandc_write_page;  in qcom_nand_attach_chip()
2639 	ecc->write_page_raw	= qcom_nandc_write_page_raw;  in qcom_nand_attach_chip()
2640 	ecc->write_oob		= qcom_nandc_write_oob;  in qcom_nand_attach_chip()
2642 	ecc->engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;  in qcom_nand_attach_chip()
2651 	 * spare data with ECC too. We protect spare data by default, so we set  in qcom_nand_attach_chip()
2657 	 * total bytes in a step, either 528 bytes for 4 bit ECC, or 532 bytes  in qcom_nand_attach_chip()
2658 	 * for 8 bit ECC  in qcom_nand_attach_chip()
2660 	host->cw_size = host->cw_data + ecc->bytes;  in qcom_nand_attach_chip()
2713 		host->cw_size, host->cw_data, ecc->strength, ecc->bytes,  in qcom_nand_attach_chip()
2929 	 * of a page with ECC disabled. currently, the nand_base and nand_bbt  in qcom_nand_host_init_and_register()
2930 	 * helpers don't allow us to read BB from a nand chip with ECC  in qcom_nand_host_init_and_register()