Lines Matching +full:nand +full:- +full:ecc +full:- +full:engine
1 // SPDX-License-Identifier: GPL-2.0-only
4 * This is the generic MTD driver for NAND flash devices. It should be
5 * capable of working with almost all NAND chips currently available.
8 * http://www.linux-mtd.infradead.org/doc/nand.html
11 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
21 * Check, if mtd->ecctype should be set to MTD_ECC_HW
22 * if we have HW ECC support.
37 #include <linux/mtd/nand.h>
38 #include <linux/mtd/nand-ecc-sw-hamming.h>
39 #include <linux/mtd/nand-ecc-sw-bch.h>
53 int lastpage = (mtd->erasesize / mtd->writesize) - 1; in nand_pairing_dist3_get_info()
60 info->group = 0; in nand_pairing_dist3_get_info()
61 info->pair = (page + 1) / 2; in nand_pairing_dist3_get_info()
63 info->group = 1; in nand_pairing_dist3_get_info()
64 info->pair = (page + 1 - dist) / 2; in nand_pairing_dist3_get_info()
73 int lastpair = ((mtd->erasesize / mtd->writesize) - 1) / 2; in nand_pairing_dist3_get_wunit()
74 int page = info->pair * 2; in nand_pairing_dist3_get_wunit()
77 if (!info->group && !info->pair) in nand_pairing_dist3_get_wunit()
80 if (info->pair == lastpair && info->group) in nand_pairing_dist3_get_wunit()
83 if (!info->group) in nand_pairing_dist3_get_wunit()
84 page--; in nand_pairing_dist3_get_wunit()
85 else if (info->pair) in nand_pairing_dist3_get_wunit()
86 page += dist - 1; in nand_pairing_dist3_get_wunit()
88 if (page >= mtd->erasesize / mtd->writesize) in nand_pairing_dist3_get_wunit()
89 return -EINVAL; in nand_pairing_dist3_get_wunit()
105 if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) { in check_offs_len()
107 ret = -EINVAL; in check_offs_len()
111 if (len & ((1ULL << chip->phys_erase_shift) - 1)) { in check_offs_len()
113 ret = -EINVAL; in check_offs_len()
120 * nand_extract_bits - Copy unaligned bits from one buffer to another one
140 n = min3(8 - dst_off, 8 - src_off, nbits); in nand_extract_bits()
142 tmp = (*src >> src_off) & GENMASK(n - 1, 0); in nand_extract_bits()
143 *dst &= ~GENMASK(n - 1 + dst_off, dst_off); in nand_extract_bits()
149 dst_off -= 8; in nand_extract_bits()
155 src_off -= 8; in nand_extract_bits()
158 nbits -= n; in nand_extract_bits()
164 * nand_select_target() - Select a NAND target (A.K.A. die)
165 * @chip: NAND chip object
169 * Select a NAND target so that further operations executed on @chip go to the
170 * selected NAND target.
178 if (WARN_ON(cs > nanddev_ntargets(&chip->base))) in nand_select_target()
181 chip->cur_cs = cs; in nand_select_target()
183 if (chip->legacy.select_chip) in nand_select_target()
184 chip->legacy.select_chip(chip, cs); in nand_select_target()
189 * nand_deselect_target() - Deselect the currently selected target
190 * @chip: NAND chip object
192 * Deselect the currently selected NAND target. The result of operations
197 if (chip->legacy.select_chip) in nand_deselect_target()
198 chip->legacy.select_chip(chip, -1); in nand_deselect_target()
200 chip->cur_cs = -1; in nand_deselect_target()
205 * nand_release_device - [GENERIC] release chip
206 * @chip: NAND chip object
213 mutex_unlock(&chip->controller->lock); in nand_release_device()
214 mutex_unlock(&chip->lock); in nand_release_device()
218 * nand_bbm_get_next_page - Get the next page for bad block markers
219 * @chip: NAND chip object
224 * available, -EINVAL is returned.
229 int last_page = ((mtd->erasesize - mtd->writesize) >> in nand_bbm_get_next_page()
230 chip->page_shift) & chip->pagemask; in nand_bbm_get_next_page()
234 if (page == 0 && !(chip->options & bbm_flags)) in nand_bbm_get_next_page()
236 if (page == 0 && chip->options & NAND_BBM_FIRSTPAGE) in nand_bbm_get_next_page()
238 if (page <= 1 && chip->options & NAND_BBM_SECONDPAGE) in nand_bbm_get_next_page()
240 if (page <= last_page && chip->options & NAND_BBM_LASTPAGE) in nand_bbm_get_next_page()
243 return -EINVAL; in nand_bbm_get_next_page()
247 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
248 * @chip: NAND chip object
259 first_page = (int)(ofs >> chip->page_shift) & chip->pagemask; in nand_block_bad()
263 res = chip->ecc.read_oob(chip, first_page + page_offset); in nand_block_bad()
267 bad = chip->oob_poi[chip->badblockpos]; in nand_block_bad()
269 if (likely(chip->badblockbits == 8)) in nand_block_bad()
272 res = hweight8(bad) < chip->badblockbits; in nand_block_bad()
283 * nand_region_is_secured() - Check if the region is secured
284 * @chip: NAND chip object
297 for (i = 0; i < chip->nr_secure_regions; i++) { in nand_region_is_secured()
298 const struct nand_secure_region *region = &chip->secure_regions[i]; in nand_region_is_secured()
300 if (offset + size <= region->offset || in nand_region_is_secured()
301 offset >= region->offset + region->size) in nand_region_is_secured()
304 pr_debug("%s: Region 0x%llx - 0x%llx is secured!", in nand_region_is_secured()
317 if (chip->options & NAND_NO_BBM_QUIRK) in nand_isbad_bbm()
321 if (nand_region_is_secured(chip, ofs, mtd->erasesize)) in nand_isbad_bbm()
322 return -EIO; in nand_isbad_bbm()
324 if (chip->legacy.block_bad) in nand_isbad_bbm()
325 return chip->legacy.block_bad(chip, ofs); in nand_isbad_bbm()
331 * nand_get_device - [GENERIC] Get chip for selected access
332 * @chip: NAND chip structure
336 * Return: -EBUSY if the chip has been suspended, 0 otherwise
340 mutex_lock(&chip->lock); in nand_get_device()
341 if (chip->suspended) { in nand_get_device()
342 mutex_unlock(&chip->lock); in nand_get_device()
343 return -EBUSY; in nand_get_device()
345 mutex_lock(&chip->controller->lock); in nand_get_device()
351 * nand_check_wp - [GENERIC] check if the chip is write protected
352 * @chip: NAND chip object
363 if (chip->options & NAND_BROKEN_XD) in nand_check_wp()
375 * nand_fill_oob - [INTERN] Transfer client buffer to oob
376 * @chip: NAND chip object
391 memset(chip->oob_poi, 0xff, mtd->oobsize); in nand_fill_oob()
393 switch (ops->mode) { in nand_fill_oob()
397 memcpy(chip->oob_poi + ops->ooboffs, oob, len); in nand_fill_oob()
401 ret = mtd_ooblayout_set_databytes(mtd, oob, chip->oob_poi, in nand_fill_oob()
402 ops->ooboffs, len); in nand_fill_oob()
413 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
414 * @chip: NAND chip object
418 * NAND write out-of-band.
427 __func__, (unsigned int)to, (int)ops->ooblen); in nand_do_write_oob()
432 if ((ops->ooboffs + ops->ooblen) > len) { in nand_do_write_oob()
435 return -EINVAL; in nand_do_write_oob()
439 if (nand_region_is_secured(chip, to, ops->ooblen)) in nand_do_write_oob()
440 return -EIO; in nand_do_write_oob()
442 chipnr = (int)(to >> chip->chip_shift); in nand_do_write_oob()
457 page = (int)(to >> chip->page_shift); in nand_do_write_oob()
462 return -EROFS; in nand_do_write_oob()
466 if (page == chip->pagecache.page) in nand_do_write_oob()
467 chip->pagecache.page = -1; in nand_do_write_oob()
469 nand_fill_oob(chip, ops->oobbuf, ops->ooblen, ops); in nand_do_write_oob()
471 if (ops->mode == MTD_OPS_RAW) in nand_do_write_oob()
472 status = chip->ecc.write_oob_raw(chip, page & chip->pagemask); in nand_do_write_oob()
474 status = chip->ecc.write_oob(chip, page & chip->pagemask); in nand_do_write_oob()
481 ops->oobretlen = ops->ooblen; in nand_do_write_oob()
487 * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
488 * @chip: NAND chip object
504 ops.ooboffs = chip->badblockpos; in nand_default_block_markbad()
505 if (chip->options & NAND_BUSWIDTH_16) { in nand_default_block_markbad()
517 ofs + (page_offset * mtd->writesize), in nand_default_block_markbad()
530 * nand_markbad_bbm - mark a block by updating the BBM
531 * @chip: NAND chip object
536 if (chip->legacy.block_markbad) in nand_markbad_bbm()
537 return chip->legacy.block_markbad(chip, ofs); in nand_markbad_bbm()
543 * nand_block_markbad_lowlevel - mark a block bad
544 * @chip: NAND chip object
547 * This function performs the generic NAND bad block marking steps (i.e., bad
549 * specify how to write bad block markers to OOB (chip->legacy.block_markbad).
566 if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) { in nand_block_markbad_lowlevel()
572 einfo.len = 1ULL << chip->phys_erase_shift; in nand_block_markbad_lowlevel()
585 if (chip->bbt) { in nand_block_markbad_lowlevel()
592 mtd->ecc_stats.badblocks++; in nand_block_markbad_lowlevel()
598 * nand_block_isreserved - [GENERIC] Check if a block is marked reserved.
608 if (!chip->bbt) in nand_block_isreserved()
615 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
616 * @chip: NAND chip object
626 if (chip->bbt) in nand_block_checkbad()
633 * nand_soft_waitrdy - Poll STATUS reg until RDY bit is set to 1
634 * @chip: NAND chip structure
637 * Poll the STATUS register using ->exec_op() until the RDY bit becomes 1.
638 * If that does not happen whitin the specified timeout, -ETIMEDOUT is
642 * to the NAND R/B pin.
644 * Be aware that calling this helper from an ->exec_op() implementation means
645 * ->exec_op() must be re-entrant.
647 * Return 0 if the NAND chip is ready, a negative error otherwise.
656 return -ENOTSUPP; in nand_soft_waitrdy()
669 * small jiffy fraction - possibly leading to false timeout in nand_soft_waitrdy()
699 return status & NAND_STATUS_READY ? 0 : -ETIMEDOUT; in nand_soft_waitrdy()
704 * nand_gpio_waitrdy - Poll R/B GPIO pin until ready
705 * @chip: NAND chip structure
710 * whitin the specified timeout, -ETIMEDOUT is returned.
713 * NAND R/B pin over GPIO.
725 * small jiffy fraction - possibly leading to false timeout. in nand_gpio_waitrdy()
735 return gpiod_get_value_cansleep(gpiod) ? 0 : -ETIMEDOUT; in nand_gpio_waitrdy()
740 * panic_nand_wait - [GENERIC] wait until the command is done
741 * @chip: NAND chip structure
752 if (chip->legacy.dev_ready) { in panic_nand_wait()
753 if (chip->legacy.dev_ready(chip)) in panic_nand_wait()
773 return (chip->parameters.supports_set_get_features && in nand_supports_get_features()
774 test_bit(addr, chip->parameters.get_feature_list)); in nand_supports_get_features()
779 return (chip->parameters.supports_set_get_features && in nand_supports_set_features()
780 test_bit(addr, chip->parameters.set_feature_list)); in nand_supports_set_features()
784 * nand_reset_interface - Reset data interface and timings
785 * @chip: The NAND chip
794 const struct nand_controller_ops *ops = chip->controller->ops; in nand_reset_interface()
803 * To transition from NV-DDR or NV-DDR2 to the SDR data in nand_reset_interface()
814 chip->current_interface_config = nand_get_reset_interface_config(); in nand_reset_interface()
815 ret = ops->setup_interface(chip, chipnr, in nand_reset_interface()
816 chip->current_interface_config); in nand_reset_interface()
824 * nand_setup_interface - Setup the best data interface and timings
825 * @chip: The NAND chip
828 * Configure what has been reported to be the best data interface and NAND
835 const struct nand_controller_ops *ops = chip->controller->ops; in nand_setup_interface()
843 * A nand_reset_interface() put both the NAND chip and the NAND in nand_setup_interface()
846 * nand_setup_interface() uses ->set/get_features() which would in nand_setup_interface()
849 if (!chip->best_interface_config) in nand_setup_interface()
852 request = chip->best_interface_config->timings.mode; in nand_setup_interface()
853 if (nand_interface_is_sdr(chip->best_interface_config)) in nand_setup_interface()
859 /* Change the mode on the chip side (if supported by the NAND chip) */ in nand_setup_interface()
870 ret = ops->setup_interface(chip, chipnr, chip->best_interface_config); in nand_setup_interface()
887 pr_warn("%s timing mode %d not acknowledged by the NAND chip\n", in nand_setup_interface()
888 nand_interface_is_nvddr(chip->best_interface_config) ? "NV-DDR" : "SDR", in nand_setup_interface()
889 chip->best_interface_config->timings.mode); in nand_setup_interface()
890 pr_debug("NAND chip would work in %s timing mode %d\n", in nand_setup_interface()
891 tmode_param[0] & ONFI_DATA_INTERFACE_NVDDR ? "NV-DDR" : "SDR", in nand_setup_interface()
897 chip->current_interface_config = chip->best_interface_config; in nand_setup_interface()
915 * nand_choose_best_sdr_timings - Pick up the best SDR timings that both the
916 * NAND controller and the NAND chip support
917 * @chip: the NAND chip
928 const struct nand_controller_ops *ops = chip->controller->ops; in nand_choose_best_sdr_timings()
931 iface->type = NAND_SDR_IFACE; in nand_choose_best_sdr_timings()
934 iface->timings.sdr = *spec_timings; in nand_choose_best_sdr_timings()
935 iface->timings.mode = onfi_find_closest_sdr_mode(spec_timings); in nand_choose_best_sdr_timings()
938 ret = ops->setup_interface(chip, NAND_DATA_IFACE_CHECK_ONLY, in nand_choose_best_sdr_timings()
941 chip->best_interface_config = iface; in nand_choose_best_sdr_timings()
946 best_mode = iface->timings.mode; in nand_choose_best_sdr_timings()
947 } else if (chip->parameters.onfi) { in nand_choose_best_sdr_timings()
948 best_mode = fls(chip->parameters.onfi->sdr_timing_modes) - 1; in nand_choose_best_sdr_timings()
951 for (mode = best_mode; mode >= 0; mode--) { in nand_choose_best_sdr_timings()
954 ret = ops->setup_interface(chip, NAND_DATA_IFACE_CHECK_ONLY, in nand_choose_best_sdr_timings()
957 chip->best_interface_config = iface; in nand_choose_best_sdr_timings()
966 * nand_choose_best_nvddr_timings - Pick up the best NVDDR timings that both the
967 * NAND controller and the NAND chip support
968 * @chip: the NAND chip
979 const struct nand_controller_ops *ops = chip->controller->ops; in nand_choose_best_nvddr_timings()
982 iface->type = NAND_NVDDR_IFACE; in nand_choose_best_nvddr_timings()
985 iface->timings.nvddr = *spec_timings; in nand_choose_best_nvddr_timings()
986 iface->timings.mode = onfi_find_closest_nvddr_mode(spec_timings); in nand_choose_best_nvddr_timings()
989 ret = ops->setup_interface(chip, NAND_DATA_IFACE_CHECK_ONLY, in nand_choose_best_nvddr_timings()
992 chip->best_interface_config = iface; in nand_choose_best_nvddr_timings()
997 best_mode = iface->timings.mode; in nand_choose_best_nvddr_timings()
998 } else if (chip->parameters.onfi) { in nand_choose_best_nvddr_timings()
999 best_mode = fls(chip->parameters.onfi->nvddr_timing_modes) - 1; in nand_choose_best_nvddr_timings()
1002 for (mode = best_mode; mode >= 0; mode--) { in nand_choose_best_nvddr_timings()
1005 ret = ops->setup_interface(chip, NAND_DATA_IFACE_CHECK_ONLY, in nand_choose_best_nvddr_timings()
1008 chip->best_interface_config = iface; in nand_choose_best_nvddr_timings()
1017 * nand_choose_best_timings - Pick up the best NVDDR or SDR timings that both
1018 * NAND controller and the NAND chip support
1019 * @chip: the NAND chip
1030 /* Try the fastest timings: NV-DDR */ in nand_choose_best_timings()
1040 * nand_choose_interface_config - find the best data interface and timings
1041 * @chip: The NAND chip
1043 * Find the best data interface and NAND timings supported by the chip
1044 * and the driver. Eventually let the NAND manufacturer driver propose his own
1047 * After this function nand_chip->interface_config is initialized with the best
1062 return -ENOMEM; in nand_choose_interface_config()
1064 if (chip->ops.choose_interface_config) in nand_choose_interface_config()
1065 ret = chip->ops.choose_interface_config(chip, iface); in nand_choose_interface_config()
1076 * nand_fill_column_cycles - fill the column cycles of an address
1077 * @chip: The NAND chip
1082 * on the NAND bus width and the page size.
1093 if (offset_in_page > mtd->writesize + mtd->oobsize) in nand_fill_column_cycles()
1094 return -EINVAL; in nand_fill_column_cycles()
1101 if (mtd->writesize <= 512 && offset_in_page >= mtd->writesize) in nand_fill_column_cycles()
1102 offset_in_page -= mtd->writesize; in nand_fill_column_cycles()
1105 * The offset in page is expressed in bytes, if the NAND bus is 16-bit in nand_fill_column_cycles()
1108 if (chip->options & NAND_BUSWIDTH_16) { in nand_fill_column_cycles()
1110 return -EINVAL; in nand_fill_column_cycles()
1121 if (mtd->writesize <= 512) in nand_fill_column_cycles()
1144 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); in nand_sp_exec_read_page_op()
1149 op.ninstrs--; in nand_sp_exec_read_page_op()
1151 if (offset_in_page >= mtd->writesize) in nand_sp_exec_read_page_op()
1154 !(chip->options & NAND_BUSWIDTH_16)) in nand_sp_exec_read_page_op()
1164 if (chip->options & NAND_ROW_ADDR_3) { in nand_sp_exec_read_page_op()
1187 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); in nand_lp_exec_read_page_op()
1192 op.ninstrs--; in nand_lp_exec_read_page_op()
1201 if (chip->options & NAND_ROW_ADDR_3) { in nand_lp_exec_read_page_op()
1210 * nand_read_page_op - Do a READ PAGE operation
1211 * @chip: The NAND chip
1228 return -EINVAL; in nand_read_page_op()
1230 if (offset_in_page + len > mtd->writesize + mtd->oobsize) in nand_read_page_op()
1231 return -EINVAL; in nand_read_page_op()
1234 if (mtd->writesize > 512) in nand_read_page_op()
1243 chip->legacy.cmdfunc(chip, NAND_CMD_READ0, offset_in_page, page); in nand_read_page_op()
1245 chip->legacy.read_buf(chip, buf, len); in nand_read_page_op()
1252 * nand_read_param_page_op - Do a READ PARAMETER PAGE operation
1253 * @chip: The NAND chip
1270 return -EINVAL; in nand_read_param_page_op()
1283 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); in nand_read_param_page_op()
1287 op.ninstrs--; in nand_read_param_page_op()
1292 chip->legacy.cmdfunc(chip, NAND_CMD_PARAM, page, -1); in nand_read_param_page_op()
1294 p[i] = chip->legacy.read_byte(chip); in nand_read_param_page_op()
1300 * nand_change_read_column_op - Do a CHANGE READ COLUMN operation
1301 * @chip: The NAND chip
1305 * @force_8bit: force 8-bit bus access
1319 return -EINVAL; in nand_change_read_column_op()
1321 if (offset_in_page + len > mtd->writesize + mtd->oobsize) in nand_change_read_column_op()
1322 return -EINVAL; in nand_change_read_column_op()
1325 if (mtd->writesize <= 512) in nand_change_read_column_op()
1326 return -ENOTSUPP; in nand_change_read_column_op()
1339 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); in nand_change_read_column_op()
1348 op.ninstrs--; in nand_change_read_column_op()
1355 chip->legacy.cmdfunc(chip, NAND_CMD_RNDOUT, offset_in_page, -1); in nand_change_read_column_op()
1357 chip->legacy.read_buf(chip, buf, len); in nand_change_read_column_op()
1364 * nand_read_oob_op - Do a READ OOB operation
1365 * @chip: The NAND chip
1382 return -EINVAL; in nand_read_oob_op()
1384 if (offset_in_oob + len > mtd->oobsize) in nand_read_oob_op()
1385 return -EINVAL; in nand_read_oob_op()
1389 mtd->writesize + offset_in_oob, in nand_read_oob_op()
1392 chip->legacy.cmdfunc(chip, NAND_CMD_READOOB, offset_in_oob, page); in nand_read_oob_op()
1394 chip->legacy.read_buf(chip, buf, len); in nand_read_oob_op()
1411 * with a large page NAND and adjusted if we're dealing in nand_exec_prog_page_op()
1412 * with a small page NAND and the page offset is > 255. in nand_exec_prog_page_op()
1422 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); in nand_exec_prog_page_op()
1430 if (chip->options & NAND_ROW_ADDR_3) in nand_exec_prog_page_op()
1437 op.ninstrs -= 2; in nand_exec_prog_page_op()
1440 op.ninstrs--; in nand_exec_prog_page_op()
1443 if (mtd->writesize <= 512) { in nand_exec_prog_page_op()
1449 if (offset_in_page >= mtd->writesize) in nand_exec_prog_page_op()
1452 !(chip->options & NAND_BUSWIDTH_16)) in nand_exec_prog_page_op()
1457 * NAND. in nand_exec_prog_page_op()
1460 op.ninstrs--; in nand_exec_prog_page_op()
1467 * nand_prog_page_begin_op - starts a PROG PAGE operation
1468 * @chip: The NAND chip
1486 return -EINVAL; in nand_prog_page_begin_op()
1488 if (offset_in_page + len > mtd->writesize + mtd->oobsize) in nand_prog_page_begin_op()
1489 return -EINVAL; in nand_prog_page_begin_op()
1495 chip->legacy.cmdfunc(chip, NAND_CMD_SEQIN, offset_in_page, page); in nand_prog_page_begin_op()
1498 chip->legacy.write_buf(chip, buf, len); in nand_prog_page_begin_op()
1505 * nand_prog_page_end_op - ends a PROG PAGE operation
1506 * @chip: The NAND chip
1527 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); in nand_prog_page_end_op()
1537 chip->legacy.cmdfunc(chip, NAND_CMD_PAGEPROG, -1, -1); in nand_prog_page_end_op()
1538 ret = chip->legacy.waitfunc(chip); in nand_prog_page_end_op()
1546 return -EIO; in nand_prog_page_end_op()
1553 * nand_prog_page_op - Do a full PROG PAGE operation
1554 * @chip: The NAND chip
1574 return -EINVAL; in nand_prog_page_op()
1576 if (offset_in_page + len > mtd->writesize + mtd->oobsize) in nand_prog_page_op()
1577 return -EINVAL; in nand_prog_page_op()
1589 chip->legacy.cmdfunc(chip, NAND_CMD_SEQIN, offset_in_page, in nand_prog_page_op()
1591 chip->legacy.write_buf(chip, buf, len); in nand_prog_page_op()
1592 chip->legacy.cmdfunc(chip, NAND_CMD_PAGEPROG, -1, -1); in nand_prog_page_op()
1593 ret = chip->legacy.waitfunc(chip); in nand_prog_page_op()
1601 return -EIO; in nand_prog_page_op()
1608 * nand_change_write_column_op - Do a CHANGE WRITE COLUMN operation
1609 * @chip: The NAND chip
1611 * @buf: buffer containing the data to send to the NAND
1613 * @force_8bit: force 8-bit bus access
1628 return -EINVAL; in nand_change_write_column_op()
1630 if (offset_in_page + len > mtd->writesize + mtd->oobsize) in nand_change_write_column_op()
1631 return -EINVAL; in nand_change_write_column_op()
1634 if (mtd->writesize <= 512) in nand_change_write_column_op()
1635 return -ENOTSUPP; in nand_change_write_column_op()
1646 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); in nand_change_write_column_op()
1657 op.ninstrs--; in nand_change_write_column_op()
1662 chip->legacy.cmdfunc(chip, NAND_CMD_RNDIN, offset_in_page, -1); in nand_change_write_column_op()
1664 chip->legacy.write_buf(chip, buf, len); in nand_change_write_column_op()
1671 * nand_readid_op - Do a READID operation
1672 * @chip: The NAND chip
1678 * NAND.
1690 return -EINVAL; in nand_readid_op()
1701 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); in nand_readid_op()
1704 /* READ_ID data bytes are received twice in NV-DDR mode */ in nand_readid_op()
1708 return -ENOMEM; in nand_readid_op()
1716 op.ninstrs--; in nand_readid_op()
1729 chip->legacy.cmdfunc(chip, NAND_CMD_READID, addr, -1); in nand_readid_op()
1732 id[i] = chip->legacy.read_byte(chip); in nand_readid_op()
1739 * nand_status_op - Do a STATUS operation
1740 * @chip: The NAND chip
1741 * @status: out variable to store the NAND status
1744 * the NAND.
1760 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); in nand_status_op()
1763 /* The status data byte will be received twice in NV-DDR mode */ in nand_status_op()
1770 op.ninstrs--; in nand_status_op()
1779 chip->legacy.cmdfunc(chip, NAND_CMD_STATUS, -1, -1); in nand_status_op()
1781 *status = chip->legacy.read_byte(chip); in nand_status_op()
1788 * nand_exit_status_op - Exit a STATUS operation
1789 * @chip: The NAND chip
1804 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); in nand_exit_status_op()
1809 chip->legacy.cmdfunc(chip, NAND_CMD_READ0, -1, -1); in nand_exit_status_op()
1815 * nand_erase_op - Do an erase operation
1816 * @chip: The NAND chip
1819 * This function sends an ERASE command and waits for the NAND to be ready
1828 (chip->phys_erase_shift - chip->page_shift); in nand_erase_op()
1844 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); in nand_erase_op()
1846 if (chip->options & NAND_ROW_ADDR_3) in nand_erase_op()
1857 chip->legacy.cmdfunc(chip, NAND_CMD_ERASE1, -1, page); in nand_erase_op()
1858 chip->legacy.cmdfunc(chip, NAND_CMD_ERASE2, -1, -1); in nand_erase_op()
1860 ret = chip->legacy.waitfunc(chip); in nand_erase_op()
1868 return -EIO; in nand_erase_op()
1875 * nand_set_features_op - Do a SET FEATURES operation
1876 * @chip: The NAND chip
1880 * This function sends a SET FEATURES command and waits for the NAND to be
1905 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); in nand_set_features_op()
1910 chip->legacy.cmdfunc(chip, NAND_CMD_SET_FEATURES, feature, -1); in nand_set_features_op()
1912 chip->legacy.write_byte(chip, params[i]); in nand_set_features_op()
1914 ret = chip->legacy.waitfunc(chip); in nand_set_features_op()
1919 return -EIO; in nand_set_features_op()
1925 * nand_get_features_op - Do a GET FEATURES operation
1926 * @chip: The NAND chip
1930 * This function sends a GET FEATURES command and waits for the NAND to be
1954 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); in nand_get_features_op()
1957 /* GET_FEATURE data bytes are received twice in NV-DDR mode */ in nand_get_features_op()
1972 chip->legacy.cmdfunc(chip, NAND_CMD_GET_FEATURES, feature, -1); in nand_get_features_op()
1974 params[i] = chip->legacy.read_byte(chip); in nand_get_features_op()
1987 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); in nand_wait_rdy_op()
1993 if (!chip->legacy.dev_ready) in nand_wait_rdy_op()
1994 udelay(chip->legacy.chip_delay); in nand_wait_rdy_op()
2002 * nand_reset_op - Do a reset operation
2003 * @chip: The NAND chip
2005 * This function sends a RESET command and waits for the NAND to be ready
2022 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); in nand_reset_op()
2027 chip->legacy.cmdfunc(chip, NAND_CMD_RESET, -1, -1); in nand_reset_op()
2034 * nand_read_data_op - Read data from the NAND
2035 * @chip: The NAND chip
2038 * @force_8bit: force 8-bit bus access
2043 * another NAND operation like nand_read_page_op().
2052 return -EINVAL; in nand_read_data_op()
2060 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); in nand_read_data_op()
2070 * case NV-DDR timings are being used the data will be received in nand_read_data_op()
2076 return -ENOMEM; in nand_read_data_op()
2109 p[i] = chip->legacy.read_byte(chip); in nand_read_data_op()
2111 chip->legacy.read_buf(chip, buf, len); in nand_read_data_op()
2119 * nand_write_data_op - Write data from the NAND
2120 * @chip: The NAND chip
2123 * @force_8bit: force 8-bit bus access
2126 * another NAND operation like nand_write_page_begin_op().
2135 return -EINVAL; in nand_write_data_op()
2141 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); in nand_write_data_op()
2153 chip->legacy.write_byte(chip, p[i]); in nand_write_data_op()
2155 chip->legacy.write_buf(chip, buf, len); in nand_write_data_op()
2163 * struct nand_op_parser_ctx - Context used by the parser
2166 * @subop: Sub-operation to be passed to the NAND controller
2168 * This structure is used by the core to split NAND operations into
2169 * sub-operations that can be handled by the NAND controller.
2178 * nand_op_parser_must_split_instr - Checks if an instruction must be split
2188 * Some NAND controllers are limited and cannot send X address cycles with a
2191 * controller-operation into two or more chunks.
2202 switch (pat->type) { in nand_op_parser_must_split_instr()
2204 if (!pat->ctx.addr.maxcycles) in nand_op_parser_must_split_instr()
2207 if (instr->ctx.addr.naddrs - *start_offset > in nand_op_parser_must_split_instr()
2208 pat->ctx.addr.maxcycles) { in nand_op_parser_must_split_instr()
2209 *start_offset += pat->ctx.addr.maxcycles; in nand_op_parser_must_split_instr()
2216 if (!pat->ctx.data.maxlen) in nand_op_parser_must_split_instr()
2219 if (instr->ctx.data.len - *start_offset > in nand_op_parser_must_split_instr()
2220 pat->ctx.data.maxlen) { in nand_op_parser_must_split_instr()
2221 *start_offset += pat->ctx.data.maxlen; in nand_op_parser_must_split_instr()
2234 * nand_op_parser_match_pat - Checks if a pattern matches the instructions
2239 * Check if @pat matches the set or a sub-set of instructions remaining in @ctx.
2241 * @ctx->subop is updated with the set of instructions to be passed to the
2248 unsigned int instr_offset = ctx->subop.first_instr_start_off; in nand_op_parser_match_pat()
2249 const struct nand_op_instr *end = ctx->instrs + ctx->ninstrs; in nand_op_parser_match_pat()
2250 const struct nand_op_instr *instr = ctx->subop.instrs; in nand_op_parser_match_pat()
2253 for (i = 0, ninstrs = 0; i < pat->nelems && instr < end; i++) { in nand_op_parser_match_pat()
2261 if (instr->type != pat->elems[i].type) { in nand_op_parser_match_pat()
2262 if (!pat->elems[i].optional) in nand_op_parser_match_pat()
2276 if (nand_op_parser_must_split_instr(&pat->elems[i], instr, in nand_op_parser_match_pat()
2302 for (; i < pat->nelems; i++) { in nand_op_parser_match_pat()
2303 if (!pat->elems[i].optional) in nand_op_parser_match_pat()
2311 ctx->subop.ninstrs = ninstrs; in nand_op_parser_match_pat()
2312 ctx->subop.last_instr_end_off = instr_offset; in nand_op_parser_match_pat()
2324 pr_debug("executing subop (CS%d):\n", ctx->subop.cs); in nand_op_parser_trace()
2326 for (i = 0; i < ctx->ninstrs; i++) { in nand_op_parser_trace()
2327 instr = &ctx->instrs[i]; in nand_op_parser_trace()
2329 if (instr == &ctx->subop.instrs[0]) in nand_op_parser_trace()
2330 prefix = " ->"; in nand_op_parser_trace()
2334 if (instr == &ctx->subop.instrs[ctx->subop.ninstrs - 1]) in nand_op_parser_trace()
2348 if (a->subop.ninstrs < b->subop.ninstrs) in nand_op_parser_cmp_ctx()
2349 return -1; in nand_op_parser_cmp_ctx()
2350 else if (a->subop.ninstrs > b->subop.ninstrs) in nand_op_parser_cmp_ctx()
2353 if (a->subop.last_instr_end_off < b->subop.last_instr_end_off) in nand_op_parser_cmp_ctx()
2354 return -1; in nand_op_parser_cmp_ctx()
2355 else if (a->subop.last_instr_end_off > b->subop.last_instr_end_off) in nand_op_parser_cmp_ctx()
2362 * nand_op_parser_exec_op - exec_op parser
2363 * @chip: the NAND chip
2365 * @op: the NAND operation to address
2369 * Helper function designed to ease integration of NAND controller drivers that
2372 * multiple sub-operations (if required) and pass them back to the ->exec()
2375 * NAND controller drivers should call this function from their own ->exec_op()
2381 * matching pattern->exec() hook.
2388 .subop.cs = op->cs, in nand_op_parser_exec_op()
2389 .subop.instrs = op->instrs, in nand_op_parser_exec_op()
2390 .instrs = op->instrs, in nand_op_parser_exec_op()
2391 .ninstrs = op->ninstrs, in nand_op_parser_exec_op()
2395 while (ctx.subop.instrs < op->instrs + op->ninstrs) { in nand_op_parser_exec_op()
2398 int ret, best_pattern = -1; in nand_op_parser_exec_op()
2400 for (i = 0; i < parser->npatterns; i++) { in nand_op_parser_exec_op()
2403 pattern = &parser->patterns[i]; in nand_op_parser_exec_op()
2416 pr_debug("->exec_op() parser: pattern not found!\n"); in nand_op_parser_exec_op()
2417 return -ENOTSUPP; in nand_op_parser_exec_op()
2424 pattern = &parser->patterns[best_pattern]; in nand_op_parser_exec_op()
2425 ret = pattern->exec(chip, &ctx.subop); in nand_op_parser_exec_op()
2436 ctx.subop.instrs -= 1; in nand_op_parser_exec_op()
2447 return instr && (instr->type == NAND_OP_DATA_IN_INSTR || in nand_instr_is_data()
2448 instr->type == NAND_OP_DATA_OUT_INSTR); in nand_instr_is_data()
2454 return subop && instr_idx < subop->ninstrs; in nand_subop_instr_is_valid()
2463 return subop->first_instr_start_off; in nand_subop_get_start_off()
2467 * nand_subop_get_addr_start_off - Get the start offset in an address array
2468 * @subop: The entire sub-operation
2469 * @instr_idx: Index of the instruction inside the sub-operation
2472 * ->addr.addrs field of address instructions. This is wrong as address
2481 subop->instrs[instr_idx].type != NAND_OP_ADDR_INSTR)) in nand_subop_get_addr_start_off()
2489 * nand_subop_get_num_addr_cyc - Get the remaining address cycles to assert
2490 * @subop: The entire sub-operation
2491 * @instr_idx: Index of the instruction inside the sub-operation
2494 * ->addr->naddrs field of a data instruction. This is wrong as instructions
2505 subop->instrs[instr_idx].type != NAND_OP_ADDR_INSTR)) in nand_subop_get_num_addr_cyc()
2510 if (instr_idx == subop->ninstrs - 1 && in nand_subop_get_num_addr_cyc()
2511 subop->last_instr_end_off) in nand_subop_get_num_addr_cyc()
2512 end_off = subop->last_instr_end_off; in nand_subop_get_num_addr_cyc()
2514 end_off = subop->instrs[instr_idx].ctx.addr.naddrs; in nand_subop_get_num_addr_cyc()
2516 return end_off - start_off; in nand_subop_get_num_addr_cyc()
2521 * nand_subop_get_data_start_off - Get the start offset in a data array
2522 * @subop: The entire sub-operation
2523 * @instr_idx: Index of the instruction inside the sub-operation
2526 * ->data->buf.{in,out} field of data instructions. This is wrong as data
2535 !nand_instr_is_data(&subop->instrs[instr_idx]))) in nand_subop_get_data_start_off()
2543 * nand_subop_get_data_len - Get the number of bytes to retrieve
2544 * @subop: The entire sub-operation
2545 * @instr_idx: Index of the instruction inside the sub-operation
2548 * ->data->len field of a data instruction. This is wrong as data instructions
2559 !nand_instr_is_data(&subop->instrs[instr_idx]))) in nand_subop_get_data_len()
2564 if (instr_idx == subop->ninstrs - 1 && in nand_subop_get_data_len()
2565 subop->last_instr_end_off) in nand_subop_get_data_len()
2566 end_off = subop->last_instr_end_off; in nand_subop_get_data_len()
2568 end_off = subop->instrs[instr_idx].ctx.data.len; in nand_subop_get_data_len()
2570 return end_off - start_off; in nand_subop_get_data_len()
2575 * nand_reset - Reset and initialize a NAND device
2576 * @chip: The NAND chip
2594 * The CS line has to be released before we can apply the new NAND in nand_reset()
2613 * nand_get_features - wrapper to perform a GET_FEATURE
2614 * @chip: NAND chip info structure
2618 * Returns 0 for success, a negative error otherwise. Returns -ENOTSUPP if the
2625 return -ENOTSUPP; in nand_get_features()
2627 if (chip->legacy.get_features) in nand_get_features()
2628 return chip->legacy.get_features(chip, addr, subfeature_param); in nand_get_features()
2634 * nand_set_features - wrapper to perform a SET_FEATURE
2635 * @chip: NAND chip info structure
2639 * Returns 0 for success, a negative error otherwise. Returns -ENOTSUPP if the
2646 return -ENOTSUPP; in nand_set_features()
2648 if (chip->legacy.set_features) in nand_set_features()
2649 return chip->legacy.set_features(chip, addr, subfeature_param); in nand_set_features()
2655 * nand_check_erased_buf - check if a buffer contains (almost) only 0xff data
2670 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
2680 len--, bitmap++) { in nand_check_erased_buf()
2682 bitflips += BITS_PER_BYTE - weight; in nand_check_erased_buf()
2684 return -EBADMSG; in nand_check_erased_buf()
2688 len -= sizeof(long), bitmap += sizeof(long)) { in nand_check_erased_buf()
2693 bitflips += BITS_PER_LONG - weight; in nand_check_erased_buf()
2695 return -EBADMSG; in nand_check_erased_buf()
2698 for (; len > 0; len--, bitmap++) { in nand_check_erased_buf()
2700 bitflips += BITS_PER_BYTE - weight; in nand_check_erased_buf()
2702 return -EBADMSG; in nand_check_erased_buf()
2709 * nand_check_erased_ecc_chunk - check if an ECC chunk contains (almost) only
2713 * @ecc: ECC buffer
2714 * @ecclen: ECC length
2719 * Check if a data buffer and its associated ECC and OOB data contains only
2726 * 1/ ECC algorithms are working on pre-defined block sizes which are usually
2727 * different from the NAND page size. When fixing bitflips, ECC engines will
2728 * report the number of errors per chunk, and the NAND core infrastructure
2734 * the payload data but also their associated ECC data, because a user might
2736 * shouldn't consider the chunk as erased, and checking ECC bytes prevent
2739 * data are protected by the ECC engine.
2741 * extra OOB data to an ECC chunk.
2744 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
2748 void *ecc, int ecclen, in nand_check_erased_ecc_chunk() argument
2759 bitflips_threshold -= data_bitflips; in nand_check_erased_ecc_chunk()
2761 ecc_bitflips = nand_check_erased_buf(ecc, ecclen, bitflips_threshold); in nand_check_erased_ecc_chunk()
2765 bitflips_threshold -= ecc_bitflips; in nand_check_erased_ecc_chunk()
2776 memset(ecc, 0xff, ecclen); in nand_check_erased_ecc_chunk()
2786 * nand_read_page_raw_notsupp - dummy read raw page function
2787 * @chip: nand chip info structure
2789 * @oob_required: caller requires OOB data read to chip->oob_poi
2792 * Returns -ENOTSUPP unconditionally.
2797 return -ENOTSUPP; in nand_read_page_raw_notsupp()
2801 * nand_read_page_raw - [INTERN] read raw page data without ecc
2802 * @chip: nand chip info structure
2804 * @oob_required: caller requires OOB data read to chip->oob_poi
2807 * Not for syndrome calculating ECC controllers, which use a special oob layout.
2815 ret = nand_read_page_op(chip, page, 0, buf, mtd->writesize); in nand_read_page_raw()
2820 ret = nand_read_data_op(chip, chip->oob_poi, mtd->oobsize, in nand_read_page_raw()
2831 * nand_monolithic_read_page_raw - Monolithic page read in raw mode
2832 * @chip: NAND chip info structure
2834 * @oob_required: caller requires OOB data read to chip->oob_poi
2839 * eventually OOB) to be loaded in the NAND cache and sent over the
2840 * bus (from the NAND chip to the NAND controller) in a single
2849 unsigned int size = mtd->writesize; in nand_monolithic_read_page_raw()
2854 size += mtd->oobsize; in nand_monolithic_read_page_raw()
2856 if (buf != chip->data_buf) in nand_monolithic_read_page_raw()
2864 if (buf != chip->data_buf) in nand_monolithic_read_page_raw()
2865 memcpy(buf, read_buf, mtd->writesize); in nand_monolithic_read_page_raw()
2872 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
2873 * @chip: nand chip info structure
2875 * @oob_required: caller requires OOB data read to chip->oob_poi
2884 int eccsize = chip->ecc.size; in nand_read_page_raw_syndrome()
2885 int eccbytes = chip->ecc.bytes; in nand_read_page_raw_syndrome()
2886 uint8_t *oob = chip->oob_poi; in nand_read_page_raw_syndrome()
2893 for (steps = chip->ecc.steps; steps > 0; steps--) { in nand_read_page_raw_syndrome()
2900 if (chip->ecc.prepad) { in nand_read_page_raw_syndrome()
2901 ret = nand_read_data_op(chip, oob, chip->ecc.prepad, in nand_read_page_raw_syndrome()
2906 oob += chip->ecc.prepad; in nand_read_page_raw_syndrome()
2915 if (chip->ecc.postpad) { in nand_read_page_raw_syndrome()
2916 ret = nand_read_data_op(chip, oob, chip->ecc.postpad, in nand_read_page_raw_syndrome()
2921 oob += chip->ecc.postpad; in nand_read_page_raw_syndrome()
2925 size = mtd->oobsize - (oob - chip->oob_poi); in nand_read_page_raw_syndrome()
2936 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
2937 * @chip: nand chip info structure
2939 * @oob_required: caller requires OOB data read to chip->oob_poi
2946 int i, eccsize = chip->ecc.size, ret; in nand_read_page_swecc()
2947 int eccbytes = chip->ecc.bytes; in nand_read_page_swecc()
2948 int eccsteps = chip->ecc.steps; in nand_read_page_swecc()
2950 uint8_t *ecc_calc = chip->ecc.calc_buf; in nand_read_page_swecc()
2951 uint8_t *ecc_code = chip->ecc.code_buf; in nand_read_page_swecc()
2954 chip->ecc.read_page_raw(chip, buf, 1, page); in nand_read_page_swecc()
2956 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) in nand_read_page_swecc()
2957 chip->ecc.calculate(chip, p, &ecc_calc[i]); in nand_read_page_swecc()
2959 ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0, in nand_read_page_swecc()
2960 chip->ecc.total); in nand_read_page_swecc()
2964 eccsteps = chip->ecc.steps; in nand_read_page_swecc()
2967 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { in nand_read_page_swecc()
2970 stat = chip->ecc.correct(chip, p, &ecc_code[i], &ecc_calc[i]); in nand_read_page_swecc()
2972 mtd->ecc_stats.failed++; in nand_read_page_swecc()
2974 mtd->ecc_stats.corrected += stat; in nand_read_page_swecc()
2982 * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
2983 * @chip: nand chip info structure
2997 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1; in nand_read_subpage()
3002 /* Column address within the page aligned to ECC size (256bytes) */ in nand_read_subpage()
3003 start_step = data_offs / chip->ecc.size; in nand_read_subpage()
3004 end_step = (data_offs + readlen - 1) / chip->ecc.size; in nand_read_subpage()
3005 num_steps = end_step - start_step + 1; in nand_read_subpage()
3006 index = start_step * chip->ecc.bytes; in nand_read_subpage()
3008 /* Data size aligned to ECC ecc.size */ in nand_read_subpage()
3009 datafrag_len = num_steps * chip->ecc.size; in nand_read_subpage()
3010 eccfrag_len = num_steps * chip->ecc.bytes; in nand_read_subpage()
3012 data_col_addr = start_step * chip->ecc.size; in nand_read_subpage()
3019 /* Calculate ECC */ in nand_read_subpage()
3020 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) in nand_read_subpage()
3021 chip->ecc.calculate(chip, p, &chip->ecc.calc_buf[i]); in nand_read_subpage()
3025 * ecc.pos. Let's make sure that there are no gaps in ECC positions. in nand_read_subpage()
3035 ret = nand_change_read_column_op(chip, mtd->writesize, in nand_read_subpage()
3036 chip->oob_poi, mtd->oobsize, in nand_read_subpage()
3042 * Send the command to read the particular ECC bytes take care in nand_read_subpage()
3045 aligned_pos = oobregion.offset & ~(busw - 1); in nand_read_subpage()
3047 if (oobregion.offset & (busw - 1)) in nand_read_subpage()
3049 if ((oobregion.offset + (num_steps * chip->ecc.bytes)) & in nand_read_subpage()
3050 (busw - 1)) in nand_read_subpage()
3054 mtd->writesize + aligned_pos, in nand_read_subpage()
3055 &chip->oob_poi[aligned_pos], in nand_read_subpage()
3061 ret = mtd_ooblayout_get_eccbytes(mtd, chip->ecc.code_buf, in nand_read_subpage()
3062 chip->oob_poi, index, eccfrag_len); in nand_read_subpage()
3067 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) { in nand_read_subpage()
3070 stat = chip->ecc.correct(chip, p, &chip->ecc.code_buf[i], in nand_read_subpage()
3071 &chip->ecc.calc_buf[i]); in nand_read_subpage()
3072 if (stat == -EBADMSG && in nand_read_subpage()
3073 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { in nand_read_subpage()
3075 stat = nand_check_erased_ecc_chunk(p, chip->ecc.size, in nand_read_subpage()
3076 &chip->ecc.code_buf[i], in nand_read_subpage()
3077 chip->ecc.bytes, in nand_read_subpage()
3079 chip->ecc.strength); in nand_read_subpage()
3083 mtd->ecc_stats.failed++; in nand_read_subpage()
3085 mtd->ecc_stats.corrected += stat; in nand_read_subpage()
3093 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
3094 * @chip: nand chip info structure
3096 * @oob_required: caller requires OOB data read to chip->oob_poi
3099 * Not for syndrome calculating ECC controllers which need a special oob layout.
3105 int i, eccsize = chip->ecc.size, ret; in nand_read_page_hwecc()
3106 int eccbytes = chip->ecc.bytes; in nand_read_page_hwecc()
3107 int eccsteps = chip->ecc.steps; in nand_read_page_hwecc()
3109 uint8_t *ecc_calc = chip->ecc.calc_buf; in nand_read_page_hwecc()
3110 uint8_t *ecc_code = chip->ecc.code_buf; in nand_read_page_hwecc()
3117 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { in nand_read_page_hwecc()
3118 chip->ecc.hwctl(chip, NAND_ECC_READ); in nand_read_page_hwecc()
3124 chip->ecc.calculate(chip, p, &ecc_calc[i]); in nand_read_page_hwecc()
3127 ret = nand_read_data_op(chip, chip->oob_poi, mtd->oobsize, false, in nand_read_page_hwecc()
3132 ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0, in nand_read_page_hwecc()
3133 chip->ecc.total); in nand_read_page_hwecc()
3137 eccsteps = chip->ecc.steps; in nand_read_page_hwecc()
3140 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { in nand_read_page_hwecc()
3143 stat = chip->ecc.correct(chip, p, &ecc_code[i], &ecc_calc[i]); in nand_read_page_hwecc()
3144 if (stat == -EBADMSG && in nand_read_page_hwecc()
3145 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { in nand_read_page_hwecc()
3150 chip->ecc.strength); in nand_read_page_hwecc()
3154 mtd->ecc_stats.failed++; in nand_read_page_hwecc()
3156 mtd->ecc_stats.corrected += stat; in nand_read_page_hwecc()
3164 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
3165 * @chip: nand chip info structure
3167 * @oob_required: caller requires OOB data read to chip->oob_poi
3177 int ret, i, eccsize = chip->ecc.size; in nand_read_page_syndrome()
3178 int eccbytes = chip->ecc.bytes; in nand_read_page_syndrome()
3179 int eccsteps = chip->ecc.steps; in nand_read_page_syndrome()
3180 int eccpadbytes = eccbytes + chip->ecc.prepad + chip->ecc.postpad; in nand_read_page_syndrome()
3182 uint8_t *oob = chip->oob_poi; in nand_read_page_syndrome()
3189 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { in nand_read_page_syndrome()
3192 chip->ecc.hwctl(chip, NAND_ECC_READ); in nand_read_page_syndrome()
3198 if (chip->ecc.prepad) { in nand_read_page_syndrome()
3199 ret = nand_read_data_op(chip, oob, chip->ecc.prepad, in nand_read_page_syndrome()
3204 oob += chip->ecc.prepad; in nand_read_page_syndrome()
3207 chip->ecc.hwctl(chip, NAND_ECC_READSYN); in nand_read_page_syndrome()
3213 stat = chip->ecc.correct(chip, p, oob, NULL); in nand_read_page_syndrome()
3217 if (chip->ecc.postpad) { in nand_read_page_syndrome()
3218 ret = nand_read_data_op(chip, oob, chip->ecc.postpad, in nand_read_page_syndrome()
3223 oob += chip->ecc.postpad; in nand_read_page_syndrome()
3226 if (stat == -EBADMSG && in nand_read_page_syndrome()
3227 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { in nand_read_page_syndrome()
3229 stat = nand_check_erased_ecc_chunk(p, chip->ecc.size, in nand_read_page_syndrome()
3230 oob - eccpadbytes, in nand_read_page_syndrome()
3233 chip->ecc.strength); in nand_read_page_syndrome()
3237 mtd->ecc_stats.failed++; in nand_read_page_syndrome()
3239 mtd->ecc_stats.corrected += stat; in nand_read_page_syndrome()
3245 i = mtd->oobsize - (oob - chip->oob_poi); in nand_read_page_syndrome()
3256 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
3257 * @chip: NAND chip object
3268 switch (ops->mode) { in nand_transfer_oob()
3272 memcpy(oob, chip->oob_poi + ops->ooboffs, len); in nand_transfer_oob()
3276 ret = mtd_ooblayout_get_databytes(mtd, oob, chip->oob_poi, in nand_transfer_oob()
3277 ops->ooboffs, len); in nand_transfer_oob()
3288 * nand_setup_read_retry - [INTERN] Set the READ RETRY mode
3289 * @chip: NAND chip object
3293 * when there are too many bitflips in a page (i.e., ECC error). After setting
3300 if (retry_mode >= chip->read_retries) in nand_setup_read_retry()
3301 return -EINVAL; in nand_setup_read_retry()
3303 if (!chip->ops.setup_read_retry) in nand_setup_read_retry()
3304 return -EOPNOTSUPP; in nand_setup_read_retry()
3306 return chip->ops.setup_read_retry(chip, retry_mode); in nand_setup_read_retry()
3313 if (!(chip->options & NAND_NEED_READRDY)) in nand_wait_readrdy()
3321 * nand_do_read_ops - [INTERN] Read data with ECC
3322 * @chip: NAND chip object
3334 uint32_t readlen = ops->len; in nand_do_read_ops()
3335 uint32_t oobreadlen = ops->ooblen; in nand_do_read_ops()
3346 return -EIO; in nand_do_read_ops()
3348 chipnr = (int)(from >> chip->chip_shift); in nand_do_read_ops()
3351 realpage = (int)(from >> chip->page_shift); in nand_do_read_ops()
3352 page = realpage & chip->pagemask; in nand_do_read_ops()
3354 col = (int)(from & (mtd->writesize - 1)); in nand_do_read_ops()
3356 buf = ops->datbuf; in nand_do_read_ops()
3357 oob = ops->oobbuf; in nand_do_read_ops()
3361 struct mtd_ecc_stats ecc_stats = mtd->ecc_stats; in nand_do_read_ops()
3363 bytes = min(mtd->writesize - col, readlen); in nand_do_read_ops()
3364 aligned = (bytes == mtd->writesize); in nand_do_read_ops()
3368 else if (chip->options & NAND_USES_DMA) in nand_do_read_ops()
3371 chip->buf_align); in nand_do_read_ops()
3376 if (realpage != chip->pagecache.page || oob) { in nand_do_read_ops()
3377 bufpoi = use_bounce_buf ? chip->data_buf : buf; in nand_do_read_ops()
3386 * the read methods return max bitflips per ecc step. in nand_do_read_ops()
3388 if (unlikely(ops->mode == MTD_OPS_RAW)) in nand_do_read_ops()
3389 ret = chip->ecc.read_page_raw(chip, bufpoi, in nand_do_read_ops()
3394 ret = chip->ecc.read_subpage(chip, col, bytes, in nand_do_read_ops()
3397 ret = chip->ecc.read_page(chip, bufpoi, in nand_do_read_ops()
3402 chip->pagecache.page = -1; in nand_do_read_ops()
3412 !(mtd->ecc_stats.failed - ecc_stats.failed) && in nand_do_read_ops()
3413 (ops->mode != MTD_OPS_RAW)) { in nand_do_read_ops()
3414 chip->pagecache.page = realpage; in nand_do_read_ops()
3415 chip->pagecache.bitflips = ret; in nand_do_read_ops()
3418 chip->pagecache.page = -1; in nand_do_read_ops()
3429 oobreadlen -= toread; in nand_do_read_ops()
3435 if (mtd->ecc_stats.failed - ecc_stats.failed) { in nand_do_read_ops()
3436 if (retry_mode + 1 < chip->read_retries) { in nand_do_read_ops()
3444 mtd->ecc_stats = ecc_stats; in nand_do_read_ops()
3455 memcpy(buf, chip->data_buf + col, bytes); in nand_do_read_ops()
3458 chip->pagecache.bitflips); in nand_do_read_ops()
3461 readlen -= bytes; in nand_do_read_ops()
3479 page = realpage & chip->pagemask; in nand_do_read_ops()
3489 ops->retlen = ops->len - (size_t) readlen; in nand_do_read_ops()
3491 ops->oobretlen = ops->ooblen - oobreadlen; in nand_do_read_ops()
3497 return -EBADMSG; in nand_do_read_ops()
3503 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
3504 * @chip: nand chip info structure
3511 return nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize); in nand_read_oob_std()
3516 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
3518 * @chip: nand chip info structure
3524 int length = mtd->oobsize; in nand_read_oob_syndrome()
3525 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; in nand_read_oob_syndrome()
3526 int eccsize = chip->ecc.size; in nand_read_oob_syndrome()
3527 uint8_t *bufpoi = chip->oob_poi; in nand_read_oob_syndrome()
3530 ret = nand_read_page_op(chip, page, chip->ecc.size, NULL, 0); in nand_read_oob_syndrome()
3534 for (i = 0; i < chip->ecc.steps; i++) { in nand_read_oob_syndrome()
3539 if (mtd->writesize > 512) in nand_read_oob_syndrome()
3558 length -= toread; in nand_read_oob_syndrome()
3570 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
3571 * @chip: nand chip info structure
3578 return nand_prog_page_op(chip, page, mtd->writesize, chip->oob_poi, in nand_write_oob_std()
3579 mtd->oobsize); in nand_write_oob_std()
3584 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
3585 * with syndrome - only for large page flash
3586 * @chip: nand chip info structure
3592 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; in nand_write_oob_syndrome()
3593 int eccsize = chip->ecc.size, length = mtd->oobsize; in nand_write_oob_syndrome()
3594 int ret, i, len, pos, sndcmd = 0, steps = chip->ecc.steps; in nand_write_oob_syndrome()
3595 const uint8_t *bufpoi = chip->oob_poi; in nand_write_oob_syndrome()
3598 * data-ecc-data-ecc ... ecc-oob in nand_write_oob_syndrome()
3600 * data-pad-ecc-pad-data-pad .... ecc-pad-oob in nand_write_oob_syndrome()
3602 if (!chip->ecc.prepad && !chip->ecc.postpad) { in nand_write_oob_syndrome()
3614 if (mtd->writesize <= 512) { in nand_write_oob_syndrome()
3626 len -= num; in nand_write_oob_syndrome()
3645 length -= len; in nand_write_oob_syndrome()
3657 * nand_do_read_oob - [INTERN] NAND read out-of-band
3658 * @chip: NAND chip object
3662 * NAND read out-of-band data from the spare area.
3671 int readlen = ops->ooblen; in nand_do_read_oob()
3673 uint8_t *buf = ops->oobbuf; in nand_do_read_oob()
3681 return -EIO; in nand_do_read_oob()
3683 stats = mtd->ecc_stats; in nand_do_read_oob()
3687 chipnr = (int)(from >> chip->chip_shift); in nand_do_read_oob()
3691 realpage = (int)(from >> chip->page_shift); in nand_do_read_oob()
3692 page = realpage & chip->pagemask; in nand_do_read_oob()
3695 if (ops->mode == MTD_OPS_RAW) in nand_do_read_oob()
3696 ret = chip->ecc.read_oob_raw(chip, page); in nand_do_read_oob()
3698 ret = chip->ecc.read_oob(chip, page); in nand_do_read_oob()
3710 readlen -= len; in nand_do_read_oob()
3717 page = realpage & chip->pagemask; in nand_do_read_oob()
3727 ops->oobretlen = ops->ooblen - readlen; in nand_do_read_oob()
3732 if (mtd->ecc_stats.failed - stats.failed) in nand_do_read_oob()
3733 return -EBADMSG; in nand_do_read_oob()
3739 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
3744 * NAND read data and/or out-of-band data.
3752 ops->retlen = 0; in nand_read_oob()
3754 if (ops->mode != MTD_OPS_PLACE_OOB && in nand_read_oob()
3755 ops->mode != MTD_OPS_AUTO_OOB && in nand_read_oob()
3756 ops->mode != MTD_OPS_RAW) in nand_read_oob()
3757 return -ENOTSUPP; in nand_read_oob()
3763 if (!ops->datbuf) in nand_read_oob()
3773 * nand_write_page_raw_notsupp - dummy raw page write function
3774 * @chip: nand chip info structure
3776 * @oob_required: must write chip->oob_poi to OOB
3779 * Returns -ENOTSUPP unconditionally.
3784 return -ENOTSUPP; in nand_write_page_raw_notsupp()
3788 * nand_write_page_raw - [INTERN] raw page write function
3789 * @chip: nand chip info structure
3791 * @oob_required: must write chip->oob_poi to OOB
3794 * Not for syndrome calculating ECC controllers, which use a special oob layout.
3802 ret = nand_prog_page_begin_op(chip, page, 0, buf, mtd->writesize); in nand_write_page_raw()
3807 ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, in nand_write_page_raw()
3818 * nand_monolithic_write_page_raw - Monolithic page write in raw mode
3819 * @chip: NAND chip info structure
3821 * @oob_required: must write chip->oob_poi to OOB
3827 * into the NAND chip arrays in a single operation. This is an
3830 * cycles on the NAND bus, and finally sends the program command to
3831 * synchronyze the NAND chip cache.
3837 unsigned int size = mtd->writesize; in nand_monolithic_write_page_raw()
3841 size += mtd->oobsize; in nand_monolithic_write_page_raw()
3843 if (buf != chip->data_buf) { in nand_monolithic_write_page_raw()
3845 memcpy(write_buf, buf, mtd->writesize); in nand_monolithic_write_page_raw()
3854 * nand_write_page_raw_syndrome - [INTERN] raw page write function
3855 * @chip: nand chip info structure
3857 * @oob_required: must write chip->oob_poi to OOB
3860 * We need a special oob layout and handling even when ECC isn't checked.
3867 int eccsize = chip->ecc.size; in nand_write_page_raw_syndrome()
3868 int eccbytes = chip->ecc.bytes; in nand_write_page_raw_syndrome()
3869 uint8_t *oob = chip->oob_poi; in nand_write_page_raw_syndrome()
3876 for (steps = chip->ecc.steps; steps > 0; steps--) { in nand_write_page_raw_syndrome()
3883 if (chip->ecc.prepad) { in nand_write_page_raw_syndrome()
3884 ret = nand_write_data_op(chip, oob, chip->ecc.prepad, in nand_write_page_raw_syndrome()
3889 oob += chip->ecc.prepad; in nand_write_page_raw_syndrome()
3898 if (chip->ecc.postpad) { in nand_write_page_raw_syndrome()
3899 ret = nand_write_data_op(chip, oob, chip->ecc.postpad, in nand_write_page_raw_syndrome()
3904 oob += chip->ecc.postpad; in nand_write_page_raw_syndrome()
3908 size = mtd->oobsize - (oob - chip->oob_poi); in nand_write_page_raw_syndrome()
3918 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
3919 * @chip: nand chip info structure
3921 * @oob_required: must write chip->oob_poi to OOB
3928 int i, eccsize = chip->ecc.size, ret; in nand_write_page_swecc()
3929 int eccbytes = chip->ecc.bytes; in nand_write_page_swecc()
3930 int eccsteps = chip->ecc.steps; in nand_write_page_swecc()
3931 uint8_t *ecc_calc = chip->ecc.calc_buf; in nand_write_page_swecc()
3934 /* Software ECC calculation */ in nand_write_page_swecc()
3935 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) in nand_write_page_swecc()
3936 chip->ecc.calculate(chip, p, &ecc_calc[i]); in nand_write_page_swecc()
3938 ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0, in nand_write_page_swecc()
3939 chip->ecc.total); in nand_write_page_swecc()
3943 return chip->ecc.write_page_raw(chip, buf, 1, page); in nand_write_page_swecc()
3947 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
3948 * @chip: nand chip info structure
3950 * @oob_required: must write chip->oob_poi to OOB
3957 int i, eccsize = chip->ecc.size, ret; in nand_write_page_hwecc()
3958 int eccbytes = chip->ecc.bytes; in nand_write_page_hwecc()
3959 int eccsteps = chip->ecc.steps; in nand_write_page_hwecc()
3960 uint8_t *ecc_calc = chip->ecc.calc_buf; in nand_write_page_hwecc()
3967 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { in nand_write_page_hwecc()
3968 chip->ecc.hwctl(chip, NAND_ECC_WRITE); in nand_write_page_hwecc()
3974 chip->ecc.calculate(chip, p, &ecc_calc[i]); in nand_write_page_hwecc()
3977 ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0, in nand_write_page_hwecc()
3978 chip->ecc.total); in nand_write_page_hwecc()
3982 ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false); in nand_write_page_hwecc()
3991 * nand_write_subpage_hwecc - [REPLACEABLE] hardware ECC based subpage write
3992 * @chip: nand chip info structure
3996 * @oob_required: must write chip->oob_poi to OOB
4004 uint8_t *oob_buf = chip->oob_poi; in nand_write_subpage_hwecc()
4005 uint8_t *ecc_calc = chip->ecc.calc_buf; in nand_write_subpage_hwecc()
4006 int ecc_size = chip->ecc.size; in nand_write_subpage_hwecc()
4007 int ecc_bytes = chip->ecc.bytes; in nand_write_subpage_hwecc()
4008 int ecc_steps = chip->ecc.steps; in nand_write_subpage_hwecc()
4010 uint32_t end_step = (offset + data_len - 1) / ecc_size; in nand_write_subpage_hwecc()
4011 int oob_bytes = mtd->oobsize / ecc_steps; in nand_write_subpage_hwecc()
4020 chip->ecc.hwctl(chip, NAND_ECC_WRITE); in nand_write_subpage_hwecc()
4027 /* mask ECC of un-touched subpages by padding 0xFF */ in nand_write_subpage_hwecc()
4031 chip->ecc.calculate(chip, buf, ecc_calc); in nand_write_subpage_hwecc()
4033 /* mask OOB of un-touched subpages by padding 0xFF */ in nand_write_subpage_hwecc()
4043 /* copy calculated ECC for whole page to chip->buffer->oob */ in nand_write_subpage_hwecc()
4044 /* this include masked-value(0xFF) for unwritten subpages */ in nand_write_subpage_hwecc()
4045 ecc_calc = chip->ecc.calc_buf; in nand_write_subpage_hwecc()
4046 ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0, in nand_write_subpage_hwecc()
4047 chip->ecc.total); in nand_write_subpage_hwecc()
4051 /* write OOB buffer to NAND device */ in nand_write_subpage_hwecc()
4052 ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false); in nand_write_subpage_hwecc()
4061 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
4062 * @chip: nand chip info structure
4064 * @oob_required: must write chip->oob_poi to OOB
4074 int i, eccsize = chip->ecc.size; in nand_write_page_syndrome()
4075 int eccbytes = chip->ecc.bytes; in nand_write_page_syndrome()
4076 int eccsteps = chip->ecc.steps; in nand_write_page_syndrome()
4078 uint8_t *oob = chip->oob_poi; in nand_write_page_syndrome()
4085 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { in nand_write_page_syndrome()
4086 chip->ecc.hwctl(chip, NAND_ECC_WRITE); in nand_write_page_syndrome()
4092 if (chip->ecc.prepad) { in nand_write_page_syndrome()
4093 ret = nand_write_data_op(chip, oob, chip->ecc.prepad, in nand_write_page_syndrome()
4098 oob += chip->ecc.prepad; in nand_write_page_syndrome()
4101 chip->ecc.calculate(chip, p, oob); in nand_write_page_syndrome()
4109 if (chip->ecc.postpad) { in nand_write_page_syndrome()
4110 ret = nand_write_data_op(chip, oob, chip->ecc.postpad, in nand_write_page_syndrome()
4115 oob += chip->ecc.postpad; in nand_write_page_syndrome()
4120 i = mtd->oobsize - (oob - chip->oob_poi); in nand_write_page_syndrome()
4131 * nand_write_page - write one page
4132 * @chip: NAND chip descriptor
4136 * @oob_required: must write chip->oob_poi to OOB
4147 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && in nand_write_page()
4148 chip->ecc.write_subpage) in nand_write_page()
4149 subpage = offset || (data_len < mtd->writesize); in nand_write_page()
4154 status = chip->ecc.write_page_raw(chip, buf, oob_required, in nand_write_page()
4157 status = chip->ecc.write_subpage(chip, offset, data_len, buf, in nand_write_page()
4160 status = chip->ecc.write_page(chip, buf, oob_required, page); in nand_write_page()
4168 #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
4171 * nand_do_write_ops - [INTERN] NAND write with ECC
4172 * @chip: NAND chip object
4176 * NAND write with ECC.
4183 uint32_t writelen = ops->len; in nand_do_write_ops()
4185 uint32_t oobwritelen = ops->ooblen; in nand_do_write_ops()
4188 uint8_t *oob = ops->oobbuf; in nand_do_write_ops()
4189 uint8_t *buf = ops->datbuf; in nand_do_write_ops()
4193 ops->retlen = 0; in nand_do_write_ops()
4198 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) { in nand_do_write_ops()
4201 return -EINVAL; in nand_do_write_ops()
4206 return -EIO; in nand_do_write_ops()
4208 column = to & (mtd->writesize - 1); in nand_do_write_ops()
4210 chipnr = (int)(to >> chip->chip_shift); in nand_do_write_ops()
4215 ret = -EIO; in nand_do_write_ops()
4219 realpage = (int)(to >> chip->page_shift); in nand_do_write_ops()
4220 page = realpage & chip->pagemask; in nand_do_write_ops()
4223 if (to <= ((loff_t)chip->pagecache.page << chip->page_shift) && in nand_do_write_ops()
4224 ((loff_t)chip->pagecache.page << chip->page_shift) < (to + ops->len)) in nand_do_write_ops()
4225 chip->pagecache.page = -1; in nand_do_write_ops()
4228 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) { in nand_do_write_ops()
4229 ret = -EINVAL; in nand_do_write_ops()
4234 int bytes = mtd->writesize; in nand_do_write_ops()
4237 int part_pagewr = (column || writelen < mtd->writesize); in nand_do_write_ops()
4241 else if (chip->options & NAND_USES_DMA) in nand_do_write_ops()
4244 chip->buf_align); in nand_do_write_ops()
4256 bytes = min_t(int, bytes - column, writelen); in nand_do_write_ops()
4258 memset(wbuf, 0xff, mtd->writesize); in nand_do_write_ops()
4265 oobwritelen -= len; in nand_do_write_ops()
4268 memset(chip->oob_poi, 0xff, mtd->oobsize); in nand_do_write_ops()
4273 (ops->mode == MTD_OPS_RAW)); in nand_do_write_ops()
4277 writelen -= bytes; in nand_do_write_ops()
4285 page = realpage & chip->pagemask; in nand_do_write_ops()
4294 ops->retlen = ops->len - writelen; in nand_do_write_ops()
4296 ops->oobretlen = ops->ooblen; in nand_do_write_ops()
4304 * panic_nand_write - [MTD Interface] NAND write with ECC
4311 * NAND write with ECC. Used when performing writes in interrupt context, this
4318 int chipnr = (int)(to >> chip->chip_shift); in panic_nand_write()
4339 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
4350 ops->retlen = 0; in nand_write_oob()
4356 switch (ops->mode) { in nand_write_oob()
4366 if (!ops->datbuf) in nand_write_oob()
4377 * nand_erase - [MTD Interface] erase block(s)
4389 * nand_erase_nand - [INTERN] erase block(s)
4390 * @chip: NAND chip object
4403 __func__, (unsigned long long)instr->addr, in nand_erase_nand()
4404 (unsigned long long)instr->len); in nand_erase_nand()
4406 if (check_offs_len(chip, instr->addr, instr->len)) in nand_erase_nand()
4407 return -EINVAL; in nand_erase_nand()
4410 if (nand_region_is_secured(chip, instr->addr, instr->len)) in nand_erase_nand()
4411 return -EIO; in nand_erase_nand()
4419 page = (int)(instr->addr >> chip->page_shift); in nand_erase_nand()
4420 chipnr = (int)(instr->addr >> chip->chip_shift); in nand_erase_nand()
4423 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift); in nand_erase_nand()
4425 /* Select the NAND device */ in nand_erase_nand()
4432 ret = -EIO; in nand_erase_nand()
4437 len = instr->len; in nand_erase_nand()
4442 chip->page_shift, allowbbt)) { in nand_erase_nand()
4445 ret = -EIO; in nand_erase_nand()
4453 if (page <= chip->pagecache.page && chip->pagecache.page < in nand_erase_nand()
4455 chip->pagecache.page = -1; in nand_erase_nand()
4457 ret = nand_erase_op(chip, (page & chip->pagemask) >> in nand_erase_nand()
4458 (chip->phys_erase_shift - chip->page_shift)); in nand_erase_nand()
4462 instr->fail_addr = in nand_erase_nand()
4463 ((loff_t)page << chip->page_shift); in nand_erase_nand()
4468 len -= (1ULL << chip->phys_erase_shift); in nand_erase_nand()
4472 if (len && !(page & chip->pagemask)) { in nand_erase_nand()
4491 * nand_sync - [MTD Interface] sync
4509 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
4516 int chipnr = (int)(offs >> chip->chip_shift); in nand_block_isbad()
4519 /* Select the NAND device */ in nand_block_isbad()
4535 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
4555 * nand_suspend - [MTD Interface] Suspend the NAND flash
4565 mutex_lock(&chip->lock); in nand_suspend()
4566 if (chip->ops.suspend) in nand_suspend()
4567 ret = chip->ops.suspend(chip); in nand_suspend()
4569 chip->suspended = 1; in nand_suspend()
4570 mutex_unlock(&chip->lock); in nand_suspend()
4576 * nand_resume - [MTD Interface] Resume the NAND flash
4583 mutex_lock(&chip->lock); in nand_resume()
4584 if (chip->suspended) { in nand_resume()
4585 if (chip->ops.resume) in nand_resume()
4586 chip->ops.resume(chip); in nand_resume()
4587 chip->suspended = 0; in nand_resume()
4592 mutex_unlock(&chip->lock); in nand_resume()
4596 * nand_shutdown - [MTD Interface] Finish the current NAND operation and
4606 * nand_lock - [MTD Interface] Lock the NAND flash
4615 if (!chip->ops.lock_area) in nand_lock()
4616 return -ENOTSUPP; in nand_lock()
4618 return chip->ops.lock_area(chip, ofs, len); in nand_lock()
4622 * nand_unlock - [MTD Interface] Unlock the NAND flash
4631 if (!chip->ops.unlock_area) in nand_unlock()
4632 return -ENOTSUPP; in nand_unlock()
4634 return chip->ops.unlock_area(chip, ofs, len); in nand_unlock()
4641 if (!chip->controller) { in nand_set_defaults()
4642 chip->controller = &chip->legacy.dummy_controller; in nand_set_defaults()
4643 nand_controller_init(chip->controller); in nand_set_defaults()
4648 if (!chip->buf_align) in nand_set_defaults()
4649 chip->buf_align = 1; in nand_set_defaults()
4658 s[len - 1] = 0; in sanitize_string()
4661 for (i = 0; i < len - 1; i++) { in sanitize_string()
4671 * nand_id_has_period - Check if an ID string has a given wraparound period
4678 * period of 3). This is a helper function for nand_id_len(). Returns non-zero
4692 * nand_id_len - Get the length of an ID string returned by CMD_READID
4703 /* Find last non-zero byte */ in nand_id_len()
4704 for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--) in nand_id_len()
4722 if (last_nonzero < arrlen - 1) in nand_id_len()
4740 * Many new NAND share similar device ID codes, which represent the size of the
4742 * manufacturer-specific "extended ID" decoding patterns.
4749 u8 *id_data = chip->id.data; in nand_decode_ext_id()
4751 memorg = nanddev_get_memorg(&chip->base); in nand_decode_ext_id()
4754 memorg->bits_per_cell = nand_get_bits_per_cell(id_data[2]); in nand_decode_ext_id()
4759 memorg->pagesize = 1024 << (extid & 0x03); in nand_decode_ext_id()
4760 mtd->writesize = memorg->pagesize; in nand_decode_ext_id()
4763 memorg->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9); in nand_decode_ext_id()
4764 mtd->oobsize = memorg->oobsize; in nand_decode_ext_id()
4767 memorg->pages_per_eraseblock = ((64 * 1024) << (extid & 0x03)) / in nand_decode_ext_id()
4768 memorg->pagesize; in nand_decode_ext_id()
4769 mtd->erasesize = (64 * 1024) << (extid & 0x03); in nand_decode_ext_id()
4773 chip->options |= NAND_BUSWIDTH_16; in nand_decode_ext_id()
4787 memorg = nanddev_get_memorg(&chip->base); in nand_decode_id()
4789 memorg->pages_per_eraseblock = type->erasesize / type->pagesize; in nand_decode_id()
4790 mtd->erasesize = type->erasesize; in nand_decode_id()
4791 memorg->pagesize = type->pagesize; in nand_decode_id()
4792 mtd->writesize = memorg->pagesize; in nand_decode_id()
4793 memorg->oobsize = memorg->pagesize / 32; in nand_decode_id()
4794 mtd->oobsize = memorg->oobsize; in nand_decode_id()
4796 /* All legacy ID NAND are small-page, SLC */ in nand_decode_id()
4797 memorg->bits_per_cell = 1; in nand_decode_id()
4803 * page size, cell-type information).
4810 if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16)) in nand_decode_bbm_options()
4811 chip->badblockpos = NAND_BBM_POS_LARGE; in nand_decode_bbm_options()
4813 chip->badblockpos = NAND_BBM_POS_SMALL; in nand_decode_bbm_options()
4818 return type->id_len; in is_full_id_nand()
4824 struct nand_device *base = &chip->base; in find_full_id_nand()
4828 u8 *id_data = chip->id.data; in find_full_id_nand()
4830 memorg = nanddev_get_memorg(&chip->base); in find_full_id_nand()
4832 if (!strncmp(type->id, id_data, type->id_len)) { in find_full_id_nand()
4833 memorg->pagesize = type->pagesize; in find_full_id_nand()
4834 mtd->writesize = memorg->pagesize; in find_full_id_nand()
4835 memorg->pages_per_eraseblock = type->erasesize / in find_full_id_nand()
4836 type->pagesize; in find_full_id_nand()
4837 mtd->erasesize = type->erasesize; in find_full_id_nand()
4838 memorg->oobsize = type->oobsize; in find_full_id_nand()
4839 mtd->oobsize = memorg->oobsize; in find_full_id_nand()
4841 memorg->bits_per_cell = nand_get_bits_per_cell(id_data[2]); in find_full_id_nand()
4842 memorg->eraseblocks_per_lun = in find_full_id_nand()
4843 DIV_ROUND_DOWN_ULL((u64)type->chipsize << 20, in find_full_id_nand()
4844 memorg->pagesize * in find_full_id_nand()
4845 memorg->pages_per_eraseblock); in find_full_id_nand()
4846 chip->options |= type->options; in find_full_id_nand()
4851 chip->parameters.model = kstrdup(type->name, GFP_KERNEL); in find_full_id_nand()
4852 if (!chip->parameters.model) in find_full_id_nand()
4861 * Manufacturer detection. Only used when the NAND is not ONFI or JEDEC
4862 * compliant and does not have a full-id or legacy-id entry in the nand_ids
4871 if (chip->manufacturer.desc && chip->manufacturer.desc->ops && in nand_manufacturer_detect()
4872 chip->manufacturer.desc->ops->detect) { in nand_manufacturer_detect()
4875 memorg = nanddev_get_memorg(&chip->base); in nand_manufacturer_detect()
4878 memorg->bits_per_cell = nand_get_bits_per_cell(chip->id.data[2]); in nand_manufacturer_detect()
4879 chip->manufacturer.desc->ops->detect(chip); in nand_manufacturer_detect()
4889 * their ->init() hook.
4893 if (!chip->manufacturer.desc || !chip->manufacturer.desc->ops || in nand_manufacturer_init()
4894 !chip->manufacturer.desc->ops->init) in nand_manufacturer_init()
4897 return chip->manufacturer.desc->ops->init(chip); in nand_manufacturer_init()
4904 * ->cleanup() hook.
4909 if (chip->manufacturer.desc && chip->manufacturer.desc->ops && in nand_manufacturer_cleanup()
4910 chip->manufacturer.desc->ops->cleanup) in nand_manufacturer_cleanup()
4911 chip->manufacturer.desc->ops->cleanup(chip); in nand_manufacturer_cleanup()
4917 return manufacturer_desc ? manufacturer_desc->name : "Unknown"; in nand_manufacturer_name()
4929 u8 *id_data = chip->id.data; in nand_detect()
4935 * unassigned by the ID-based detection logic. in nand_detect()
4937 memorg = nanddev_get_memorg(&chip->base); in nand_detect()
4938 memorg->planes_per_lun = 1; in nand_detect()
4939 memorg->luns_per_target = 1; in nand_detect()
4943 * after power-up. in nand_detect()
4962 * Try again to make sure, as some systems the bus-hold or other in nand_detect()
4964 * possibly credible NAND flash to appear. If the two results do in nand_detect()
4969 ret = nand_readid_op(chip, 0, id_data, sizeof(chip->id.data)); in nand_detect()
4976 return -ENODEV; in nand_detect()
4979 chip->id.len = nand_id_len(id_data, ARRAY_SIZE(chip->id.data)); in nand_detect()
4983 chip->manufacturer.desc = manufacturer_desc; in nand_detect()
4989 * Save the NAND_BUSWIDTH_16 flag before letting auto-detection logic in nand_detect()
4991 * This is required to make sure initial NAND bus width set by the in nand_detect()
4992 * NAND controller driver is coherent with the real NAND bus width in nand_detect()
4993 * (extracted by auto-detection code). in nand_detect()
4995 busw = chip->options & NAND_BUSWIDTH_16; in nand_detect()
4999 * before starting auto-detection. in nand_detect()
5001 chip->options &= ~NAND_BUSWIDTH_16; in nand_detect()
5003 for (; type->name != NULL; type++) { in nand_detect()
5007 } else if (dev_id == type->dev_id) { in nand_detect()
5012 if (!type->name || !type->pagesize) { in nand_detect()
5028 if (!type->name) in nand_detect()
5029 return -ENODEV; in nand_detect()
5031 chip->parameters.model = kstrdup(type->name, GFP_KERNEL); in nand_detect()
5032 if (!chip->parameters.model) in nand_detect()
5033 return -ENOMEM; in nand_detect()
5035 if (!type->pagesize) in nand_detect()
5041 chip->options |= type->options; in nand_detect()
5043 memorg->eraseblocks_per_lun = in nand_detect()
5044 DIV_ROUND_DOWN_ULL((u64)type->chipsize << 20, in nand_detect()
5045 memorg->pagesize * in nand_detect()
5046 memorg->pages_per_eraseblock); in nand_detect()
5049 if (!mtd->name) in nand_detect()
5050 mtd->name = chip->parameters.model; in nand_detect()
5052 if (chip->options & NAND_BUSWIDTH_AUTO) { in nand_detect()
5055 } else if (busw != (chip->options & NAND_BUSWIDTH_16)) { in nand_detect()
5063 mtd->name); in nand_detect()
5065 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8); in nand_detect()
5066 ret = -EINVAL; in nand_detect()
5074 chip->page_shift = ffs(mtd->writesize) - 1; in nand_detect()
5075 /* Convert chipsize to number of pages per chip -1 */ in nand_detect()
5076 targetsize = nanddev_target_size(&chip->base); in nand_detect()
5077 chip->pagemask = (targetsize >> chip->page_shift) - 1; in nand_detect()
5079 chip->bbt_erase_shift = chip->phys_erase_shift = in nand_detect()
5080 ffs(mtd->erasesize) - 1; in nand_detect()
5082 chip->chip_shift = ffs((unsigned)targetsize) - 1; in nand_detect()
5084 chip->chip_shift = ffs((unsigned)(targetsize >> 32)); in nand_detect()
5085 chip->chip_shift += 32 - 1; in nand_detect()
5088 if (chip->chip_shift - chip->page_shift > 16) in nand_detect()
5089 chip->options |= NAND_ROW_ADDR_3; in nand_detect()
5091 chip->badblockbits = 8; in nand_detect()
5098 chip->parameters.model); in nand_detect()
5101 mtd->erasesize >> 10, mtd->writesize, mtd->oobsize); in nand_detect()
5105 kfree(chip->parameters.model); in nand_detect()
5128 [NAND_ECC_ON_DIE] = "on-die", in of_get_rawnand_ecc_engine_type_legacy()
5134 err = of_property_read_string(np, "nand-ecc-mode", &pm); in of_get_rawnand_ecc_engine_type_legacy()
5167 err = of_property_read_string(np, "nand-ecc-mode", &pm); in of_get_rawnand_ecc_placement_legacy()
5181 err = of_property_read_string(np, "nand-ecc-mode", &pm); in of_get_rawnand_ecc_algo_legacy()
5195 struct nand_ecc_props *user_conf = &chip->base.ecc.user_conf; in of_get_nand_ecc_legacy_user_config()
5197 if (user_conf->engine_type == NAND_ECC_ENGINE_TYPE_INVALID) in of_get_nand_ecc_legacy_user_config()
5198 user_conf->engine_type = of_get_rawnand_ecc_engine_type_legacy(dn); in of_get_nand_ecc_legacy_user_config()
5200 if (user_conf->algo == NAND_ECC_ALGO_UNKNOWN) in of_get_nand_ecc_legacy_user_config()
5201 user_conf->algo = of_get_rawnand_ecc_algo_legacy(dn); in of_get_nand_ecc_legacy_user_config()
5203 if (user_conf->placement == NAND_ECC_PLACEMENT_UNKNOWN) in of_get_nand_ecc_legacy_user_config()
5204 user_conf->placement = of_get_rawnand_ecc_placement_legacy(dn); in of_get_nand_ecc_legacy_user_config()
5211 if (of_property_read_u32(np, "nand-bus-width", &val)) in of_get_nand_bus_width()
5219 return -EIO; in of_get_nand_bus_width()
5225 return of_property_read_bool(np, "nand-on-flash-bbt"); in of_get_nand_on_flash_bbt()
5234 /* Only proceed if the "secure-regions" property is present in DT */ in of_get_nand_secure_regions()
5235 prop = of_find_property(dn, "secure-regions", NULL); in of_get_nand_secure_regions()
5239 nr_elem = of_property_count_elems_of_size(dn, "secure-regions", sizeof(u64)); in of_get_nand_secure_regions()
5243 chip->nr_secure_regions = nr_elem / 2; in of_get_nand_secure_regions()
5244 chip->secure_regions = kcalloc(chip->nr_secure_regions, sizeof(*chip->secure_regions), in of_get_nand_secure_regions()
5246 if (!chip->secure_regions) in of_get_nand_secure_regions()
5247 return -ENOMEM; in of_get_nand_secure_regions()
5249 for (i = 0, j = 0; i < chip->nr_secure_regions; i++, j += 2) { in of_get_nand_secure_regions()
5250 of_property_read_u64_index(dn, "secure-regions", j, in of_get_nand_secure_regions()
5251 &chip->secure_regions[i].offset); in of_get_nand_secure_regions()
5252 of_property_read_u64_index(dn, "secure-regions", j + 1, in of_get_nand_secure_regions()
5253 &chip->secure_regions[i].size); in of_get_nand_secure_regions()
5260 * rawnand_dt_parse_gpio_cs - Parse the gpio-cs property of a controller
5269 struct device_node *np = dev->of_node; in rawnand_dt_parse_gpio_cs()
5273 ndescs = of_gpio_named_count(np, "cs-gpios"); in rawnand_dt_parse_gpio_cs()
5275 dev_dbg(dev, "No valid cs-gpios property\n"); in rawnand_dt_parse_gpio_cs()
5281 return -ENOMEM; in rawnand_dt_parse_gpio_cs()
5299 struct nand_device *nand = mtd_to_nanddev(nand_to_mtd(chip)); in rawnand_dt_init() local
5306 chip->options |= NAND_BUSWIDTH_16; in rawnand_dt_init()
5308 if (of_property_read_bool(dn, "nand-is-boot-medium")) in rawnand_dt_init()
5309 chip->options |= NAND_IS_BOOT_MEDIUM; in rawnand_dt_init()
5312 chip->bbt_options |= NAND_BBT_USE_FLASH; in rawnand_dt_init()
5314 of_get_nand_ecc_user_config(nand); in rawnand_dt_init()
5318 * If neither the user nor the NAND controller have requested a specific in rawnand_dt_init()
5319 * ECC engine type, we will default to NAND_ECC_ENGINE_TYPE_ON_HOST. in rawnand_dt_init()
5321 nand->ecc.defaults.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; in rawnand_dt_init()
5324 * Use the user requested engine type, unless there is none, in this in rawnand_dt_init()
5325 * case default to the NAND controller choice, otherwise fallback to in rawnand_dt_init()
5326 * the raw NAND default one. in rawnand_dt_init()
5328 if (nand->ecc.user_conf.engine_type != NAND_ECC_ENGINE_TYPE_INVALID) in rawnand_dt_init()
5329 chip->ecc.engine_type = nand->ecc.user_conf.engine_type; in rawnand_dt_init()
5330 if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_INVALID) in rawnand_dt_init()
5331 chip->ecc.engine_type = nand->ecc.defaults.engine_type; in rawnand_dt_init()
5333 chip->ecc.placement = nand->ecc.user_conf.placement; in rawnand_dt_init()
5334 chip->ecc.algo = nand->ecc.user_conf.algo; in rawnand_dt_init()
5335 chip->ecc.strength = nand->ecc.user_conf.strength; in rawnand_dt_init()
5336 chip->ecc.size = nand->ecc.user_conf.step_size; in rawnand_dt_init()
5342 * nand_scan_ident - Scan for the NAND device
5343 * @chip: NAND chip object
5345 * @table: alternative NAND ID table
5351 * to tweak some ECC-related parameters before nand_scan_tail(). This separation
5353 * as been banned for the benefit of the ->init_ecc()/cleanup_ecc() hooks.
5364 memorg = nanddev_get_memorg(&chip->base); in nand_scan_ident()
5367 chip->cur_cs = -1; in nand_scan_ident()
5369 mutex_init(&chip->lock); in nand_scan_ident()
5372 chip->current_interface_config = nand_get_reset_interface_config(); in nand_scan_ident()
5378 if (!mtd->name && mtd->dev.parent) in nand_scan_ident()
5379 mtd->name = dev_name(mtd->dev.parent); in nand_scan_ident()
5388 memorg->ntargets = maxchips; in nand_scan_ident()
5393 if (!(chip->options & NAND_SCAN_SILENT_NODEV)) in nand_scan_ident()
5394 pr_warn("No NAND device found\n"); in nand_scan_ident()
5399 nand_maf_id = chip->id.data[0]; in nand_scan_ident()
5400 nand_dev_id = chip->id.data[1]; in nand_scan_ident()
5429 memorg->ntargets = i; in nand_scan_ident()
5430 mtd->size = i * nanddev_target_size(&chip->base); in nand_scan_ident()
5437 kfree(chip->parameters.model); in nand_scan_ident_cleanup()
5438 kfree(chip->parameters.onfi); in nand_scan_ident_cleanup()
5444 struct nand_device *base = &chip->base; in rawnand_sw_hamming_init()
5447 base->ecc.user_conf.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; in rawnand_sw_hamming_init()
5448 base->ecc.user_conf.algo = NAND_ECC_ALGO_HAMMING; in rawnand_sw_hamming_init()
5449 base->ecc.user_conf.strength = chip->ecc.strength; in rawnand_sw_hamming_init()
5450 base->ecc.user_conf.step_size = chip->ecc.size; in rawnand_sw_hamming_init()
5456 engine_conf = base->ecc.ctx.priv; in rawnand_sw_hamming_init()
5458 if (chip->ecc.options & NAND_ECC_SOFT_HAMMING_SM_ORDER) in rawnand_sw_hamming_init()
5459 engine_conf->sm_order = true; in rawnand_sw_hamming_init()
5461 chip->ecc.size = base->ecc.ctx.conf.step_size; in rawnand_sw_hamming_init()
5462 chip->ecc.strength = base->ecc.ctx.conf.strength; in rawnand_sw_hamming_init()
5463 chip->ecc.total = base->ecc.ctx.total; in rawnand_sw_hamming_init()
5464 chip->ecc.steps = nanddev_get_ecc_nsteps(base); in rawnand_sw_hamming_init()
5465 chip->ecc.bytes = base->ecc.ctx.total / nanddev_get_ecc_nsteps(base); in rawnand_sw_hamming_init()
5475 struct nand_device *base = &chip->base; in rawnand_sw_hamming_calculate()
5486 struct nand_device *base = &chip->base; in rawnand_sw_hamming_correct()
5494 struct nand_device *base = &chip->base; in rawnand_sw_hamming_cleanup()
5502 struct nand_device *base = &chip->base; in rawnand_sw_bch_init()
5506 base->ecc.user_conf.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; in rawnand_sw_bch_init()
5507 base->ecc.user_conf.algo = NAND_ECC_ALGO_BCH; in rawnand_sw_bch_init()
5508 base->ecc.user_conf.step_size = chip->ecc.size; in rawnand_sw_bch_init()
5509 base->ecc.user_conf.strength = chip->ecc.strength; in rawnand_sw_bch_init()
5515 chip->ecc.size = ecc_conf->step_size; in rawnand_sw_bch_init()
5516 chip->ecc.strength = ecc_conf->strength; in rawnand_sw_bch_init()
5517 chip->ecc.total = base->ecc.ctx.total; in rawnand_sw_bch_init()
5518 chip->ecc.steps = nanddev_get_ecc_nsteps(base); in rawnand_sw_bch_init()
5519 chip->ecc.bytes = base->ecc.ctx.total / nanddev_get_ecc_nsteps(base); in rawnand_sw_bch_init()
5529 struct nand_device *base = &chip->base; in rawnand_sw_bch_calculate()
5537 struct nand_device *base = &chip->base; in rawnand_sw_bch_correct()
5545 struct nand_device *base = &chip->base; in rawnand_sw_bch_cleanup()
5553 struct nand_ecc_ctrl *ecc = &chip->ecc; in nand_set_ecc_on_host_ops() local
5555 switch (ecc->placement) { in nand_set_ecc_on_host_ops()
5559 if (!ecc->read_page) in nand_set_ecc_on_host_ops()
5560 ecc->read_page = nand_read_page_hwecc; in nand_set_ecc_on_host_ops()
5561 if (!ecc->write_page) in nand_set_ecc_on_host_ops()
5562 ecc->write_page = nand_write_page_hwecc; in nand_set_ecc_on_host_ops()
5563 if (!ecc->read_page_raw) in nand_set_ecc_on_host_ops()
5564 ecc->read_page_raw = nand_read_page_raw; in nand_set_ecc_on_host_ops()
5565 if (!ecc->write_page_raw) in nand_set_ecc_on_host_ops()
5566 ecc->write_page_raw = nand_write_page_raw; in nand_set_ecc_on_host_ops()
5567 if (!ecc->read_oob) in nand_set_ecc_on_host_ops()
5568 ecc->read_oob = nand_read_oob_std; in nand_set_ecc_on_host_ops()
5569 if (!ecc->write_oob) in nand_set_ecc_on_host_ops()
5570 ecc->write_oob = nand_write_oob_std; in nand_set_ecc_on_host_ops()
5571 if (!ecc->read_subpage) in nand_set_ecc_on_host_ops()
5572 ecc->read_subpage = nand_read_subpage; in nand_set_ecc_on_host_ops()
5573 if (!ecc->write_subpage && ecc->hwctl && ecc->calculate) in nand_set_ecc_on_host_ops()
5574 ecc->write_subpage = nand_write_subpage_hwecc; in nand_set_ecc_on_host_ops()
5578 if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) && in nand_set_ecc_on_host_ops()
5579 (!ecc->read_page || in nand_set_ecc_on_host_ops()
5580 ecc->read_page == nand_read_page_hwecc || in nand_set_ecc_on_host_ops()
5581 !ecc->write_page || in nand_set_ecc_on_host_ops()
5582 ecc->write_page == nand_write_page_hwecc)) { in nand_set_ecc_on_host_ops()
5583 WARN(1, "No ECC functions supplied; hardware ECC not possible\n"); in nand_set_ecc_on_host_ops()
5584 return -EINVAL; in nand_set_ecc_on_host_ops()
5587 if (!ecc->read_page) in nand_set_ecc_on_host_ops()
5588 ecc->read_page = nand_read_page_syndrome; in nand_set_ecc_on_host_ops()
5589 if (!ecc->write_page) in nand_set_ecc_on_host_ops()
5590 ecc->write_page = nand_write_page_syndrome; in nand_set_ecc_on_host_ops()
5591 if (!ecc->read_page_raw) in nand_set_ecc_on_host_ops()
5592 ecc->read_page_raw = nand_read_page_raw_syndrome; in nand_set_ecc_on_host_ops()
5593 if (!ecc->write_page_raw) in nand_set_ecc_on_host_ops()
5594 ecc->write_page_raw = nand_write_page_raw_syndrome; in nand_set_ecc_on_host_ops()
5595 if (!ecc->read_oob) in nand_set_ecc_on_host_ops()
5596 ecc->read_oob = nand_read_oob_syndrome; in nand_set_ecc_on_host_ops()
5597 if (!ecc->write_oob) in nand_set_ecc_on_host_ops()
5598 ecc->write_oob = nand_write_oob_syndrome; in nand_set_ecc_on_host_ops()
5603 ecc->placement); in nand_set_ecc_on_host_ops()
5604 return -EINVAL; in nand_set_ecc_on_host_ops()
5614 struct nand_ecc_ctrl *ecc = &chip->ecc; in nand_set_ecc_soft_ops() local
5617 if (WARN_ON(ecc->engine_type != NAND_ECC_ENGINE_TYPE_SOFT)) in nand_set_ecc_soft_ops()
5618 return -EINVAL; in nand_set_ecc_soft_ops()
5620 switch (ecc->algo) { in nand_set_ecc_soft_ops()
5622 ecc->calculate = rawnand_sw_hamming_calculate; in nand_set_ecc_soft_ops()
5623 ecc->correct = rawnand_sw_hamming_correct; in nand_set_ecc_soft_ops()
5624 ecc->read_page = nand_read_page_swecc; in nand_set_ecc_soft_ops()
5625 ecc->read_subpage = nand_read_subpage; in nand_set_ecc_soft_ops()
5626 ecc->write_page = nand_write_page_swecc; in nand_set_ecc_soft_ops()
5627 if (!ecc->read_page_raw) in nand_set_ecc_soft_ops()
5628 ecc->read_page_raw = nand_read_page_raw; in nand_set_ecc_soft_ops()
5629 if (!ecc->write_page_raw) in nand_set_ecc_soft_ops()
5630 ecc->write_page_raw = nand_write_page_raw; in nand_set_ecc_soft_ops()
5631 ecc->read_oob = nand_read_oob_std; in nand_set_ecc_soft_ops()
5632 ecc->write_oob = nand_write_oob_std; in nand_set_ecc_soft_ops()
5633 if (!ecc->size) in nand_set_ecc_soft_ops()
5634 ecc->size = 256; in nand_set_ecc_soft_ops()
5635 ecc->bytes = 3; in nand_set_ecc_soft_ops()
5636 ecc->strength = 1; in nand_set_ecc_soft_ops()
5639 ecc->options |= NAND_ECC_SOFT_HAMMING_SM_ORDER; in nand_set_ecc_soft_ops()
5643 WARN(1, "Hamming ECC initialization failed!\n"); in nand_set_ecc_soft_ops()
5651 return -EINVAL; in nand_set_ecc_soft_ops()
5653 ecc->calculate = rawnand_sw_bch_calculate; in nand_set_ecc_soft_ops()
5654 ecc->correct = rawnand_sw_bch_correct; in nand_set_ecc_soft_ops()
5655 ecc->read_page = nand_read_page_swecc; in nand_set_ecc_soft_ops()
5656 ecc->read_subpage = nand_read_subpage; in nand_set_ecc_soft_ops()
5657 ecc->write_page = nand_write_page_swecc; in nand_set_ecc_soft_ops()
5658 if (!ecc->read_page_raw) in nand_set_ecc_soft_ops()
5659 ecc->read_page_raw = nand_read_page_raw; in nand_set_ecc_soft_ops()
5660 if (!ecc->write_page_raw) in nand_set_ecc_soft_ops()
5661 ecc->write_page_raw = nand_write_page_raw; in nand_set_ecc_soft_ops()
5662 ecc->read_oob = nand_read_oob_std; in nand_set_ecc_soft_ops()
5663 ecc->write_oob = nand_write_oob_std; in nand_set_ecc_soft_ops()
5666 * We can only maximize ECC config when the default layout is in nand_set_ecc_soft_ops()
5670 if (nanddev->ecc.user_conf.flags & NAND_ECC_MAXIMIZE_STRENGTH && in nand_set_ecc_soft_ops()
5671 mtd->ooblayout != nand_get_large_page_ooblayout()) in nand_set_ecc_soft_ops()
5672 nanddev->ecc.user_conf.flags &= ~NAND_ECC_MAXIMIZE_STRENGTH; in nand_set_ecc_soft_ops()
5676 WARN(1, "BCH ECC initialization failed!\n"); in nand_set_ecc_soft_ops()
5682 WARN(1, "Unsupported ECC algorithm!\n"); in nand_set_ecc_soft_ops()
5683 return -EINVAL; in nand_set_ecc_soft_ops()
5688 * nand_check_ecc_caps - check the sanity of preset ECC settings
5689 * @chip: nand chip info structure
5690 * @caps: ECC caps info structure
5691 * @oobavail: OOB size that the ECC engine can use
5693 * When ECC step size and strength are already set, check if they are supported
5694 * by the controller and the calculated ECC bytes fit within the chip's OOB.
5695 * On success, the calculated ECC bytes is set.
5703 int preset_step = chip->ecc.size; in nand_check_ecc_caps()
5704 int preset_strength = chip->ecc.strength; in nand_check_ecc_caps()
5705 int ecc_bytes, nsteps = mtd->writesize / preset_step; in nand_check_ecc_caps()
5708 for (i = 0; i < caps->nstepinfos; i++) { in nand_check_ecc_caps()
5709 stepinfo = &caps->stepinfos[i]; in nand_check_ecc_caps()
5711 if (stepinfo->stepsize != preset_step) in nand_check_ecc_caps()
5714 for (j = 0; j < stepinfo->nstrengths; j++) { in nand_check_ecc_caps()
5715 if (stepinfo->strengths[j] != preset_strength) in nand_check_ecc_caps()
5718 ecc_bytes = caps->calc_ecc_bytes(preset_step, in nand_check_ecc_caps()
5724 pr_err("ECC (step, strength) = (%d, %d) does not fit in OOB", in nand_check_ecc_caps()
5726 return -ENOSPC; in nand_check_ecc_caps()
5729 chip->ecc.bytes = ecc_bytes; in nand_check_ecc_caps()
5735 pr_err("ECC (step, strength) = (%d, %d) not supported on this controller", in nand_check_ecc_caps()
5738 return -ENOTSUPP; in nand_check_ecc_caps()
5742 * nand_match_ecc_req - meet the chip's requirement with least ECC bytes
5743 * @chip: nand chip info structure
5744 * @caps: ECC engine caps info structure
5745 * @oobavail: OOB size that the ECC engine can use
5747 * If a chip's ECC requirement is provided, try to meet it with the least
5748 * number of ECC bytes (i.e. with the largest number of OOB-free bytes).
5749 * On success, the chosen ECC settings are set.
5756 nanddev_get_ecc_requirements(&chip->base); in nand_match_ecc_req()
5759 int req_step = requirements->step_size; in nand_match_ecc_req()
5760 int req_strength = requirements->strength; in nand_match_ecc_req()
5766 /* No information provided by the NAND chip */ in nand_match_ecc_req()
5768 return -ENOTSUPP; in nand_match_ecc_req()
5771 req_corr = mtd->writesize / req_step * req_strength; in nand_match_ecc_req()
5773 for (i = 0; i < caps->nstepinfos; i++) { in nand_match_ecc_req()
5774 stepinfo = &caps->stepinfos[i]; in nand_match_ecc_req()
5775 step_size = stepinfo->stepsize; in nand_match_ecc_req()
5777 for (j = 0; j < stepinfo->nstrengths; j++) { in nand_match_ecc_req()
5778 strength = stepinfo->strengths[j]; in nand_match_ecc_req()
5788 if (mtd->writesize % step_size) in nand_match_ecc_req()
5791 nsteps = mtd->writesize / step_size; in nand_match_ecc_req()
5793 ecc_bytes = caps->calc_ecc_bytes(step_size, strength); in nand_match_ecc_req()
5804 * with the least number of ECC bytes. in nand_match_ecc_req()
5816 return -ENOTSUPP; in nand_match_ecc_req()
5818 chip->ecc.size = best_step; in nand_match_ecc_req()
5819 chip->ecc.strength = best_strength; in nand_match_ecc_req()
5820 chip->ecc.bytes = best_ecc_bytes; in nand_match_ecc_req()
5826 * nand_maximize_ecc - choose the max ECC strength available
5827 * @chip: nand chip info structure
5828 * @caps: ECC engine caps info structure
5829 * @oobavail: OOB size that the ECC engine can use
5831 * Choose the max ECC strength that is supported on the controller, and can fit
5832 * within the chip's OOB. On success, the chosen ECC settings are set.
5846 for (i = 0; i < caps->nstepinfos; i++) { in nand_maximize_ecc()
5847 stepinfo = &caps->stepinfos[i]; in nand_maximize_ecc()
5848 step_size = stepinfo->stepsize; in nand_maximize_ecc()
5850 /* If chip->ecc.size is already set, respect it */ in nand_maximize_ecc()
5851 if (chip->ecc.size && step_size != chip->ecc.size) in nand_maximize_ecc()
5854 for (j = 0; j < stepinfo->nstrengths; j++) { in nand_maximize_ecc()
5855 strength = stepinfo->strengths[j]; in nand_maximize_ecc()
5857 if (mtd->writesize % step_size) in nand_maximize_ecc()
5860 nsteps = mtd->writesize / step_size; in nand_maximize_ecc()
5862 ecc_bytes = caps->calc_ecc_bytes(step_size, strength); in nand_maximize_ecc()
5886 return -ENOTSUPP; in nand_maximize_ecc()
5888 chip->ecc.size = best_step; in nand_maximize_ecc()
5889 chip->ecc.strength = best_strength; in nand_maximize_ecc()
5890 chip->ecc.bytes = best_ecc_bytes; in nand_maximize_ecc()
5896 * nand_ecc_choose_conf - Set the ECC strength and ECC step size
5897 * @chip: nand chip info structure
5898 * @caps: ECC engine caps info structure
5899 * @oobavail: OOB size that the ECC engine can use
5901 * Choose the ECC configuration according to following logic.
5903 * 1. If both ECC step size and ECC strength are already set (usually by DT)
5905 * 2. If the user provided the nand-ecc-maximize property, then select maximum
5906 * ECC strength.
5907 * 3. Otherwise, try to match the ECC step size and ECC strength closest
5909 * requirement then fallback to the maximum ECC step size and ECC strength.
5911 * On success, the chosen ECC settings are set.
5919 if (WARN_ON(oobavail < 0 || oobavail > mtd->oobsize)) in nand_ecc_choose_conf()
5920 return -EINVAL; in nand_ecc_choose_conf()
5922 if (chip->ecc.size && chip->ecc.strength) in nand_ecc_choose_conf()
5925 if (nanddev->ecc.user_conf.flags & NAND_ECC_MAXIMIZE_STRENGTH) in nand_ecc_choose_conf()
5935 static int rawnand_erase(struct nand_device *nand, const struct nand_pos *pos) in rawnand_erase() argument
5937 struct nand_chip *chip = container_of(nand, struct nand_chip, in rawnand_erase()
5939 unsigned int eb = nanddev_pos_to_row(nand, pos); in rawnand_erase()
5942 eb >>= nand->rowconv.eraseblock_addr_shift; in rawnand_erase()
5944 nand_select_target(chip, pos->target); in rawnand_erase()
5951 static int rawnand_markbad(struct nand_device *nand, in rawnand_markbad() argument
5954 struct nand_chip *chip = container_of(nand, struct nand_chip, in rawnand_markbad()
5957 return nand_markbad_bbm(chip, nanddev_pos_to_offs(nand, pos)); in rawnand_markbad()
5960 static bool rawnand_isbad(struct nand_device *nand, const struct nand_pos *pos) in rawnand_isbad() argument
5962 struct nand_chip *chip = container_of(nand, struct nand_chip, in rawnand_isbad()
5966 nand_select_target(chip, pos->target); in rawnand_isbad()
5967 ret = nand_isbad_bbm(chip, nanddev_pos_to_offs(nand, pos)); in rawnand_isbad()
5980 * nand_scan_tail - Scan for the NAND device
5981 * @chip: NAND chip object
5990 struct nand_ecc_ctrl *ecc = &chip->ecc; in nand_scan_tail() local
5993 /* New bad blocks should be marked in OOB, flash-based BBT, or both */ in nand_scan_tail()
5994 if (WARN_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) && in nand_scan_tail()
5995 !(chip->bbt_options & NAND_BBT_USE_FLASH))) { in nand_scan_tail()
5996 return -EINVAL; in nand_scan_tail()
5999 chip->data_buf = kmalloc(mtd->writesize + mtd->oobsize, GFP_KERNEL); in nand_scan_tail()
6000 if (!chip->data_buf) in nand_scan_tail()
6001 return -ENOMEM; in nand_scan_tail()
6004 * FIXME: some NAND manufacturer drivers expect the first die to be in nand_scan_tail()
6005 * selected when manufacturer->init() is called. They should be fixed in nand_scan_tail()
6006 * to explictly select the relevant die when interacting with the NAND in nand_scan_tail()
6016 chip->oob_poi = chip->data_buf + mtd->writesize; in nand_scan_tail()
6021 if (!mtd->ooblayout && in nand_scan_tail()
6022 !(ecc->engine_type == NAND_ECC_ENGINE_TYPE_SOFT && in nand_scan_tail()
6023 ecc->algo == NAND_ECC_ALGO_BCH) && in nand_scan_tail()
6024 !(ecc->engine_type == NAND_ECC_ENGINE_TYPE_SOFT && in nand_scan_tail()
6025 ecc->algo == NAND_ECC_ALGO_HAMMING)) { in nand_scan_tail()
6026 switch (mtd->oobsize) { in nand_scan_tail()
6040 * ->oobsize, but we must keep the old large/small in nand_scan_tail()
6041 * page with ECC layout when ->oobsize <= 128 for in nand_scan_tail()
6044 if (ecc->engine_type == NAND_ECC_ENGINE_TYPE_NONE) { in nand_scan_tail()
6051 mtd->oobsize); in nand_scan_tail()
6052 ret = -EINVAL; in nand_scan_tail()
6058 * Check ECC mode, default to software if 3byte/512byte hardware ECC is in nand_scan_tail()
6059 * selected and we have 256 byte pagesize fallback to software ECC in nand_scan_tail()
6062 switch (ecc->engine_type) { in nand_scan_tail()
6068 if (mtd->writesize >= ecc->size) { in nand_scan_tail()
6069 if (!ecc->strength) { in nand_scan_tail()
6070 WARN(1, "Driver must set ecc.strength when using hardware ECC\n"); in nand_scan_tail()
6071 ret = -EINVAL; in nand_scan_tail()
6076 pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n", in nand_scan_tail()
6077 ecc->size, mtd->writesize); in nand_scan_tail()
6078 ecc->engine_type = NAND_ECC_ENGINE_TYPE_SOFT; in nand_scan_tail()
6079 ecc->algo = NAND_ECC_ALGO_HAMMING; in nand_scan_tail()
6089 if (!ecc->read_page || !ecc->write_page) { in nand_scan_tail()
6090 WARN(1, "No ECC functions supplied; on-die ECC not possible\n"); in nand_scan_tail()
6091 ret = -EINVAL; in nand_scan_tail()
6094 if (!ecc->read_oob) in nand_scan_tail()
6095 ecc->read_oob = nand_read_oob_std; in nand_scan_tail()
6096 if (!ecc->write_oob) in nand_scan_tail()
6097 ecc->write_oob = nand_write_oob_std; in nand_scan_tail()
6102 ecc->read_page = nand_read_page_raw; in nand_scan_tail()
6103 ecc->write_page = nand_write_page_raw; in nand_scan_tail()
6104 ecc->read_oob = nand_read_oob_std; in nand_scan_tail()
6105 ecc->read_page_raw = nand_read_page_raw; in nand_scan_tail()
6106 ecc->write_page_raw = nand_write_page_raw; in nand_scan_tail()
6107 ecc->write_oob = nand_write_oob_std; in nand_scan_tail()
6108 ecc->size = mtd->writesize; in nand_scan_tail()
6109 ecc->bytes = 0; in nand_scan_tail()
6110 ecc->strength = 0; in nand_scan_tail()
6114 WARN(1, "Invalid NAND_ECC_MODE %d\n", ecc->engine_type); in nand_scan_tail()
6115 ret = -EINVAL; in nand_scan_tail()
6119 if (ecc->correct || ecc->calculate) { in nand_scan_tail()
6120 ecc->calc_buf = kmalloc(mtd->oobsize, GFP_KERNEL); in nand_scan_tail()
6121 ecc->code_buf = kmalloc(mtd->oobsize, GFP_KERNEL); in nand_scan_tail()
6122 if (!ecc->calc_buf || !ecc->code_buf) { in nand_scan_tail()
6123 ret = -ENOMEM; in nand_scan_tail()
6129 if (!ecc->read_oob_raw) in nand_scan_tail()
6130 ecc->read_oob_raw = ecc->read_oob; in nand_scan_tail()
6131 if (!ecc->write_oob_raw) in nand_scan_tail()
6132 ecc->write_oob_raw = ecc->write_oob; in nand_scan_tail()
6134 /* propagate ecc info to mtd_info */ in nand_scan_tail()
6135 mtd->ecc_strength = ecc->strength; in nand_scan_tail()
6136 mtd->ecc_step_size = ecc->size; in nand_scan_tail()
6139 * Set the number of read / write steps for one page depending on ECC in nand_scan_tail()
6142 if (!ecc->steps) in nand_scan_tail()
6143 ecc->steps = mtd->writesize / ecc->size; in nand_scan_tail()
6144 if (ecc->steps * ecc->size != mtd->writesize) { in nand_scan_tail()
6145 WARN(1, "Invalid ECC parameters\n"); in nand_scan_tail()
6146 ret = -EINVAL; in nand_scan_tail()
6150 if (!ecc->total) { in nand_scan_tail()
6151 ecc->total = ecc->steps * ecc->bytes; in nand_scan_tail()
6152 chip->base.ecc.ctx.total = ecc->total; in nand_scan_tail()
6155 if (ecc->total > mtd->oobsize) { in nand_scan_tail()
6156 WARN(1, "Total number of ECC bytes exceeded oobsize\n"); in nand_scan_tail()
6157 ret = -EINVAL; in nand_scan_tail()
6169 mtd->oobavail = ret; in nand_scan_tail()
6171 /* ECC sanity check: warn if it's too weak */ in nand_scan_tail()
6172 if (!nand_ecc_is_strong_enough(&chip->base)) in nand_scan_tail()
6173 …pr_warn("WARNING: %s: the ECC used on your system (%db/%dB) is too weak compared to the one requir… in nand_scan_tail()
6174 mtd->name, chip->ecc.strength, chip->ecc.size, in nand_scan_tail()
6175 nanddev_get_ecc_requirements(&chip->base)->strength, in nand_scan_tail()
6176 nanddev_get_ecc_requirements(&chip->base)->step_size); in nand_scan_tail()
6178 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */ in nand_scan_tail()
6179 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) { in nand_scan_tail()
6180 switch (ecc->steps) { in nand_scan_tail()
6182 mtd->subpage_sft = 1; in nand_scan_tail()
6187 mtd->subpage_sft = 2; in nand_scan_tail()
6191 chip->subpagesize = mtd->writesize >> mtd->subpage_sft; in nand_scan_tail()
6194 chip->pagecache.page = -1; in nand_scan_tail()
6196 /* Large page NAND with SOFT_ECC should support subpage reads */ in nand_scan_tail()
6197 switch (ecc->engine_type) { in nand_scan_tail()
6199 if (chip->page_shift > 9) in nand_scan_tail()
6200 chip->options |= NAND_SUBPAGE_READ; in nand_scan_tail()
6207 ret = nanddev_init(&chip->base, &rawnand_ops, mtd->owner); in nand_scan_tail()
6212 if (chip->options & NAND_ROM) in nand_scan_tail()
6213 mtd->flags = MTD_CAP_ROM; in nand_scan_tail()
6216 mtd->_erase = nand_erase; in nand_scan_tail()
6217 mtd->_point = NULL; in nand_scan_tail()
6218 mtd->_unpoint = NULL; in nand_scan_tail()
6219 mtd->_panic_write = panic_nand_write; in nand_scan_tail()
6220 mtd->_read_oob = nand_read_oob; in nand_scan_tail()
6221 mtd->_write_oob = nand_write_oob; in nand_scan_tail()
6222 mtd->_sync = nand_sync; in nand_scan_tail()
6223 mtd->_lock = nand_lock; in nand_scan_tail()
6224 mtd->_unlock = nand_unlock; in nand_scan_tail()
6225 mtd->_suspend = nand_suspend; in nand_scan_tail()
6226 mtd->_resume = nand_resume; in nand_scan_tail()
6227 mtd->_reboot = nand_shutdown; in nand_scan_tail()
6228 mtd->_block_isreserved = nand_block_isreserved; in nand_scan_tail()
6229 mtd->_block_isbad = nand_block_isbad; in nand_scan_tail()
6230 mtd->_block_markbad = nand_block_markbad; in nand_scan_tail()
6231 mtd->_max_bad_blocks = nanddev_mtd_max_bad_blocks; in nand_scan_tail()
6238 if (!mtd->bitflip_threshold) in nand_scan_tail()
6239 mtd->bitflip_threshold = DIV_ROUND_UP(mtd->ecc_strength * 3, 4); in nand_scan_tail()
6247 for (i = 0; i < nanddev_ntargets(&chip->base); i++) { in nand_scan_tail()
6254 * Look for secure regions in the NAND chip. These regions are supposed in nand_scan_tail()
6264 if (chip->options & NAND_SKIP_BBTSCAN) in nand_scan_tail()
6275 kfree(chip->secure_regions); in nand_scan_tail()
6278 kfree(chip->best_interface_config); in nand_scan_tail()
6281 nanddev_cleanup(&chip->base); in nand_scan_tail()
6287 kfree(chip->data_buf); in nand_scan_tail()
6288 kfree(ecc->code_buf); in nand_scan_tail()
6289 kfree(ecc->calc_buf); in nand_scan_tail()
6296 if (chip->controller->ops && chip->controller->ops->attach_chip) in nand_attach()
6297 return chip->controller->ops->attach_chip(chip); in nand_attach()
6304 if (chip->controller->ops && chip->controller->ops->detach_chip) in nand_detach()
6305 chip->controller->ops->detach_chip(chip); in nand_detach()
6309 * nand_scan_with_ids - [NAND Interface] Scan for the NAND device
6310 * @chip: NAND chip object
6324 return -EINVAL; in nand_scan_with_ids()
6350 * nand_cleanup - [NAND Interface] Free resources held by the NAND device
6351 * @chip: NAND chip object
6355 if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT) { in nand_cleanup()
6356 if (chip->ecc.algo == NAND_ECC_ALGO_HAMMING) in nand_cleanup()
6358 else if (chip->ecc.algo == NAND_ECC_ALGO_BCH) in nand_cleanup()
6362 nanddev_cleanup(&chip->base); in nand_cleanup()
6365 kfree(chip->secure_regions); in nand_cleanup()
6368 kfree(chip->bbt); in nand_cleanup()
6369 kfree(chip->data_buf); in nand_cleanup()
6370 kfree(chip->ecc.code_buf); in nand_cleanup()
6371 kfree(chip->ecc.calc_buf); in nand_cleanup()
6374 if (chip->badblock_pattern && chip->badblock_pattern->options in nand_cleanup()
6376 kfree(chip->badblock_pattern); in nand_cleanup()
6379 kfree(chip->best_interface_config); in nand_cleanup()
6396 MODULE_DESCRIPTION("Generic NAND flash driver code");