Lines Matching full:ctrl
312 struct brcmnand_controller *ctrl; member
595 static inline u32 nand_readreg(struct brcmnand_controller *ctrl, u32 offs) in nand_readreg() argument
597 return brcmnand_readl(ctrl->nand_base + offs); in nand_readreg()
600 static inline void nand_writereg(struct brcmnand_controller *ctrl, u32 offs, in nand_writereg() argument
603 brcmnand_writel(val, ctrl->nand_base + offs); in nand_writereg()
606 static int brcmnand_revision_init(struct brcmnand_controller *ctrl) in brcmnand_revision_init() argument
616 ctrl->nand_version = nand_readreg(ctrl, 0) & 0xffff; in brcmnand_revision_init()
619 if (ctrl->nand_version < 0x0201) { in brcmnand_revision_init()
620 dev_err(ctrl->dev, "version %#x not supported\n", in brcmnand_revision_init()
621 ctrl->nand_version); in brcmnand_revision_init()
626 if (ctrl->nand_version >= 0x0702) in brcmnand_revision_init()
627 ctrl->reg_offsets = brcmnand_regs_v72; in brcmnand_revision_init()
628 else if (ctrl->nand_version == 0x0701) in brcmnand_revision_init()
629 ctrl->reg_offsets = brcmnand_regs_v71; in brcmnand_revision_init()
630 else if (ctrl->nand_version >= 0x0600) in brcmnand_revision_init()
631 ctrl->reg_offsets = brcmnand_regs_v60; in brcmnand_revision_init()
632 else if (ctrl->nand_version >= 0x0500) in brcmnand_revision_init()
633 ctrl->reg_offsets = brcmnand_regs_v50; in brcmnand_revision_init()
634 else if (ctrl->nand_version >= 0x0303) in brcmnand_revision_init()
635 ctrl->reg_offsets = brcmnand_regs_v33; in brcmnand_revision_init()
636 else if (ctrl->nand_version >= 0x0201) in brcmnand_revision_init()
637 ctrl->reg_offsets = brcmnand_regs_v21; in brcmnand_revision_init()
640 if (ctrl->nand_version >= 0x0701) in brcmnand_revision_init()
641 ctrl->reg_spacing = 0x14; in brcmnand_revision_init()
643 ctrl->reg_spacing = 0x10; in brcmnand_revision_init()
646 if (ctrl->nand_version >= 0x0701) { in brcmnand_revision_init()
647 ctrl->cs_offsets = brcmnand_cs_offsets_v71; in brcmnand_revision_init()
649 ctrl->cs_offsets = brcmnand_cs_offsets; in brcmnand_revision_init()
652 if (ctrl->nand_version >= 0x0303 && in brcmnand_revision_init()
653 ctrl->nand_version <= 0x0500) in brcmnand_revision_init()
654 ctrl->cs0_offsets = brcmnand_cs_offsets_cs0; in brcmnand_revision_init()
658 if (ctrl->nand_version >= 0x0701) { in brcmnand_revision_init()
660 ctrl->max_page_size = 16 * 1024; in brcmnand_revision_init()
661 ctrl->max_block_size = 2 * 1024 * 1024; in brcmnand_revision_init()
663 if (ctrl->nand_version >= 0x0304) in brcmnand_revision_init()
664 ctrl->page_sizes = page_sizes_v3_4; in brcmnand_revision_init()
665 else if (ctrl->nand_version >= 0x0202) in brcmnand_revision_init()
666 ctrl->page_sizes = page_sizes_v2_2; in brcmnand_revision_init()
668 ctrl->page_sizes = page_sizes_v2_1; in brcmnand_revision_init()
670 if (ctrl->nand_version >= 0x0202) in brcmnand_revision_init()
671 ctrl->page_size_shift = CFG_PAGE_SIZE_SHIFT; in brcmnand_revision_init()
673 ctrl->page_size_shift = CFG_PAGE_SIZE_SHIFT_v2_1; in brcmnand_revision_init()
675 if (ctrl->nand_version >= 0x0600) in brcmnand_revision_init()
676 ctrl->block_sizes = block_sizes_v6; in brcmnand_revision_init()
677 else if (ctrl->nand_version >= 0x0400) in brcmnand_revision_init()
678 ctrl->block_sizes = block_sizes_v4; in brcmnand_revision_init()
679 else if (ctrl->nand_version >= 0x0202) in brcmnand_revision_init()
680 ctrl->block_sizes = block_sizes_v2_2; in brcmnand_revision_init()
682 ctrl->block_sizes = block_sizes_v2_1; in brcmnand_revision_init()
684 if (ctrl->nand_version < 0x0400) { in brcmnand_revision_init()
685 if (ctrl->nand_version < 0x0202) in brcmnand_revision_init()
686 ctrl->max_page_size = 2048; in brcmnand_revision_init()
688 ctrl->max_page_size = 4096; in brcmnand_revision_init()
689 ctrl->max_block_size = 512 * 1024; in brcmnand_revision_init()
694 if (ctrl->nand_version == 0x0702) in brcmnand_revision_init()
695 ctrl->max_oob = 128; in brcmnand_revision_init()
696 else if (ctrl->nand_version >= 0x0600) in brcmnand_revision_init()
697 ctrl->max_oob = 64; in brcmnand_revision_init()
698 else if (ctrl->nand_version >= 0x0500) in brcmnand_revision_init()
699 ctrl->max_oob = 32; in brcmnand_revision_init()
701 ctrl->max_oob = 16; in brcmnand_revision_init()
704 if (ctrl->nand_version >= 0x0600 && ctrl->nand_version != 0x0601) in brcmnand_revision_init()
705 ctrl->features |= BRCMNAND_HAS_PREFETCH; in brcmnand_revision_init()
711 if (ctrl->nand_version >= 0x0700) in brcmnand_revision_init()
712 ctrl->features |= BRCMNAND_HAS_CACHE_MODE; in brcmnand_revision_init()
714 if (ctrl->nand_version >= 0x0500) in brcmnand_revision_init()
715 ctrl->features |= BRCMNAND_HAS_1K_SECTORS; in brcmnand_revision_init()
717 if (ctrl->nand_version >= 0x0700) in brcmnand_revision_init()
718 ctrl->features |= BRCMNAND_HAS_WP; in brcmnand_revision_init()
719 else if (of_property_read_bool(ctrl->dev->of_node, "brcm,nand-has-wp")) in brcmnand_revision_init()
720 ctrl->features |= BRCMNAND_HAS_WP; in brcmnand_revision_init()
725 static void brcmnand_flash_dma_revision_init(struct brcmnand_controller *ctrl) in brcmnand_flash_dma_revision_init() argument
728 if (ctrl->nand_version >= 0x0703) in brcmnand_flash_dma_revision_init()
729 ctrl->flash_dma_offsets = flash_dma_regs_v4; in brcmnand_flash_dma_revision_init()
730 else if (ctrl->nand_version == 0x0602) in brcmnand_flash_dma_revision_init()
731 ctrl->flash_dma_offsets = flash_dma_regs_v0; in brcmnand_flash_dma_revision_init()
733 ctrl->flash_dma_offsets = flash_dma_regs_v1; in brcmnand_flash_dma_revision_init()
736 static inline u32 brcmnand_read_reg(struct brcmnand_controller *ctrl, in brcmnand_read_reg() argument
739 u16 offs = ctrl->reg_offsets[reg]; in brcmnand_read_reg()
742 return nand_readreg(ctrl, offs); in brcmnand_read_reg()
747 static inline void brcmnand_write_reg(struct brcmnand_controller *ctrl, in brcmnand_write_reg() argument
750 u16 offs = ctrl->reg_offsets[reg]; in brcmnand_write_reg()
753 nand_writereg(ctrl, offs, val); in brcmnand_write_reg()
756 static inline void brcmnand_rmw_reg(struct brcmnand_controller *ctrl, in brcmnand_rmw_reg() argument
760 u32 tmp = brcmnand_read_reg(ctrl, reg); in brcmnand_rmw_reg()
764 brcmnand_write_reg(ctrl, reg, tmp); in brcmnand_rmw_reg()
767 static inline u32 brcmnand_read_fc(struct brcmnand_controller *ctrl, int word) in brcmnand_read_fc() argument
769 return __raw_readl(ctrl->nand_fc + word * 4); in brcmnand_read_fc()
772 static inline void brcmnand_write_fc(struct brcmnand_controller *ctrl, in brcmnand_write_fc() argument
775 __raw_writel(val, ctrl->nand_fc + word * 4); in brcmnand_write_fc()
778 static inline void edu_writel(struct brcmnand_controller *ctrl, in edu_writel() argument
781 u16 offs = ctrl->edu_offsets[reg]; in edu_writel()
783 brcmnand_writel(val, ctrl->edu_base + offs); in edu_writel()
786 static inline u32 edu_readl(struct brcmnand_controller *ctrl, in edu_readl() argument
789 u16 offs = ctrl->edu_offsets[reg]; in edu_readl()
791 return brcmnand_readl(ctrl->edu_base + offs); in edu_readl()
794 static void brcmnand_clear_ecc_addr(struct brcmnand_controller *ctrl) in brcmnand_clear_ecc_addr() argument
798 brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_ADDR, 0); in brcmnand_clear_ecc_addr()
799 brcmnand_write_reg(ctrl, BRCMNAND_CORR_ADDR, 0); in brcmnand_clear_ecc_addr()
800 brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_EXT_ADDR, 0); in brcmnand_clear_ecc_addr()
801 brcmnand_write_reg(ctrl, BRCMNAND_CORR_EXT_ADDR, 0); in brcmnand_clear_ecc_addr()
804 static u64 brcmnand_get_uncorrecc_addr(struct brcmnand_controller *ctrl) in brcmnand_get_uncorrecc_addr() argument
808 err_addr = brcmnand_read_reg(ctrl, BRCMNAND_UNCORR_ADDR); in brcmnand_get_uncorrecc_addr()
809 err_addr |= ((u64)(brcmnand_read_reg(ctrl, in brcmnand_get_uncorrecc_addr()
816 static u64 brcmnand_get_correcc_addr(struct brcmnand_controller *ctrl) in brcmnand_get_correcc_addr() argument
820 err_addr = brcmnand_read_reg(ctrl, BRCMNAND_CORR_ADDR); in brcmnand_get_correcc_addr()
821 err_addr |= ((u64)(brcmnand_read_reg(ctrl, in brcmnand_get_correcc_addr()
832 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_set_cmd_addr() local
834 brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS, in brcmnand_set_cmd_addr()
836 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS); in brcmnand_set_cmd_addr()
837 brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS, in brcmnand_set_cmd_addr()
839 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS); in brcmnand_set_cmd_addr()
842 static inline u16 brcmnand_cs_offset(struct brcmnand_controller *ctrl, int cs, in brcmnand_cs_offset() argument
845 u16 offs_cs0 = ctrl->reg_offsets[BRCMNAND_CS0_BASE]; in brcmnand_cs_offset()
846 u16 offs_cs1 = ctrl->reg_offsets[BRCMNAND_CS1_BASE]; in brcmnand_cs_offset()
849 if (cs == 0 && ctrl->cs0_offsets) in brcmnand_cs_offset()
850 cs_offs = ctrl->cs0_offsets[reg]; in brcmnand_cs_offset()
852 cs_offs = ctrl->cs_offsets[reg]; in brcmnand_cs_offset()
855 return offs_cs1 + (cs - 1) * ctrl->reg_spacing + cs_offs; in brcmnand_cs_offset()
857 return offs_cs0 + cs * ctrl->reg_spacing + cs_offs; in brcmnand_cs_offset()
860 static inline u32 brcmnand_count_corrected(struct brcmnand_controller *ctrl) in brcmnand_count_corrected() argument
862 if (ctrl->nand_version < 0x0600) in brcmnand_count_corrected()
864 return brcmnand_read_reg(ctrl, BRCMNAND_CORR_COUNT); in brcmnand_count_corrected()
869 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_wr_corr_thresh() local
874 if (!ctrl->reg_offsets[reg]) in brcmnand_wr_corr_thresh()
877 if (ctrl->nand_version == 0x0702) in brcmnand_wr_corr_thresh()
879 else if (ctrl->nand_version >= 0x0600) in brcmnand_wr_corr_thresh()
881 else if (ctrl->nand_version >= 0x0500) in brcmnand_wr_corr_thresh()
886 if (ctrl->nand_version >= 0x0702) { in brcmnand_wr_corr_thresh()
890 } else if (ctrl->nand_version >= 0x0600) { in brcmnand_wr_corr_thresh()
895 brcmnand_rmw_reg(ctrl, reg, (bits - 1) << shift, shift, val); in brcmnand_wr_corr_thresh()
898 static inline int brcmnand_cmd_shift(struct brcmnand_controller *ctrl) in brcmnand_cmd_shift() argument
900 if (ctrl->nand_version < 0x0602) in brcmnand_cmd_shift()
929 static inline u32 brcmnand_spare_area_mask(struct brcmnand_controller *ctrl) in brcmnand_spare_area_mask() argument
931 if (ctrl->nand_version == 0x0702) in brcmnand_spare_area_mask()
933 else if (ctrl->nand_version >= 0x0600) in brcmnand_spare_area_mask()
935 else if (ctrl->nand_version >= 0x0303) in brcmnand_spare_area_mask()
944 static inline u32 brcmnand_ecc_level_mask(struct brcmnand_controller *ctrl) in brcmnand_ecc_level_mask() argument
946 u32 mask = (ctrl->nand_version >= 0x0600) ? 0x1f : 0x0f; in brcmnand_ecc_level_mask()
951 if (ctrl->nand_version >= 0x0702) in brcmnand_ecc_level_mask()
959 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_set_ecc_enabled() local
960 u16 offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL); in brcmnand_set_ecc_enabled()
961 u32 acc_control = nand_readreg(ctrl, offs); in brcmnand_set_ecc_enabled()
970 acc_control &= ~brcmnand_ecc_level_mask(ctrl); in brcmnand_set_ecc_enabled()
973 nand_writereg(ctrl, offs, acc_control); in brcmnand_set_ecc_enabled()
976 static inline int brcmnand_sector_1k_shift(struct brcmnand_controller *ctrl) in brcmnand_sector_1k_shift() argument
978 if (ctrl->nand_version >= 0x0702) in brcmnand_sector_1k_shift()
980 else if (ctrl->nand_version >= 0x0600) in brcmnand_sector_1k_shift()
982 else if (ctrl->nand_version >= 0x0500) in brcmnand_sector_1k_shift()
990 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_get_sector_size_1k() local
991 int shift = brcmnand_sector_1k_shift(ctrl); in brcmnand_get_sector_size_1k()
992 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, in brcmnand_get_sector_size_1k()
998 return (nand_readreg(ctrl, acc_control_offs) >> shift) & 0x1; in brcmnand_get_sector_size_1k()
1003 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_set_sector_size_1k() local
1004 int shift = brcmnand_sector_1k_shift(ctrl); in brcmnand_set_sector_size_1k()
1005 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, in brcmnand_set_sector_size_1k()
1012 tmp = nand_readreg(ctrl, acc_control_offs); in brcmnand_set_sector_size_1k()
1015 nand_writereg(ctrl, acc_control_offs, tmp); in brcmnand_set_sector_size_1k()
1027 static int bcmnand_ctrl_poll_status(struct brcmnand_controller *ctrl, in bcmnand_ctrl_poll_status() argument
1039 val = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS); in bcmnand_ctrl_poll_status()
1046 dev_warn(ctrl->dev, "timeout on status poll (expected %x got %x)\n", in bcmnand_ctrl_poll_status()
1052 static inline void brcmnand_set_wp(struct brcmnand_controller *ctrl, bool en) in brcmnand_set_wp() argument
1056 brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT, CS_SELECT_NAND_WP, 0, val); in brcmnand_set_wp()
1063 static inline bool has_flash_dma(struct brcmnand_controller *ctrl) in has_flash_dma() argument
1065 return ctrl->flash_dma_base; in has_flash_dma()
1068 static inline bool has_edu(struct brcmnand_controller *ctrl) in has_edu() argument
1070 return ctrl->edu_base; in has_edu()
1073 static inline bool use_dma(struct brcmnand_controller *ctrl) in use_dma() argument
1075 return has_flash_dma(ctrl) || has_edu(ctrl); in use_dma()
1078 static inline void disable_ctrl_irqs(struct brcmnand_controller *ctrl) in disable_ctrl_irqs() argument
1080 if (ctrl->pio_poll_mode) in disable_ctrl_irqs()
1083 if (has_flash_dma(ctrl)) { in disable_ctrl_irqs()
1084 ctrl->flash_dma_base = NULL; in disable_ctrl_irqs()
1085 disable_irq(ctrl->dma_irq); in disable_ctrl_irqs()
1088 disable_irq(ctrl->irq); in disable_ctrl_irqs()
1089 ctrl->pio_poll_mode = true; in disable_ctrl_irqs()
1098 static inline void flash_dma_writel(struct brcmnand_controller *ctrl, in flash_dma_writel() argument
1101 u16 offs = ctrl->flash_dma_offsets[dma_reg]; in flash_dma_writel()
1103 brcmnand_writel(val, ctrl->flash_dma_base + offs); in flash_dma_writel()
1106 static inline u32 flash_dma_readl(struct brcmnand_controller *ctrl, in flash_dma_readl() argument
1109 u16 offs = ctrl->flash_dma_offsets[dma_reg]; in flash_dma_readl()
1111 return brcmnand_readl(ctrl->flash_dma_base + offs); in flash_dma_readl()
1126 static inline bool is_hamming_ecc(struct brcmnand_controller *ctrl, in is_hamming_ecc() argument
1129 if (ctrl->nand_version <= 0x0701) in is_hamming_ecc()
1290 if (is_hamming_ecc(host->ctrl, p)) { in brcmstb_choose_ecc_layout()
1322 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_wp() local
1324 if ((ctrl->features & BRCMNAND_HAS_WP) && wp_on == 1) { in brcmnand_wp()
1329 dev_dbg(ctrl->dev, "WP %s\n", wp ? "on" : "off"); in brcmnand_wp()
1334 * make sure ctrl/flash ready before and after in brcmnand_wp()
1337 ret = bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY | in brcmnand_wp()
1344 brcmnand_set_wp(ctrl, wp); in brcmnand_wp()
1347 ret = bcmnand_ctrl_poll_status(ctrl, in brcmnand_wp()
1363 static inline u8 oob_reg_read(struct brcmnand_controller *ctrl, u32 offs) in oob_reg_read() argument
1367 offset0 = ctrl->reg_offsets[BRCMNAND_OOB_READ_BASE]; in oob_reg_read()
1368 offset10 = ctrl->reg_offsets[BRCMNAND_OOB_READ_10_BASE]; in oob_reg_read()
1370 if (offs >= ctrl->max_oob) in oob_reg_read()
1378 return nand_readreg(ctrl, reg_offs) >> (24 - ((offs & 0x03) << 3)); in oob_reg_read()
1381 static inline void oob_reg_write(struct brcmnand_controller *ctrl, u32 offs, in oob_reg_write() argument
1386 offset0 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_BASE]; in oob_reg_write()
1387 offset10 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_10_BASE]; in oob_reg_write()
1389 if (offs >= ctrl->max_oob) in oob_reg_write()
1397 nand_writereg(ctrl, reg_offs, data); in oob_reg_write()
1402 * @ctrl: NAND controller
1408 static int read_oob_from_regs(struct brcmnand_controller *ctrl, int i, u8 *oob, in read_oob_from_regs() argument
1416 tbytes = max(0, tbytes - (int)ctrl->max_oob); in read_oob_from_regs()
1417 tbytes = min_t(int, tbytes, ctrl->max_oob); in read_oob_from_regs()
1420 oob[j] = oob_reg_read(ctrl, j); in read_oob_from_regs()
1431 static int write_oob_to_regs(struct brcmnand_controller *ctrl, int i, in write_oob_to_regs() argument
1439 tbytes = max(0, tbytes - (int)ctrl->max_oob); in write_oob_to_regs()
1440 tbytes = min_t(int, tbytes, ctrl->max_oob); in write_oob_to_regs()
1443 oob_reg_write(ctrl, j, in write_oob_to_regs()
1451 static void brcmnand_edu_init(struct brcmnand_controller *ctrl) in brcmnand_edu_init() argument
1454 edu_writel(ctrl, EDU_ERR_STATUS, 0); in brcmnand_edu_init()
1455 edu_readl(ctrl, EDU_ERR_STATUS); in brcmnand_edu_init()
1456 edu_writel(ctrl, EDU_DONE, 0); in brcmnand_edu_init()
1457 edu_writel(ctrl, EDU_DONE, 0); in brcmnand_edu_init()
1458 edu_writel(ctrl, EDU_DONE, 0); in brcmnand_edu_init()
1459 edu_writel(ctrl, EDU_DONE, 0); in brcmnand_edu_init()
1460 edu_readl(ctrl, EDU_DONE); in brcmnand_edu_init()
1466 struct brcmnand_controller *ctrl = data; in brcmnand_edu_irq() local
1468 if (ctrl->edu_count) { in brcmnand_edu_irq()
1469 ctrl->edu_count--; in brcmnand_edu_irq()
1470 while (!(edu_readl(ctrl, EDU_DONE) & EDU_DONE_MASK)) in brcmnand_edu_irq()
1472 edu_writel(ctrl, EDU_DONE, 0); in brcmnand_edu_irq()
1473 edu_readl(ctrl, EDU_DONE); in brcmnand_edu_irq()
1476 if (ctrl->edu_count) { in brcmnand_edu_irq()
1477 ctrl->edu_dram_addr += FC_BYTES; in brcmnand_edu_irq()
1478 ctrl->edu_ext_addr += FC_BYTES; in brcmnand_edu_irq()
1480 edu_writel(ctrl, EDU_DRAM_ADDR, (u32)ctrl->edu_dram_addr); in brcmnand_edu_irq()
1481 edu_readl(ctrl, EDU_DRAM_ADDR); in brcmnand_edu_irq()
1482 edu_writel(ctrl, EDU_EXT_ADDR, ctrl->edu_ext_addr); in brcmnand_edu_irq()
1483 edu_readl(ctrl, EDU_EXT_ADDR); in brcmnand_edu_irq()
1485 if (ctrl->oob) { in brcmnand_edu_irq()
1486 if (ctrl->edu_cmd == EDU_CMD_READ) { in brcmnand_edu_irq()
1487 ctrl->oob += read_oob_from_regs(ctrl, in brcmnand_edu_irq()
1488 ctrl->edu_count + 1, in brcmnand_edu_irq()
1489 ctrl->oob, ctrl->sas, in brcmnand_edu_irq()
1490 ctrl->sector_size_1k); in brcmnand_edu_irq()
1492 brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS, in brcmnand_edu_irq()
1493 ctrl->edu_ext_addr); in brcmnand_edu_irq()
1494 brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS); in brcmnand_edu_irq()
1495 ctrl->oob += write_oob_to_regs(ctrl, in brcmnand_edu_irq()
1496 ctrl->edu_count, in brcmnand_edu_irq()
1497 ctrl->oob, ctrl->sas, in brcmnand_edu_irq()
1498 ctrl->sector_size_1k); in brcmnand_edu_irq()
1503 edu_writel(ctrl, EDU_CMD, ctrl->edu_cmd); in brcmnand_edu_irq()
1504 edu_readl(ctrl, EDU_CMD); in brcmnand_edu_irq()
1509 complete(&ctrl->edu_done); in brcmnand_edu_irq()
1516 struct brcmnand_controller *ctrl = data; in brcmnand_ctlrdy_irq() local
1519 if (ctrl->dma_pending) in brcmnand_ctlrdy_irq()
1523 if (ctrl->edu_pending) { in brcmnand_ctlrdy_irq()
1524 if (irq == ctrl->irq && ((int)ctrl->edu_irq >= 0)) in brcmnand_ctlrdy_irq()
1532 complete(&ctrl->done); in brcmnand_ctlrdy_irq()
1539 struct brcmnand_controller *ctrl = data; in brcmnand_irq() local
1541 if (ctrl->soc->ctlrdy_ack(ctrl->soc)) in brcmnand_irq()
1549 struct brcmnand_controller *ctrl = data; in brcmnand_dma_irq() local
1551 complete(&ctrl->dma_done); in brcmnand_dma_irq()
1558 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_send_cmd() local
1562 cmd_addr = brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS); in brcmnand_send_cmd()
1564 dev_dbg(ctrl->dev, "send native cmd %d addr 0x%llx\n", cmd, cmd_addr); in brcmnand_send_cmd()
1566 BUG_ON(ctrl->cmd_pending != 0); in brcmnand_send_cmd()
1567 ctrl->cmd_pending = cmd; in brcmnand_send_cmd()
1569 ret = bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY, NAND_CTRL_RDY, 0); in brcmnand_send_cmd()
1573 brcmnand_write_reg(ctrl, BRCMNAND_CMD_START, in brcmnand_send_cmd()
1574 cmd << brcmnand_cmd_shift(ctrl)); in brcmnand_send_cmd()
1582 unsigned int ctrl) in brcmnand_cmd_ctrl() argument
1590 struct brcmnand_controller *ctrl = host->ctrl; in brcmstb_nand_wait_for_completion() local
1597 disable_ctrl_irqs(ctrl); in brcmstb_nand_wait_for_completion()
1598 sts = bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY, in brcmstb_nand_wait_for_completion()
1605 sts = wait_for_completion_timeout(&ctrl->done, timeo); in brcmstb_nand_wait_for_completion()
1615 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_waitfunc() local
1618 dev_dbg(ctrl->dev, "wait on native cmd %d\n", ctrl->cmd_pending); in brcmnand_waitfunc()
1619 if (ctrl->cmd_pending) in brcmnand_waitfunc()
1623 u32 cmd = brcmnand_read_reg(ctrl, BRCMNAND_CMD_START) in brcmnand_waitfunc()
1624 >> brcmnand_cmd_shift(ctrl); in brcmnand_waitfunc()
1626 dev_err_ratelimited(ctrl->dev, in brcmnand_waitfunc()
1628 dev_err_ratelimited(ctrl->dev, "intfc status %08x\n", in brcmnand_waitfunc()
1629 brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS)); in brcmnand_waitfunc()
1631 ctrl->cmd_pending = 0; in brcmnand_waitfunc()
1632 return brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) & in brcmnand_waitfunc()
1651 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_low_level_op() local
1676 dev_dbg(ctrl->dev, "ll_op cmd %#x\n", tmp); in brcmnand_low_level_op()
1678 brcmnand_write_reg(ctrl, BRCMNAND_LL_OP, tmp); in brcmnand_low_level_op()
1679 (void)brcmnand_read_reg(ctrl, BRCMNAND_LL_OP); in brcmnand_low_level_op()
1690 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_cmdfunc() local
1701 dev_dbg(ctrl->dev, "cmd 0x%x addr 0x%llx\n", command, in brcmnand_cmdfunc()
1758 u32 *flash_cache = (u32 *)ctrl->flash_cache; in brcmnand_cmdfunc()
1761 brcmnand_soc_data_bus_prepare(ctrl->soc, true); in brcmnand_cmdfunc()
1772 flash_cache[i] = be32_to_cpu(brcmnand_read_fc(ctrl, i)); in brcmnand_cmdfunc()
1774 brcmnand_soc_data_bus_unprepare(ctrl->soc, true); in brcmnand_cmdfunc()
1790 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_read_byte() local
1797 ret = brcmnand_read_reg(ctrl, BRCMNAND_ID) >> in brcmnand_read_byte()
1800 ret = brcmnand_read_reg(ctrl, BRCMNAND_ID_EXT) >> in brcmnand_read_byte()
1805 ret = oob_reg_read(ctrl, host->last_byte); in brcmnand_read_byte()
1809 ret = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) & in brcmnand_read_byte()
1824 ret = ctrl->flash_cache[offs]; in brcmnand_read_byte()
1833 ret = brcmnand_read_reg(ctrl, BRCMNAND_LL_RDATA) & 0xff; in brcmnand_read_byte()
1837 dev_dbg(ctrl->dev, "read byte = 0x%02x\n", ret); in brcmnand_read_byte()
1875 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_edu_trans() local
1884 dev_dbg(ctrl->dev, "EDU %s %p:%p\n", ((edu_cmd == EDU_CMD_READ) ? in brcmnand_edu_trans()
1887 pa = dma_map_single(ctrl->dev, buf, len, dir); in brcmnand_edu_trans()
1888 if (dma_mapping_error(ctrl->dev, pa)) { in brcmnand_edu_trans()
1889 dev_err(ctrl->dev, "unable to map buffer for EDU DMA\n"); in brcmnand_edu_trans()
1893 ctrl->edu_pending = true; in brcmnand_edu_trans()
1894 ctrl->edu_dram_addr = pa; in brcmnand_edu_trans()
1895 ctrl->edu_ext_addr = addr; in brcmnand_edu_trans()
1896 ctrl->edu_cmd = edu_cmd; in brcmnand_edu_trans()
1897 ctrl->edu_count = trans; in brcmnand_edu_trans()
1898 ctrl->sas = cfg->spare_area_size; in brcmnand_edu_trans()
1899 ctrl->oob = oob; in brcmnand_edu_trans()
1901 edu_writel(ctrl, EDU_DRAM_ADDR, (u32)ctrl->edu_dram_addr); in brcmnand_edu_trans()
1902 edu_readl(ctrl, EDU_DRAM_ADDR); in brcmnand_edu_trans()
1903 edu_writel(ctrl, EDU_EXT_ADDR, ctrl->edu_ext_addr); in brcmnand_edu_trans()
1904 edu_readl(ctrl, EDU_EXT_ADDR); in brcmnand_edu_trans()
1905 edu_writel(ctrl, EDU_LENGTH, FC_BYTES); in brcmnand_edu_trans()
1906 edu_readl(ctrl, EDU_LENGTH); in brcmnand_edu_trans()
1908 if (ctrl->oob && (ctrl->edu_cmd == EDU_CMD_WRITE)) { in brcmnand_edu_trans()
1909 brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS, in brcmnand_edu_trans()
1910 ctrl->edu_ext_addr); in brcmnand_edu_trans()
1911 brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS); in brcmnand_edu_trans()
1912 ctrl->oob += write_oob_to_regs(ctrl, in brcmnand_edu_trans()
1914 ctrl->oob, ctrl->sas, in brcmnand_edu_trans()
1915 ctrl->sector_size_1k); in brcmnand_edu_trans()
1920 edu_writel(ctrl, EDU_CMD, ctrl->edu_cmd); in brcmnand_edu_trans()
1921 edu_readl(ctrl, EDU_CMD); in brcmnand_edu_trans()
1923 if (wait_for_completion_timeout(&ctrl->edu_done, timeo) <= 0) { in brcmnand_edu_trans()
1924 dev_err(ctrl->dev, in brcmnand_edu_trans()
1926 edu_readl(ctrl, EDU_STATUS), in brcmnand_edu_trans()
1927 edu_readl(ctrl, EDU_ERR_STATUS)); in brcmnand_edu_trans()
1930 dma_unmap_single(ctrl->dev, pa, len, dir); in brcmnand_edu_trans()
1933 if (ctrl->oob && (ctrl->edu_cmd == EDU_CMD_READ)) { in brcmnand_edu_trans()
1934 ctrl->oob += read_oob_from_regs(ctrl, in brcmnand_edu_trans()
1936 ctrl->oob, ctrl->sas, in brcmnand_edu_trans()
1937 ctrl->sector_size_1k); in brcmnand_edu_trans()
1941 if (((brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) & in brcmnand_edu_trans()
1944 dev_info(ctrl->dev, "program failed at %llx\n", in brcmnand_edu_trans()
1950 if (edu_readl(ctrl, EDU_STATUS) & EDU_STATUS_ACTIVE) in brcmnand_edu_trans()
1951 dev_warn(ctrl->dev, "EDU still active: %#x\n", in brcmnand_edu_trans()
1952 edu_readl(ctrl, EDU_STATUS)); in brcmnand_edu_trans()
1954 if (unlikely(edu_readl(ctrl, EDU_ERR_STATUS) & EDU_ERR_STATUS_ERRACK)) { in brcmnand_edu_trans()
1955 dev_warn(ctrl->dev, "EDU RBUS error at addr %llx\n", in brcmnand_edu_trans()
1960 ctrl->edu_pending = false; in brcmnand_edu_trans()
1961 brcmnand_edu_init(ctrl); in brcmnand_edu_trans()
1962 edu_writel(ctrl, EDU_STOP, 0); /* force stop */ in brcmnand_edu_trans()
1963 edu_readl(ctrl, EDU_STOP); in brcmnand_edu_trans()
1972 err_addr = brcmnand_get_uncorrecc_addr(ctrl); in brcmnand_edu_trans()
1974 err_addr = brcmnand_get_correcc_addr(ctrl); in brcmnand_edu_trans()
2022 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_dma_run() local
2025 flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC, lower_32_bits(desc)); in brcmnand_dma_run()
2026 (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC); in brcmnand_dma_run()
2027 if (ctrl->nand_version > 0x0602) { in brcmnand_dma_run()
2028 flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC_EXT, in brcmnand_dma_run()
2030 (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC_EXT); in brcmnand_dma_run()
2034 ctrl->dma_pending = true; in brcmnand_dma_run()
2036 flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0x03); /* wake | run */ in brcmnand_dma_run()
2038 if (wait_for_completion_timeout(&ctrl->dma_done, timeo) <= 0) { in brcmnand_dma_run()
2039 dev_err(ctrl->dev, in brcmnand_dma_run()
2041 flash_dma_readl(ctrl, FLASH_DMA_STATUS), in brcmnand_dma_run()
2042 flash_dma_readl(ctrl, FLASH_DMA_ERROR_STATUS)); in brcmnand_dma_run()
2044 ctrl->dma_pending = false; in brcmnand_dma_run()
2045 flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0); /* force stop */ in brcmnand_dma_run()
2051 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_dma_trans() local
2055 buf_pa = dma_map_single(ctrl->dev, buf, len, dir); in brcmnand_dma_trans()
2056 if (dma_mapping_error(ctrl->dev, buf_pa)) { in brcmnand_dma_trans()
2057 dev_err(ctrl->dev, "unable to map buffer for DMA\n"); in brcmnand_dma_trans()
2061 brcmnand_fill_dma_desc(host, ctrl->dma_desc, addr, buf_pa, len, in brcmnand_dma_trans()
2064 brcmnand_dma_run(host, ctrl->dma_pa); in brcmnand_dma_trans()
2066 dma_unmap_single(ctrl->dev, buf_pa, len, dir); in brcmnand_dma_trans()
2068 if (ctrl->dma_desc->status_valid & FLASH_DMA_ECC_ERROR) in brcmnand_dma_trans()
2070 else if (ctrl->dma_desc->status_valid & FLASH_DMA_CORR_ERROR) in brcmnand_dma_trans()
2084 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_read_by_pio() local
2087 brcmnand_clear_ecc_addr(ctrl); in brcmnand_read_by_pio()
2096 brcmnand_soc_data_bus_prepare(ctrl->soc, false); in brcmnand_read_by_pio()
2099 *buf = brcmnand_read_fc(ctrl, j); in brcmnand_read_by_pio()
2101 brcmnand_soc_data_bus_unprepare(ctrl->soc, false); in brcmnand_read_by_pio()
2105 oob += read_oob_from_regs(ctrl, i, oob, in brcmnand_read_by_pio()
2110 *err_addr = brcmnand_get_uncorrecc_addr(ctrl); in brcmnand_read_by_pio()
2117 *err_addr = brcmnand_get_correcc_addr(ctrl); in brcmnand_read_by_pio()
2183 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_read() local
2189 dev_dbg(ctrl->dev, "read %llx -> %p\n", (unsigned long long)addr, buf); in brcmnand_read()
2192 brcmnand_clear_ecc_addr(ctrl); in brcmnand_read()
2194 if (ctrl->dma_trans && (has_edu(ctrl) || !oob) && in brcmnand_read()
2196 err = ctrl->dma_trans(host, addr, buf, oob, in brcmnand_read()
2207 if (has_edu(ctrl) && err_addr) in brcmnand_read()
2227 if ((ctrl->nand_version == 0x0700) || in brcmnand_read()
2228 (ctrl->nand_version == 0x0701)) { in brcmnand_read()
2239 if (ctrl->nand_version < 0x0702) { in brcmnand_read()
2247 dev_dbg(ctrl->dev, "uncorrectable error at 0x%llx\n", in brcmnand_read()
2255 unsigned int corrected = brcmnand_count_corrected(ctrl); in brcmnand_read()
2262 dev_dbg(ctrl->dev, "corrected error at 0x%llx\n", in brcmnand_read()
2328 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_write() local
2332 dev_dbg(ctrl->dev, "write %llx <- %p\n", (unsigned long long)addr, buf); in brcmnand_write()
2335 dev_warn(ctrl->dev, "unaligned buffer: %p\n", buf); in brcmnand_write()
2341 for (i = 0; i < ctrl->max_oob; i += 4) in brcmnand_write()
2342 oob_reg_write(ctrl, i, 0xffffffff); in brcmnand_write()
2346 disable_ctrl_irqs(ctrl); in brcmnand_write()
2348 if (use_dma(ctrl) && (has_edu(ctrl) || !oob) && flash_dma_buf_ok(buf)) { in brcmnand_write()
2349 if (ctrl->dma_trans(host, addr, (u32 *)buf, oob, mtd->writesize, in brcmnand_write()
2362 brcmnand_soc_data_bus_prepare(ctrl->soc, false); in brcmnand_write()
2365 brcmnand_write_fc(ctrl, j, *buf); in brcmnand_write()
2367 brcmnand_soc_data_bus_unprepare(ctrl->soc, false); in brcmnand_write()
2370 brcmnand_write_fc(ctrl, j, 0xffffffff); in brcmnand_write()
2374 oob += write_oob_to_regs(ctrl, i, oob, in brcmnand_write()
2384 dev_info(ctrl->dev, "program failed at %llx\n", in brcmnand_write()
2451 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_set_cfg() local
2453 u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG); in brcmnand_set_cfg()
2454 u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs, in brcmnand_set_cfg()
2456 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, in brcmnand_set_cfg()
2461 if (ctrl->block_sizes) { in brcmnand_set_cfg()
2464 for (i = 0, found = 0; ctrl->block_sizes[i]; i++) in brcmnand_set_cfg()
2465 if (ctrl->block_sizes[i] * 1024 == cfg->block_size) { in brcmnand_set_cfg()
2470 dev_warn(ctrl->dev, "invalid block size %u\n", in brcmnand_set_cfg()
2478 if (cfg->block_size < BRCMNAND_MIN_BLOCKSIZE || (ctrl->max_block_size && in brcmnand_set_cfg()
2479 cfg->block_size > ctrl->max_block_size)) { in brcmnand_set_cfg()
2480 dev_warn(ctrl->dev, "invalid block size %u\n", in brcmnand_set_cfg()
2485 if (ctrl->page_sizes) { in brcmnand_set_cfg()
2488 for (i = 0, found = 0; ctrl->page_sizes[i]; i++) in brcmnand_set_cfg()
2489 if (ctrl->page_sizes[i] == cfg->page_size) { in brcmnand_set_cfg()
2494 dev_warn(ctrl->dev, "invalid page size %u\n", in brcmnand_set_cfg()
2502 if (cfg->page_size < BRCMNAND_MIN_PAGESIZE || (ctrl->max_page_size && in brcmnand_set_cfg()
2503 cfg->page_size > ctrl->max_page_size)) { in brcmnand_set_cfg()
2504 dev_warn(ctrl->dev, "invalid page size %u\n", cfg->page_size); in brcmnand_set_cfg()
2509 dev_warn(ctrl->dev, "invalid device size 0x%llx\n", in brcmnand_set_cfg()
2521 tmp |= (page_size << ctrl->page_size_shift) | in brcmnand_set_cfg()
2523 nand_writereg(ctrl, cfg_offs, tmp); in brcmnand_set_cfg()
2525 nand_writereg(ctrl, cfg_offs, tmp); in brcmnand_set_cfg()
2528 nand_writereg(ctrl, cfg_ext_offs, tmp); in brcmnand_set_cfg()
2531 tmp = nand_readreg(ctrl, acc_control_offs); in brcmnand_set_cfg()
2532 tmp &= ~brcmnand_ecc_level_mask(ctrl); in brcmnand_set_cfg()
2533 tmp &= ~brcmnand_spare_area_mask(ctrl); in brcmnand_set_cfg()
2534 if (ctrl->nand_version >= 0x0302) { in brcmnand_set_cfg()
2538 nand_writereg(ctrl, acc_control_offs, tmp); in brcmnand_set_cfg()
2560 if (is_hamming_ecc(host->ctrl, cfg)) in brcmnand_print_cfg()
2586 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_setup_dev() local
2604 if (cfg->spare_area_size > ctrl->max_oob) in brcmnand_setup_dev()
2605 cfg->spare_area_size = ctrl->max_oob; in brcmnand_setup_dev()
2620 dev_err(ctrl->dev, "only HW ECC supported; selected: %d\n", in brcmnand_setup_dev()
2636 dev_err(ctrl->dev, "invalid Hamming params: %d bits per %d bytes\n", in brcmnand_setup_dev()
2647 dev_info(ctrl->dev, "Using ECC step-size %d, strength %d\n", in brcmnand_setup_dev()
2661 if (!(ctrl->features & BRCMNAND_HAS_1K_SECTORS)) { in brcmnand_setup_dev()
2662 dev_err(ctrl->dev, "1KB sectors not supported\n"); in brcmnand_setup_dev()
2666 dev_err(ctrl->dev, in brcmnand_setup_dev()
2675 dev_err(ctrl->dev, "unsupported ECC size: %d\n", in brcmnand_setup_dev()
2693 dev_info(ctrl->dev, "detected %s\n", msg); in brcmnand_setup_dev()
2696 offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL); in brcmnand_setup_dev()
2697 tmp = nand_readreg(ctrl, offs); in brcmnand_setup_dev()
2702 if (ctrl->nand_version >= 0x0702) in brcmnand_setup_dev()
2705 if (ctrl->features & BRCMNAND_HAS_PREFETCH) in brcmnand_setup_dev()
2708 nand_writereg(ctrl, offs, tmp); in brcmnand_setup_dev()
2741 if (is_hamming_ecc(host->ctrl, &host->hwcfg)) { in brcmnand_attach_chip()
2755 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_init_cs() local
2798 chip->controller = &ctrl->controller; in brcmnand_init_cs()
2805 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG); in brcmnand_init_cs()
2806 nand_writereg(ctrl, cfg_offs, in brcmnand_init_cs()
2807 nand_readreg(ctrl, cfg_offs) & ~CFG_BUS_WIDTH); in brcmnand_init_cs()
2823 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_save_restore_cs_config() local
2824 u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG); in brcmnand_save_restore_cs_config()
2825 u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs, in brcmnand_save_restore_cs_config()
2827 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, in brcmnand_save_restore_cs_config()
2829 u16 t1_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING1); in brcmnand_save_restore_cs_config()
2830 u16 t2_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING2); in brcmnand_save_restore_cs_config()
2833 nand_writereg(ctrl, cfg_offs, host->hwcfg.config); in brcmnand_save_restore_cs_config()
2835 nand_writereg(ctrl, cfg_ext_offs, in brcmnand_save_restore_cs_config()
2837 nand_writereg(ctrl, acc_control_offs, host->hwcfg.acc_control); in brcmnand_save_restore_cs_config()
2838 nand_writereg(ctrl, t1_offs, host->hwcfg.timing_1); in brcmnand_save_restore_cs_config()
2839 nand_writereg(ctrl, t2_offs, host->hwcfg.timing_2); in brcmnand_save_restore_cs_config()
2841 host->hwcfg.config = nand_readreg(ctrl, cfg_offs); in brcmnand_save_restore_cs_config()
2844 nand_readreg(ctrl, cfg_ext_offs); in brcmnand_save_restore_cs_config()
2845 host->hwcfg.acc_control = nand_readreg(ctrl, acc_control_offs); in brcmnand_save_restore_cs_config()
2846 host->hwcfg.timing_1 = nand_readreg(ctrl, t1_offs); in brcmnand_save_restore_cs_config()
2847 host->hwcfg.timing_2 = nand_readreg(ctrl, t2_offs); in brcmnand_save_restore_cs_config()
2853 struct brcmnand_controller *ctrl = dev_get_drvdata(dev); in brcmnand_suspend() local
2856 list_for_each_entry(host, &ctrl->host_list, node) in brcmnand_suspend()
2859 ctrl->nand_cs_nand_select = brcmnand_read_reg(ctrl, BRCMNAND_CS_SELECT); in brcmnand_suspend()
2860 ctrl->nand_cs_nand_xor = brcmnand_read_reg(ctrl, BRCMNAND_CS_XOR); in brcmnand_suspend()
2861 ctrl->corr_stat_threshold = in brcmnand_suspend()
2862 brcmnand_read_reg(ctrl, BRCMNAND_CORR_THRESHOLD); in brcmnand_suspend()
2864 if (has_flash_dma(ctrl)) in brcmnand_suspend()
2865 ctrl->flash_dma_mode = flash_dma_readl(ctrl, FLASH_DMA_MODE); in brcmnand_suspend()
2866 else if (has_edu(ctrl)) in brcmnand_suspend()
2867 ctrl->edu_config = edu_readl(ctrl, EDU_CONFIG); in brcmnand_suspend()
2874 struct brcmnand_controller *ctrl = dev_get_drvdata(dev); in brcmnand_resume() local
2877 if (has_flash_dma(ctrl)) { in brcmnand_resume()
2878 flash_dma_writel(ctrl, FLASH_DMA_MODE, ctrl->flash_dma_mode); in brcmnand_resume()
2879 flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0); in brcmnand_resume()
2882 if (has_edu(ctrl)) { in brcmnand_resume()
2883 ctrl->edu_config = edu_readl(ctrl, EDU_CONFIG); in brcmnand_resume()
2884 edu_writel(ctrl, EDU_CONFIG, ctrl->edu_config); in brcmnand_resume()
2885 edu_readl(ctrl, EDU_CONFIG); in brcmnand_resume()
2886 brcmnand_edu_init(ctrl); in brcmnand_resume()
2889 brcmnand_write_reg(ctrl, BRCMNAND_CS_SELECT, ctrl->nand_cs_nand_select); in brcmnand_resume()
2890 brcmnand_write_reg(ctrl, BRCMNAND_CS_XOR, ctrl->nand_cs_nand_xor); in brcmnand_resume()
2891 brcmnand_write_reg(ctrl, BRCMNAND_CORR_THRESHOLD, in brcmnand_resume()
2892 ctrl->corr_stat_threshold); in brcmnand_resume()
2893 if (ctrl->soc) { in brcmnand_resume()
2895 ctrl->soc->ctlrdy_ack(ctrl->soc); in brcmnand_resume()
2896 ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true); in brcmnand_resume()
2899 list_for_each_entry(host, &ctrl->host_list, node) { in brcmnand_resume()
2939 struct brcmnand_controller *ctrl = dev_get_drvdata(&pdev->dev); in brcmnand_edu_setup() local
2945 ctrl->edu_base = devm_ioremap_resource(dev, res); in brcmnand_edu_setup()
2946 if (IS_ERR(ctrl->edu_base)) in brcmnand_edu_setup()
2947 return PTR_ERR(ctrl->edu_base); in brcmnand_edu_setup()
2949 ctrl->edu_offsets = edu_regs; in brcmnand_edu_setup()
2951 edu_writel(ctrl, EDU_CONFIG, EDU_CONFIG_MODE_NAND | in brcmnand_edu_setup()
2953 edu_readl(ctrl, EDU_CONFIG); in brcmnand_edu_setup()
2956 brcmnand_edu_init(ctrl); in brcmnand_edu_setup()
2958 ctrl->edu_irq = platform_get_irq_optional(pdev, 1); in brcmnand_edu_setup()
2959 if (ctrl->edu_irq < 0) { in brcmnand_edu_setup()
2963 ret = devm_request_irq(dev, ctrl->edu_irq, in brcmnand_edu_setup()
2965 "brcmnand-edu", ctrl); in brcmnand_edu_setup()
2967 dev_err(ctrl->dev, "can't allocate IRQ %d: error %d\n", in brcmnand_edu_setup()
2968 ctrl->edu_irq, ret); in brcmnand_edu_setup()
2973 ctrl->edu_irq); in brcmnand_edu_setup()
2984 struct brcmnand_controller *ctrl; in brcmnand_probe() local
2995 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); in brcmnand_probe()
2996 if (!ctrl) in brcmnand_probe()
2999 dev_set_drvdata(dev, ctrl); in brcmnand_probe()
3000 ctrl->dev = dev; in brcmnand_probe()
3002 init_completion(&ctrl->done); in brcmnand_probe()
3003 init_completion(&ctrl->dma_done); in brcmnand_probe()
3004 init_completion(&ctrl->edu_done); in brcmnand_probe()
3005 nand_controller_init(&ctrl->controller); in brcmnand_probe()
3006 ctrl->controller.ops = &brcmnand_controller_ops; in brcmnand_probe()
3007 INIT_LIST_HEAD(&ctrl->host_list); in brcmnand_probe()
3011 ctrl->nand_base = devm_ioremap_resource(dev, res); in brcmnand_probe()
3012 if (IS_ERR(ctrl->nand_base)) in brcmnand_probe()
3013 return PTR_ERR(ctrl->nand_base); in brcmnand_probe()
3016 ctrl->clk = devm_clk_get(dev, "nand"); in brcmnand_probe()
3017 if (!IS_ERR(ctrl->clk)) { in brcmnand_probe()
3018 ret = clk_prepare_enable(ctrl->clk); in brcmnand_probe()
3022 ret = PTR_ERR(ctrl->clk); in brcmnand_probe()
3026 ctrl->clk = NULL; in brcmnand_probe()
3030 ret = brcmnand_revision_init(ctrl); in brcmnand_probe()
3040 ctrl->nand_fc = devm_ioremap_resource(dev, res); in brcmnand_probe()
3041 if (IS_ERR(ctrl->nand_fc)) { in brcmnand_probe()
3042 ret = PTR_ERR(ctrl->nand_fc); in brcmnand_probe()
3046 ctrl->nand_fc = ctrl->nand_base + in brcmnand_probe()
3047 ctrl->reg_offsets[BRCMNAND_FC_BASE]; in brcmnand_probe()
3053 ctrl->flash_dma_base = devm_ioremap_resource(dev, res); in brcmnand_probe()
3054 if (IS_ERR(ctrl->flash_dma_base)) { in brcmnand_probe()
3055 ret = PTR_ERR(ctrl->flash_dma_base); in brcmnand_probe()
3060 brcmnand_flash_dma_revision_init(ctrl); in brcmnand_probe()
3063 if (ctrl->nand_version >= 0x0700) in brcmnand_probe()
3073 flash_dma_writel(ctrl, FLASH_DMA_MODE, FLASH_DMA_MODE_MASK); in brcmnand_probe()
3074 flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0); in brcmnand_probe()
3077 ctrl->dma_desc = dmam_alloc_coherent(dev, in brcmnand_probe()
3078 sizeof(*ctrl->dma_desc), in brcmnand_probe()
3079 &ctrl->dma_pa, GFP_KERNEL); in brcmnand_probe()
3080 if (!ctrl->dma_desc) { in brcmnand_probe()
3085 ctrl->dma_irq = platform_get_irq(pdev, 1); in brcmnand_probe()
3086 if ((int)ctrl->dma_irq < 0) { in brcmnand_probe()
3092 ret = devm_request_irq(dev, ctrl->dma_irq, in brcmnand_probe()
3094 ctrl); in brcmnand_probe()
3097 ctrl->dma_irq, ret); in brcmnand_probe()
3103 ctrl->dma_trans = brcmnand_dma_trans; in brcmnand_probe()
3109 if (has_edu(ctrl)) in brcmnand_probe()
3111 ctrl->dma_trans = brcmnand_edu_trans; in brcmnand_probe()
3115 brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT, in brcmnand_probe()
3118 brcmnand_rmw_reg(ctrl, BRCMNAND_CS_XOR, 0xff, 0, 0); in brcmnand_probe()
3120 if (ctrl->features & BRCMNAND_HAS_WP) { in brcmnand_probe()
3123 brcmnand_set_wp(ctrl, false); in brcmnand_probe()
3129 ctrl->irq = platform_get_irq(pdev, 0); in brcmnand_probe()
3130 if ((int)ctrl->irq < 0) { in brcmnand_probe()
3141 ctrl->soc = soc; in brcmnand_probe()
3143 ret = devm_request_irq(dev, ctrl->irq, brcmnand_irq, 0, in brcmnand_probe()
3144 DRV_NAME, ctrl); in brcmnand_probe()
3147 ctrl->soc->ctlrdy_ack(ctrl->soc); in brcmnand_probe()
3148 ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true); in brcmnand_probe()
3151 ret = devm_request_irq(dev, ctrl->irq, brcmnand_ctlrdy_irq, 0, in brcmnand_probe()
3152 DRV_NAME, ctrl); in brcmnand_probe()
3156 ctrl->irq, ret); in brcmnand_probe()
3171 host->ctrl = ctrl; in brcmnand_probe()
3179 list_add_tail(&host->node, &ctrl->host_list); in brcmnand_probe()
3184 if (list_empty(&ctrl->host_list)) { in brcmnand_probe()
3192 clk_disable_unprepare(ctrl->clk); in brcmnand_probe()
3200 struct brcmnand_controller *ctrl = dev_get_drvdata(&pdev->dev); in brcmnand_remove() local
3205 list_for_each_entry(host, &ctrl->host_list, node) { in brcmnand_remove()
3212 clk_disable_unprepare(ctrl->clk); in brcmnand_remove()