Lines Matching +full:nand +full:- +full:rb
1 // SPDX-License-Identifier: GPL-2.0
6 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
13 * Derived from drivers/mtd/nand/autcpu12.c (removed in v3.8)
23 * Derived from Das U-Boot source code
24 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
30 * Add Nand Flash Controller support for SAMA5 SoC
38 * - atmel_nand_: all generic structures/functions
39 * - atmel_smc_nand_: all structures/functions specific to the SMC interface
41 * - atmel_hsmc_nand_: all structures/functions specific to the HSMC interface
43 * - atmel_nfc_: all structures/functions used to manipulate the NFC sub-block
45 * - <soc>_nand_: all SoC specific structures/functions
49 #include <linux/dma-mapping.h>
55 #include <linux/mfd/syscon/atmel-matrix.h>
56 #include <linux/mfd/syscon/atmel-smc.h>
65 #include <soc/at91/atmel-sfr.h>
79 #define ATMEL_HSMC_NFC_CFG_PAGESIZE(x) (fls((x) / 512) - 1)
150 struct atmel_nand_rb rb; member
201 struct atmel_nand *nand);
203 int (*setup_interface)(struct atmel_nand *nand, int csline,
205 int (*exec_op)(struct atmel_nand *nand,
280 op->errors |= status & ATMEL_HSMC_NFC_SR_ERRORS; in atmel_nfc_op_done()
281 op->wait ^= status & op->wait; in atmel_nfc_op_done()
283 return !op->wait || op->errors; in atmel_nfc_op_done()
292 regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &sr); in atmel_nfc_interrupt()
294 rcvd = sr & (nc->op.wait | ATMEL_HSMC_NFC_SR_ERRORS); in atmel_nfc_interrupt()
295 done = atmel_nfc_op_done(&nc->op, sr); in atmel_nfc_interrupt()
298 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, rcvd); in atmel_nfc_interrupt()
301 complete(&nc->complete); in atmel_nfc_interrupt()
317 ret = regmap_read_poll_timeout(nc->base.smc, in atmel_nfc_wait()
319 atmel_nfc_op_done(&nc->op, in atmel_nfc_wait()
323 init_completion(&nc->complete); in atmel_nfc_wait()
324 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IER, in atmel_nfc_wait()
325 nc->op.wait | ATMEL_HSMC_NFC_SR_ERRORS); in atmel_nfc_wait()
326 ret = wait_for_completion_timeout(&nc->complete, in atmel_nfc_wait()
329 ret = -ETIMEDOUT; in atmel_nfc_wait()
333 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, 0xffffffff); in atmel_nfc_wait()
336 if (nc->op.errors & ATMEL_HSMC_NFC_SR_DTOE) { in atmel_nfc_wait()
337 dev_err(nc->base.dev, "Waiting NAND R/B Timeout\n"); in atmel_nfc_wait()
338 ret = -ETIMEDOUT; in atmel_nfc_wait()
341 if (nc->op.errors & ATMEL_HSMC_NFC_SR_UNDEF) { in atmel_nfc_wait()
342 dev_err(nc->base.dev, "Access to an undefined area\n"); in atmel_nfc_wait()
343 ret = -EIO; in atmel_nfc_wait()
346 if (nc->op.errors & ATMEL_HSMC_NFC_SR_AWB) { in atmel_nfc_wait()
347 dev_err(nc->base.dev, "Access while busy\n"); in atmel_nfc_wait()
348 ret = -EIO; in atmel_nfc_wait()
351 if (nc->op.errors & ATMEL_HSMC_NFC_SR_NFCASE) { in atmel_nfc_wait()
352 dev_err(nc->base.dev, "Wrong access size\n"); in atmel_nfc_wait()
353 ret = -EIO; in atmel_nfc_wait()
375 buf_dma = dma_map_single(nc->dev, buf, len, dir); in atmel_nand_dma_transfer()
376 if (dma_mapping_error(nc->dev, dev_dma)) { in atmel_nand_dma_transfer()
377 dev_err(nc->dev, in atmel_nand_dma_transfer()
390 tx = dmaengine_prep_dma_memcpy(nc->dmac, dst_dma, src_dma, len, in atmel_nand_dma_transfer()
393 dev_err(nc->dev, "Failed to prepare DMA memcpy\n"); in atmel_nand_dma_transfer()
397 tx->callback = atmel_nand_dma_transfer_finished; in atmel_nand_dma_transfer()
398 tx->callback_param = &finished; in atmel_nand_dma_transfer()
402 dev_err(nc->dev, "Failed to do DMA tx_submit\n"); in atmel_nand_dma_transfer()
406 dma_async_issue_pending(nc->dmac); in atmel_nand_dma_transfer()
412 dma_unmap_single(nc->dev, buf_dma, len, dir); in atmel_nand_dma_transfer()
415 dev_dbg(nc->dev, "Fall back to CPU I/O\n"); in atmel_nand_dma_transfer()
417 return -EIO; in atmel_nand_dma_transfer()
422 u8 *addrs = nc->op.addrs; in atmel_nfc_exec_op()
427 nc->op.wait = ATMEL_HSMC_NFC_SR_CMDDONE; in atmel_nfc_exec_op()
429 for (i = 0; i < nc->op.ncmds; i++) in atmel_nfc_exec_op()
430 op |= ATMEL_NFC_CMD(i, nc->op.cmds[i]); in atmel_nfc_exec_op()
432 if (nc->op.naddrs == ATMEL_NFC_MAX_ADDR_CYCLES) in atmel_nfc_exec_op()
433 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_ADDR, *addrs++); in atmel_nfc_exec_op()
435 op |= ATMEL_NFC_CSID(nc->op.cs) | in atmel_nfc_exec_op()
436 ATMEL_NFC_ACYCLE(nc->op.naddrs); in atmel_nfc_exec_op()
438 if (nc->op.ncmds > 1) in atmel_nfc_exec_op()
444 if (nc->op.data != ATMEL_NFC_NO_DATA) { in atmel_nfc_exec_op()
446 nc->op.wait |= ATMEL_HSMC_NFC_SR_XFRDONE; in atmel_nfc_exec_op()
448 if (nc->op.data == ATMEL_NFC_WRITE_DATA) in atmel_nfc_exec_op()
453 regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &val); in atmel_nfc_exec_op()
456 regmap_write(nc->io, op, addr); in atmel_nfc_exec_op()
460 dev_err(nc->base.dev, in atmel_nfc_exec_op()
461 "Failed to send NAND command (err = %d)!", in atmel_nfc_exec_op()
465 memset(&nc->op, 0, sizeof(nc->op)); in atmel_nfc_exec_op()
470 static void atmel_nand_data_in(struct atmel_nand *nand, void *buf, in atmel_nand_data_in() argument
475 nc = to_nand_controller(nand->base.controller); in atmel_nand_data_in()
478 * If the controller supports DMA, the buffer address is DMA-able and in atmel_nand_data_in()
482 if (nc->dmac && virt_addr_valid(buf) && in atmel_nand_data_in()
484 !atmel_nand_dma_transfer(nc, buf, nand->activecs->io.dma, len, in atmel_nand_data_in()
488 if ((nand->base.options & NAND_BUSWIDTH_16) && !force_8bit) in atmel_nand_data_in()
489 ioread16_rep(nand->activecs->io.virt, buf, len / 2); in atmel_nand_data_in()
491 ioread8_rep(nand->activecs->io.virt, buf, len); in atmel_nand_data_in()
494 static void atmel_nand_data_out(struct atmel_nand *nand, const void *buf, in atmel_nand_data_out() argument
499 nc = to_nand_controller(nand->base.controller); in atmel_nand_data_out()
502 * If the controller supports DMA, the buffer address is DMA-able and in atmel_nand_data_out()
506 if (nc->dmac && virt_addr_valid(buf) && in atmel_nand_data_out()
508 !atmel_nand_dma_transfer(nc, (void *)buf, nand->activecs->io.dma, in atmel_nand_data_out()
512 if ((nand->base.options & NAND_BUSWIDTH_16) && !force_8bit) in atmel_nand_data_out()
513 iowrite16_rep(nand->activecs->io.virt, buf, len / 2); in atmel_nand_data_out()
515 iowrite8_rep(nand->activecs->io.virt, buf, len); in atmel_nand_data_out()
518 static int atmel_nand_waitrdy(struct atmel_nand *nand, unsigned int timeout_ms) in atmel_nand_waitrdy() argument
520 if (nand->activecs->rb.type == ATMEL_NAND_NO_RB) in atmel_nand_waitrdy()
521 return nand_soft_waitrdy(&nand->base, timeout_ms); in atmel_nand_waitrdy()
523 return nand_gpio_waitrdy(&nand->base, nand->activecs->rb.gpio, in atmel_nand_waitrdy()
527 static int atmel_hsmc_nand_waitrdy(struct atmel_nand *nand, in atmel_hsmc_nand_waitrdy() argument
533 if (nand->activecs->rb.type != ATMEL_NAND_NATIVE_RB) in atmel_hsmc_nand_waitrdy()
534 return atmel_nand_waitrdy(nand, timeout_ms); in atmel_hsmc_nand_waitrdy()
536 nc = to_hsmc_nand_controller(nand->base.controller); in atmel_hsmc_nand_waitrdy()
537 mask = ATMEL_HSMC_NFC_SR_RBEDGE(nand->activecs->rb.id); in atmel_hsmc_nand_waitrdy()
538 return regmap_read_poll_timeout_atomic(nc->base.smc, ATMEL_HSMC_NFC_SR, in atmel_hsmc_nand_waitrdy()
543 static void atmel_nand_select_target(struct atmel_nand *nand, in atmel_nand_select_target() argument
546 nand->activecs = &nand->cs[cs]; in atmel_nand_select_target()
549 static void atmel_hsmc_nand_select_target(struct atmel_nand *nand, in atmel_hsmc_nand_select_target() argument
552 struct mtd_info *mtd = nand_to_mtd(&nand->base); in atmel_hsmc_nand_select_target()
554 u32 cfg = ATMEL_HSMC_NFC_CFG_PAGESIZE(mtd->writesize) | in atmel_hsmc_nand_select_target()
555 ATMEL_HSMC_NFC_CFG_SPARESIZE(mtd->oobsize) | in atmel_hsmc_nand_select_target()
558 nand->activecs = &nand->cs[cs]; in atmel_hsmc_nand_select_target()
559 nc = to_hsmc_nand_controller(nand->base.controller); in atmel_hsmc_nand_select_target()
560 if (nc->cfg == cfg) in atmel_hsmc_nand_select_target()
563 regmap_update_bits(nc->base.smc, ATMEL_HSMC_NFC_CFG, in atmel_hsmc_nand_select_target()
569 nc->cfg = cfg; in atmel_hsmc_nand_select_target()
572 static int atmel_smc_nand_exec_instr(struct atmel_nand *nand, in atmel_smc_nand_exec_instr() argument
578 nc = to_nand_controller(nand->base.controller); in atmel_smc_nand_exec_instr()
579 switch (instr->type) { in atmel_smc_nand_exec_instr()
581 writeb(instr->ctx.cmd.opcode, in atmel_smc_nand_exec_instr()
582 nand->activecs->io.virt + nc->caps->cle_offs); in atmel_smc_nand_exec_instr()
585 for (i = 0; i < instr->ctx.addr.naddrs; i++) in atmel_smc_nand_exec_instr()
586 writeb(instr->ctx.addr.addrs[i], in atmel_smc_nand_exec_instr()
587 nand->activecs->io.virt + nc->caps->ale_offs); in atmel_smc_nand_exec_instr()
590 atmel_nand_data_in(nand, instr->ctx.data.buf.in, in atmel_smc_nand_exec_instr()
591 instr->ctx.data.len, in atmel_smc_nand_exec_instr()
592 instr->ctx.data.force_8bit); in atmel_smc_nand_exec_instr()
595 atmel_nand_data_out(nand, instr->ctx.data.buf.out, in atmel_smc_nand_exec_instr()
596 instr->ctx.data.len, in atmel_smc_nand_exec_instr()
597 instr->ctx.data.force_8bit); in atmel_smc_nand_exec_instr()
600 return atmel_nand_waitrdy(nand, in atmel_smc_nand_exec_instr()
601 instr->ctx.waitrdy.timeout_ms); in atmel_smc_nand_exec_instr()
606 return -EINVAL; in atmel_smc_nand_exec_instr()
609 static int atmel_smc_nand_exec_op(struct atmel_nand *nand, in atmel_smc_nand_exec_op() argument
619 atmel_nand_select_target(nand, op->cs); in atmel_smc_nand_exec_op()
620 gpiod_set_value(nand->activecs->csgpio, 0); in atmel_smc_nand_exec_op()
621 for (i = 0; i < op->ninstrs; i++) { in atmel_smc_nand_exec_op()
622 ret = atmel_smc_nand_exec_instr(nand, &op->instrs[i]); in atmel_smc_nand_exec_op()
626 gpiod_set_value(nand->activecs->csgpio, 1); in atmel_smc_nand_exec_op()
634 struct atmel_nand *nand = to_atmel_nand(chip); in atmel_hsmc_exec_cmd_addr() local
638 nc = to_hsmc_nand_controller(chip->controller); in atmel_hsmc_exec_cmd_addr()
640 nc->op.cs = nand->activecs->id; in atmel_hsmc_exec_cmd_addr()
641 for (i = 0; i < subop->ninstrs; i++) { in atmel_hsmc_exec_cmd_addr()
642 const struct nand_op_instr *instr = &subop->instrs[i]; in atmel_hsmc_exec_cmd_addr()
644 if (instr->type == NAND_OP_CMD_INSTR) { in atmel_hsmc_exec_cmd_addr()
645 nc->op.cmds[nc->op.ncmds++] = instr->ctx.cmd.opcode; in atmel_hsmc_exec_cmd_addr()
651 nc->op.addrs[nc->op.naddrs] = instr->ctx.addr.addrs[j]; in atmel_hsmc_exec_cmd_addr()
652 nc->op.naddrs++; in atmel_hsmc_exec_cmd_addr()
662 const struct nand_op_instr *instr = subop->instrs; in atmel_hsmc_exec_rw()
663 struct atmel_nand *nand = to_atmel_nand(chip); in atmel_hsmc_exec_rw() local
665 if (instr->type == NAND_OP_DATA_IN_INSTR) in atmel_hsmc_exec_rw()
666 atmel_nand_data_in(nand, instr->ctx.data.buf.in, in atmel_hsmc_exec_rw()
667 instr->ctx.data.len, in atmel_hsmc_exec_rw()
668 instr->ctx.data.force_8bit); in atmel_hsmc_exec_rw()
670 atmel_nand_data_out(nand, instr->ctx.data.buf.out, in atmel_hsmc_exec_rw()
671 instr->ctx.data.len, in atmel_hsmc_exec_rw()
672 instr->ctx.data.force_8bit); in atmel_hsmc_exec_rw()
680 const struct nand_op_instr *instr = subop->instrs; in atmel_hsmc_exec_waitrdy()
681 struct atmel_nand *nand = to_atmel_nand(chip); in atmel_hsmc_exec_waitrdy() local
683 return atmel_hsmc_nand_waitrdy(nand, instr->ctx.waitrdy.timeout_ms); in atmel_hsmc_exec_waitrdy()
699 static int atmel_hsmc_nand_exec_op(struct atmel_nand *nand, in atmel_hsmc_nand_exec_op() argument
706 return nand_op_parser_exec_op(&nand->base, in atmel_hsmc_nand_exec_op()
709 atmel_hsmc_nand_select_target(nand, op->cs); in atmel_hsmc_nand_exec_op()
710 ret = nand_op_parser_exec_op(&nand->base, &atmel_hsmc_op_parser, op, in atmel_hsmc_nand_exec_op()
721 int ret = -EIO; in atmel_nfc_copy_to_sram()
723 nc = to_hsmc_nand_controller(chip->controller); in atmel_nfc_copy_to_sram()
725 if (nc->base.dmac) in atmel_nfc_copy_to_sram()
726 ret = atmel_nand_dma_transfer(&nc->base, (void *)buf, in atmel_nfc_copy_to_sram()
727 nc->sram.dma, mtd->writesize, in atmel_nfc_copy_to_sram()
732 memcpy_toio(nc->sram.virt, buf, mtd->writesize); in atmel_nfc_copy_to_sram()
735 memcpy_toio(nc->sram.virt + mtd->writesize, chip->oob_poi, in atmel_nfc_copy_to_sram()
736 mtd->oobsize); in atmel_nfc_copy_to_sram()
744 int ret = -EIO; in atmel_nfc_copy_from_sram()
746 nc = to_hsmc_nand_controller(chip->controller); in atmel_nfc_copy_from_sram()
748 if (nc->base.dmac) in atmel_nfc_copy_from_sram()
749 ret = atmel_nand_dma_transfer(&nc->base, buf, nc->sram.dma, in atmel_nfc_copy_from_sram()
750 mtd->writesize, DMA_FROM_DEVICE); in atmel_nfc_copy_from_sram()
754 memcpy_fromio(buf, nc->sram.virt, mtd->writesize); in atmel_nfc_copy_from_sram()
757 memcpy_fromio(chip->oob_poi, nc->sram.virt + mtd->writesize, in atmel_nfc_copy_from_sram()
758 mtd->oobsize); in atmel_nfc_copy_from_sram()
766 nc = to_hsmc_nand_controller(chip->controller); in atmel_nfc_set_op_addr()
769 nc->op.addrs[nc->op.naddrs++] = column; in atmel_nfc_set_op_addr()
774 if (mtd->writesize > 512) in atmel_nfc_set_op_addr()
775 nc->op.addrs[nc->op.naddrs++] = column >> 8; in atmel_nfc_set_op_addr()
779 nc->op.addrs[nc->op.naddrs++] = page; in atmel_nfc_set_op_addr()
780 nc->op.addrs[nc->op.naddrs++] = page >> 8; in atmel_nfc_set_op_addr()
782 if (chip->options & NAND_ROW_ADDR_3) in atmel_nfc_set_op_addr()
783 nc->op.addrs[nc->op.naddrs++] = page >> 16; in atmel_nfc_set_op_addr()
789 struct atmel_nand *nand = to_atmel_nand(chip); in atmel_nand_pmecc_enable() local
793 nc = to_nand_controller(chip->controller); in atmel_nand_pmecc_enable()
798 ret = atmel_pmecc_enable(nand->pmecc, op); in atmel_nand_pmecc_enable()
800 dev_err(nc->dev, in atmel_nand_pmecc_enable()
808 struct atmel_nand *nand = to_atmel_nand(chip); in atmel_nand_pmecc_disable() local
811 atmel_pmecc_disable(nand->pmecc); in atmel_nand_pmecc_disable()
816 struct atmel_nand *nand = to_atmel_nand(chip); in atmel_nand_pmecc_generate_eccbytes() local
823 nc = to_nand_controller(chip->controller); in atmel_nand_pmecc_generate_eccbytes()
828 ret = atmel_pmecc_wait_rdy(nand->pmecc); in atmel_nand_pmecc_generate_eccbytes()
830 dev_err(nc->dev, in atmel_nand_pmecc_generate_eccbytes()
831 "Failed to transfer NAND page data (err = %d)\n", in atmel_nand_pmecc_generate_eccbytes()
837 eccbuf = chip->oob_poi + oobregion.offset; in atmel_nand_pmecc_generate_eccbytes()
839 for (i = 0; i < chip->ecc.steps; i++) { in atmel_nand_pmecc_generate_eccbytes()
840 atmel_pmecc_get_generated_eccbytes(nand->pmecc, i, in atmel_nand_pmecc_generate_eccbytes()
842 eccbuf += chip->ecc.bytes; in atmel_nand_pmecc_generate_eccbytes()
851 struct atmel_nand *nand = to_atmel_nand(chip); in atmel_nand_pmecc_correct_data() local
858 nc = to_nand_controller(chip->controller); in atmel_nand_pmecc_correct_data()
863 ret = atmel_pmecc_wait_rdy(nand->pmecc); in atmel_nand_pmecc_correct_data()
865 dev_err(nc->dev, in atmel_nand_pmecc_correct_data()
866 "Failed to read NAND page data (err = %d)\n", in atmel_nand_pmecc_correct_data()
872 eccbuf = chip->oob_poi + oobregion.offset; in atmel_nand_pmecc_correct_data()
875 for (i = 0; i < chip->ecc.steps; i++) { in atmel_nand_pmecc_correct_data()
876 ret = atmel_pmecc_correct_sector(nand->pmecc, i, databuf, in atmel_nand_pmecc_correct_data()
878 if (ret < 0 && !atmel_pmecc_correct_erased_chunks(nand->pmecc)) in atmel_nand_pmecc_correct_data()
880 chip->ecc.size, in atmel_nand_pmecc_correct_data()
882 chip->ecc.bytes, in atmel_nand_pmecc_correct_data()
884 chip->ecc.strength); in atmel_nand_pmecc_correct_data()
887 mtd->ecc_stats.corrected += ret; in atmel_nand_pmecc_correct_data()
890 mtd->ecc_stats.failed++; in atmel_nand_pmecc_correct_data()
893 databuf += chip->ecc.size; in atmel_nand_pmecc_correct_data()
894 eccbuf += chip->ecc.bytes; in atmel_nand_pmecc_correct_data()
904 struct atmel_nand *nand = to_atmel_nand(chip); in atmel_nand_pmecc_write_pg() local
913 nand_write_data_op(chip, buf, mtd->writesize, false); in atmel_nand_pmecc_write_pg()
917 atmel_pmecc_disable(nand->pmecc); in atmel_nand_pmecc_write_pg()
923 nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false); in atmel_nand_pmecc_write_pg()
953 ret = nand_read_data_op(chip, buf, mtd->writesize, false, false); in atmel_nand_pmecc_read_pg()
957 ret = nand_read_data_op(chip, chip->oob_poi, mtd->oobsize, false, false); in atmel_nand_pmecc_read_pg()
986 struct atmel_nand *nand = to_atmel_nand(chip); in atmel_hsmc_nand_pmecc_write_pg() local
990 atmel_hsmc_nand_select_target(nand, chip->cur_cs); in atmel_hsmc_nand_pmecc_write_pg()
991 nc = to_hsmc_nand_controller(chip->controller); in atmel_hsmc_nand_pmecc_write_pg()
995 nc->op.cmds[0] = NAND_CMD_SEQIN; in atmel_hsmc_nand_pmecc_write_pg()
996 nc->op.ncmds = 1; in atmel_hsmc_nand_pmecc_write_pg()
998 nc->op.cs = nand->activecs->id; in atmel_hsmc_nand_pmecc_write_pg()
999 nc->op.data = ATMEL_NFC_WRITE_DATA; in atmel_hsmc_nand_pmecc_write_pg()
1008 dev_err(nc->base.dev, in atmel_hsmc_nand_pmecc_write_pg()
1009 "Failed to transfer NAND page data (err = %d)\n", in atmel_hsmc_nand_pmecc_write_pg()
1021 nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false); in atmel_hsmc_nand_pmecc_write_pg()
1047 struct atmel_nand *nand = to_atmel_nand(chip); in atmel_hsmc_nand_pmecc_read_pg() local
1051 atmel_hsmc_nand_select_target(nand, chip->cur_cs); in atmel_hsmc_nand_pmecc_read_pg()
1052 nc = to_hsmc_nand_controller(chip->controller); in atmel_hsmc_nand_pmecc_read_pg()
1055 * Optimized read page accessors only work when the NAND R/B pin is in atmel_hsmc_nand_pmecc_read_pg()
1057 * to the non-optimized one. in atmel_hsmc_nand_pmecc_read_pg()
1059 if (nand->activecs->rb.type != ATMEL_NAND_NATIVE_RB) in atmel_hsmc_nand_pmecc_read_pg()
1063 nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READ0; in atmel_hsmc_nand_pmecc_read_pg()
1065 if (mtd->writesize > 512) in atmel_hsmc_nand_pmecc_read_pg()
1066 nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READSTART; in atmel_hsmc_nand_pmecc_read_pg()
1069 nc->op.cs = nand->activecs->id; in atmel_hsmc_nand_pmecc_read_pg()
1070 nc->op.data = ATMEL_NFC_READ_DATA; in atmel_hsmc_nand_pmecc_read_pg()
1079 dev_err(nc->base.dev, in atmel_hsmc_nand_pmecc_read_pg()
1080 "Failed to load NAND page data (err = %d)\n", in atmel_hsmc_nand_pmecc_read_pg()
1112 nanddev_get_ecc_requirements(&chip->base); in atmel_nand_pmecc_init()
1115 struct atmel_nand *nand = to_atmel_nand(chip); in atmel_nand_pmecc_init() local
1119 nc = to_nand_controller(chip->controller); in atmel_nand_pmecc_init()
1121 if (!nc->pmecc) { in atmel_nand_pmecc_init()
1122 dev_err(nc->dev, "HW ECC not supported\n"); in atmel_nand_pmecc_init()
1123 return -ENOTSUPP; in atmel_nand_pmecc_init()
1126 if (nc->caps->legacy_of_bindings) { in atmel_nand_pmecc_init()
1129 if (!of_property_read_u32(nc->dev->of_node, "atmel,pmecc-cap", in atmel_nand_pmecc_init()
1131 chip->ecc.strength = val; in atmel_nand_pmecc_init()
1133 if (!of_property_read_u32(nc->dev->of_node, in atmel_nand_pmecc_init()
1134 "atmel,pmecc-sector-size", in atmel_nand_pmecc_init()
1136 chip->ecc.size = val; in atmel_nand_pmecc_init()
1139 if (nanddev->ecc.user_conf.flags & NAND_ECC_MAXIMIZE_STRENGTH) in atmel_nand_pmecc_init()
1141 else if (chip->ecc.strength) in atmel_nand_pmecc_init()
1142 req.ecc.strength = chip->ecc.strength; in atmel_nand_pmecc_init()
1143 else if (requirements->strength) in atmel_nand_pmecc_init()
1144 req.ecc.strength = requirements->strength; in atmel_nand_pmecc_init()
1148 if (chip->ecc.size) in atmel_nand_pmecc_init()
1149 req.ecc.sectorsize = chip->ecc.size; in atmel_nand_pmecc_init()
1150 else if (requirements->step_size) in atmel_nand_pmecc_init()
1151 req.ecc.sectorsize = requirements->step_size; in atmel_nand_pmecc_init()
1155 req.pagesize = mtd->writesize; in atmel_nand_pmecc_init()
1156 req.oobsize = mtd->oobsize; in atmel_nand_pmecc_init()
1158 if (mtd->writesize <= 512) { in atmel_nand_pmecc_init()
1162 req.ecc.bytes = mtd->oobsize - 2; in atmel_nand_pmecc_init()
1166 nand->pmecc = atmel_pmecc_create_user(nc->pmecc, &req); in atmel_nand_pmecc_init()
1167 if (IS_ERR(nand->pmecc)) in atmel_nand_pmecc_init()
1168 return PTR_ERR(nand->pmecc); in atmel_nand_pmecc_init()
1170 chip->ecc.algo = NAND_ECC_ALGO_BCH; in atmel_nand_pmecc_init()
1171 chip->ecc.size = req.ecc.sectorsize; in atmel_nand_pmecc_init()
1172 chip->ecc.bytes = req.ecc.bytes / req.ecc.nsectors; in atmel_nand_pmecc_init()
1173 chip->ecc.strength = req.ecc.strength; in atmel_nand_pmecc_init()
1175 chip->options |= NAND_NO_SUBPAGE_WRITE; in atmel_nand_pmecc_init()
1187 nc = to_nand_controller(chip->controller); in atmel_nand_ecc_init()
1189 switch (chip->ecc.engine_type) { in atmel_nand_ecc_init()
1202 chip->ecc.read_page = atmel_nand_pmecc_read_page; in atmel_nand_ecc_init()
1203 chip->ecc.write_page = atmel_nand_pmecc_write_page; in atmel_nand_ecc_init()
1204 chip->ecc.read_page_raw = atmel_nand_pmecc_read_page_raw; in atmel_nand_ecc_init()
1205 chip->ecc.write_page_raw = atmel_nand_pmecc_write_page_raw; in atmel_nand_ecc_init()
1210 dev_err(nc->dev, "Unsupported ECC mode: %d\n", in atmel_nand_ecc_init()
1211 chip->ecc.engine_type); in atmel_nand_ecc_init()
1212 return -ENOTSUPP; in atmel_nand_ecc_init()
1226 if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST) in atmel_hsmc_nand_ecc_init()
1230 chip->ecc.read_page = atmel_hsmc_nand_pmecc_read_page; in atmel_hsmc_nand_ecc_init()
1231 chip->ecc.write_page = atmel_hsmc_nand_pmecc_write_page; in atmel_hsmc_nand_ecc_init()
1232 chip->ecc.read_page_raw = atmel_hsmc_nand_pmecc_read_page_raw; in atmel_hsmc_nand_ecc_init()
1233 chip->ecc.write_page_raw = atmel_hsmc_nand_pmecc_write_page_raw; in atmel_hsmc_nand_ecc_init()
1238 static int atmel_smc_nand_prepare_smcconf(struct atmel_nand *nand, in atmel_smc_nand_prepare_smcconf() argument
1246 nc = to_nand_controller(nand->base.controller); in atmel_smc_nand_prepare_smcconf()
1250 return -ENOTSUPP; in atmel_smc_nand_prepare_smcconf()
1256 if (conf->timings.sdr.tRC_min < 30000) in atmel_smc_nand_prepare_smcconf()
1257 return -ENOTSUPP; in atmel_smc_nand_prepare_smcconf()
1261 mckperiodps = NSEC_PER_SEC / clk_get_rate(nc->mck); in atmel_smc_nand_prepare_smcconf()
1269 ncycles = DIV_ROUND_UP(conf->timings.sdr.tWP_min, mckperiodps); in atmel_smc_nand_prepare_smcconf()
1277 * The write setup timing depends on the operation done on the NAND. in atmel_smc_nand_prepare_smcconf()
1285 * NWE_SETUP = max(tCLS, tCS, tALS, tDS) - NWE_PULSE in atmel_smc_nand_prepare_smcconf()
1287 timeps = max3(conf->timings.sdr.tCLS_min, conf->timings.sdr.tCS_min, in atmel_smc_nand_prepare_smcconf()
1288 conf->timings.sdr.tALS_min); in atmel_smc_nand_prepare_smcconf()
1289 timeps = max(timeps, conf->timings.sdr.tDS_min); in atmel_smc_nand_prepare_smcconf()
1291 ncycles = ncycles > totalcycles ? ncycles - totalcycles : 0; in atmel_smc_nand_prepare_smcconf()
1300 * operation done on the NAND: in atmel_smc_nand_prepare_smcconf()
1304 timeps = max3(conf->timings.sdr.tCLH_min, conf->timings.sdr.tCH_min, in atmel_smc_nand_prepare_smcconf()
1305 conf->timings.sdr.tALH_min); in atmel_smc_nand_prepare_smcconf()
1306 timeps = max3(timeps, conf->timings.sdr.tDH_min, in atmel_smc_nand_prepare_smcconf()
1307 conf->timings.sdr.tWH_min); in atmel_smc_nand_prepare_smcconf()
1318 ncycles = DIV_ROUND_UP(conf->timings.sdr.tWC_min, mckperiodps); in atmel_smc_nand_prepare_smcconf()
1327 * transfer to the NAND. The only way to guarantee that is to have the in atmel_smc_nand_prepare_smcconf()
1339 * operation done on the NAND: in atmel_smc_nand_prepare_smcconf()
1343 timeps = max(conf->timings.sdr.tREH_min, conf->timings.sdr.tRHOH_min); in atmel_smc_nand_prepare_smcconf()
1348 * TDF = tRHZ - NRD_HOLD in atmel_smc_nand_prepare_smcconf()
1350 ncycles = DIV_ROUND_UP(conf->timings.sdr.tRHZ_max, mckperiodps); in atmel_smc_nand_prepare_smcconf()
1351 ncycles -= totalcycles; in atmel_smc_nand_prepare_smcconf()
1356 * Just take the max value in this case and hope that the NAND is more in atmel_smc_nand_prepare_smcconf()
1364 smcconf->mode |= ATMEL_SMC_MODE_TDF(ncycles) | in atmel_smc_nand_prepare_smcconf()
1372 ncycles = DIV_ROUND_UP(conf->timings.sdr.tRP_min, mckperiodps); in atmel_smc_nand_prepare_smcconf()
1388 ncycles = DIV_ROUND_UP(conf->timings.sdr.tRC_min, mckperiodps); in atmel_smc_nand_prepare_smcconf()
1397 * transfer from the NAND. The only way to guarantee that is to have in atmel_smc_nand_prepare_smcconf()
1408 ncycles = DIV_ROUND_UP(conf->timings.sdr.tCLR_min, mckperiodps); in atmel_smc_nand_prepare_smcconf()
1415 ncycles = DIV_ROUND_UP(conf->timings.sdr.tADL_min, mckperiodps); in atmel_smc_nand_prepare_smcconf()
1423 * accept the -ERANGE return code. in atmel_smc_nand_prepare_smcconf()
1430 if (ret && ret != -ERANGE) in atmel_smc_nand_prepare_smcconf()
1433 ncycles = DIV_ROUND_UP(conf->timings.sdr.tAR_min, mckperiodps); in atmel_smc_nand_prepare_smcconf()
1440 ncycles = DIV_ROUND_UP(conf->timings.sdr.tRR_min, mckperiodps); in atmel_smc_nand_prepare_smcconf()
1447 ncycles = DIV_ROUND_UP(conf->timings.sdr.tWB_max, mckperiodps); in atmel_smc_nand_prepare_smcconf()
1455 smcconf->timings |= ATMEL_HSMC_TIMINGS_NFSEL; in atmel_smc_nand_prepare_smcconf()
1458 if (nand->base.options & NAND_BUSWIDTH_16) in atmel_smc_nand_prepare_smcconf()
1459 smcconf->mode |= ATMEL_SMC_MODE_DBW_16; in atmel_smc_nand_prepare_smcconf()
1462 smcconf->mode |= ATMEL_SMC_MODE_READMODE_NRD | in atmel_smc_nand_prepare_smcconf()
1468 static int atmel_smc_nand_setup_interface(struct atmel_nand *nand, in atmel_smc_nand_setup_interface() argument
1477 nc = to_nand_controller(nand->base.controller); in atmel_smc_nand_setup_interface()
1479 ret = atmel_smc_nand_prepare_smcconf(nand, conf, &smcconf); in atmel_smc_nand_setup_interface()
1486 cs = &nand->cs[csline]; in atmel_smc_nand_setup_interface()
1487 cs->smcconf = smcconf; in atmel_smc_nand_setup_interface()
1488 atmel_smc_cs_conf_apply(nc->smc, cs->id, &cs->smcconf); in atmel_smc_nand_setup_interface()
1493 static int atmel_hsmc_nand_setup_interface(struct atmel_nand *nand, in atmel_hsmc_nand_setup_interface() argument
1502 nc = to_hsmc_nand_controller(nand->base.controller); in atmel_hsmc_nand_setup_interface()
1504 ret = atmel_smc_nand_prepare_smcconf(nand, conf, &smcconf); in atmel_hsmc_nand_setup_interface()
1511 cs = &nand->cs[csline]; in atmel_hsmc_nand_setup_interface()
1512 cs->smcconf = smcconf; in atmel_hsmc_nand_setup_interface()
1514 if (cs->rb.type == ATMEL_NAND_NATIVE_RB) in atmel_hsmc_nand_setup_interface()
1515 cs->smcconf.timings |= ATMEL_HSMC_TIMINGS_RBNSEL(cs->rb.id); in atmel_hsmc_nand_setup_interface()
1517 atmel_hsmc_cs_conf_apply(nc->base.smc, nc->hsmc_layout, cs->id, in atmel_hsmc_nand_setup_interface()
1518 &cs->smcconf); in atmel_hsmc_nand_setup_interface()
1526 struct atmel_nand *nand = to_atmel_nand(chip); in atmel_nand_setup_interface() local
1534 nc = to_nand_controller(nand->base.controller); in atmel_nand_setup_interface()
1536 if (csline >= nand->numcs || in atmel_nand_setup_interface()
1538 return -EINVAL; in atmel_nand_setup_interface()
1540 return nc->caps->ops->setup_interface(nand, csline, conf); in atmel_nand_setup_interface()
1547 struct atmel_nand *nand = to_atmel_nand(chip); in atmel_nand_exec_op() local
1550 nc = to_nand_controller(nand->base.controller); in atmel_nand_exec_op()
1552 return nc->caps->ops->exec_op(nand, op, check_only); in atmel_nand_exec_op()
1556 struct atmel_nand *nand) in atmel_nand_init() argument
1558 struct nand_chip *chip = &nand->base; in atmel_nand_init()
1561 mtd->dev.parent = nc->dev; in atmel_nand_init()
1562 nand->base.controller = &nc->base; in atmel_nand_init()
1564 if (!nc->mck || !nc->caps->ops->setup_interface) in atmel_nand_init()
1565 chip->options |= NAND_KEEP_TIMINGS; in atmel_nand_init()
1571 if (nc->dmac) in atmel_nand_init()
1572 chip->options |= NAND_USES_DMA; in atmel_nand_init()
1575 if (nc->pmecc) in atmel_nand_init()
1576 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; in atmel_nand_init()
1580 struct atmel_nand *nand) in atmel_smc_nand_init() argument
1582 struct nand_chip *chip = &nand->base; in atmel_smc_nand_init()
1586 atmel_nand_init(nc, nand); in atmel_smc_nand_init()
1588 smc_nc = to_smc_nand_controller(chip->controller); in atmel_smc_nand_init()
1589 if (!smc_nc->ebi_csa_regmap) in atmel_smc_nand_init()
1592 /* Attach the CS to the NAND Flash logic. */ in atmel_smc_nand_init()
1593 for (i = 0; i < nand->numcs; i++) in atmel_smc_nand_init()
1594 regmap_update_bits(smc_nc->ebi_csa_regmap, in atmel_smc_nand_init()
1595 smc_nc->ebi_csa->offs, in atmel_smc_nand_init()
1596 BIT(nand->cs[i].id), BIT(nand->cs[i].id)); in atmel_smc_nand_init()
1598 if (smc_nc->ebi_csa->nfd0_on_d16) in atmel_smc_nand_init()
1599 regmap_update_bits(smc_nc->ebi_csa_regmap, in atmel_smc_nand_init()
1600 smc_nc->ebi_csa->offs, in atmel_smc_nand_init()
1601 smc_nc->ebi_csa->nfd0_on_d16, in atmel_smc_nand_init()
1602 smc_nc->ebi_csa->nfd0_on_d16); in atmel_smc_nand_init()
1605 static int atmel_nand_controller_remove_nand(struct atmel_nand *nand) in atmel_nand_controller_remove_nand() argument
1607 struct nand_chip *chip = &nand->base; in atmel_nand_controller_remove_nand()
1616 list_del(&nand->node); in atmel_nand_controller_remove_nand()
1625 struct atmel_nand *nand; in atmel_nand_create() local
1632 dev_err(nc->dev, "Missing or invalid reg property\n"); in atmel_nand_create()
1633 return ERR_PTR(-EINVAL); in atmel_nand_create()
1636 nand = devm_kzalloc(nc->dev, struct_size(nand, cs, numcs), GFP_KERNEL); in atmel_nand_create()
1637 if (!nand) in atmel_nand_create()
1638 return ERR_PTR(-ENOMEM); in atmel_nand_create()
1640 nand->numcs = numcs; in atmel_nand_create()
1642 gpio = devm_fwnode_gpiod_get(nc->dev, of_fwnode_handle(np), in atmel_nand_create()
1643 "det", GPIOD_IN, "nand-det"); in atmel_nand_create()
1644 if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) { in atmel_nand_create()
1645 dev_err(nc->dev, in atmel_nand_create()
1652 nand->cdgpio = gpio; in atmel_nand_create()
1660 dev_err(nc->dev, "Invalid reg property (err = %d)\n", in atmel_nand_create()
1668 dev_err(nc->dev, "Invalid reg property (err = %d)\n", in atmel_nand_create()
1673 nand->cs[i].id = val; in atmel_nand_create()
1675 nand->cs[i].io.dma = res.start; in atmel_nand_create()
1676 nand->cs[i].io.virt = devm_ioremap_resource(nc->dev, &res); in atmel_nand_create()
1677 if (IS_ERR(nand->cs[i].io.virt)) in atmel_nand_create()
1678 return ERR_CAST(nand->cs[i].io.virt); in atmel_nand_create()
1680 if (!of_property_read_u32(np, "atmel,rb", &val)) { in atmel_nand_create()
1682 return ERR_PTR(-EINVAL); in atmel_nand_create()
1684 nand->cs[i].rb.type = ATMEL_NAND_NATIVE_RB; in atmel_nand_create()
1685 nand->cs[i].rb.id = val; in atmel_nand_create()
1687 gpio = devm_fwnode_gpiod_get_index(nc->dev, in atmel_nand_create()
1689 "rb", i, GPIOD_IN, in atmel_nand_create()
1690 "nand-rb"); in atmel_nand_create()
1691 if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) { in atmel_nand_create()
1692 dev_err(nc->dev, in atmel_nand_create()
1699 nand->cs[i].rb.type = ATMEL_NAND_GPIO_RB; in atmel_nand_create()
1700 nand->cs[i].rb.gpio = gpio; in atmel_nand_create()
1704 gpio = devm_fwnode_gpiod_get_index(nc->dev, in atmel_nand_create()
1707 "nand-cs"); in atmel_nand_create()
1708 if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) { in atmel_nand_create()
1709 dev_err(nc->dev, in atmel_nand_create()
1716 nand->cs[i].csgpio = gpio; in atmel_nand_create()
1719 nand_set_flash_node(&nand->base, np); in atmel_nand_create()
1721 return nand; in atmel_nand_create()
1726 struct atmel_nand *nand) in atmel_nand_controller_add_nand() argument
1728 struct nand_chip *chip = &nand->base; in atmel_nand_controller_add_nand()
1732 /* No card inserted, skip this NAND. */ in atmel_nand_controller_add_nand()
1733 if (nand->cdgpio && gpiod_get_value(nand->cdgpio)) { in atmel_nand_controller_add_nand()
1734 dev_info(nc->dev, "No SmartMedia card inserted.\n"); in atmel_nand_controller_add_nand()
1738 nc->caps->ops->nand_init(nc, nand); in atmel_nand_controller_add_nand()
1740 ret = nand_scan(chip, nand->numcs); in atmel_nand_controller_add_nand()
1742 dev_err(nc->dev, "NAND scan failed: %d\n", ret); in atmel_nand_controller_add_nand()
1748 dev_err(nc->dev, "Failed to register mtd device: %d\n", ret); in atmel_nand_controller_add_nand()
1753 list_add_tail(&nand->node, &nc->chips); in atmel_nand_controller_add_nand()
1761 struct atmel_nand *nand, *tmp; in atmel_nand_controller_remove_nands() local
1764 list_for_each_entry_safe(nand, tmp, &nc->chips, node) { in atmel_nand_controller_remove_nands()
1765 ret = atmel_nand_controller_remove_nand(nand); in atmel_nand_controller_remove_nands()
1776 struct device *dev = nc->dev; in atmel_nand_controller_legacy_add_nands()
1778 struct atmel_nand *nand; in atmel_nand_controller_legacy_add_nands() local
1783 * Legacy bindings only allow connecting a single NAND with a unique CS in atmel_nand_controller_legacy_add_nands()
1786 nand = devm_kzalloc(nc->dev, sizeof(*nand) + sizeof(*nand->cs), in atmel_nand_controller_legacy_add_nands()
1788 if (!nand) in atmel_nand_controller_legacy_add_nands()
1789 return -ENOMEM; in atmel_nand_controller_legacy_add_nands()
1791 nand->numcs = 1; in atmel_nand_controller_legacy_add_nands()
1794 nand->cs[0].io.virt = devm_ioremap_resource(dev, res); in atmel_nand_controller_legacy_add_nands()
1795 if (IS_ERR(nand->cs[0].io.virt)) in atmel_nand_controller_legacy_add_nands()
1796 return PTR_ERR(nand->cs[0].io.virt); in atmel_nand_controller_legacy_add_nands()
1798 nand->cs[0].io.dma = res->start; in atmel_nand_controller_legacy_add_nands()
1805 * If one wants to connect a NAND to a different CS line, he will in atmel_nand_controller_legacy_add_nands()
1808 nand->cs[0].id = 3; in atmel_nand_controller_legacy_add_nands()
1819 nand->cs[0].rb.type = ATMEL_NAND_GPIO_RB; in atmel_nand_controller_legacy_add_nands()
1820 nand->cs[0].rb.gpio = gpio; in atmel_nand_controller_legacy_add_nands()
1831 nand->cs[0].csgpio = gpio; in atmel_nand_controller_legacy_add_nands()
1834 gpio = devm_gpiod_get_index_optional(nc->dev, NULL, 2, GPIOD_IN); in atmel_nand_controller_legacy_add_nands()
1842 nand->cdgpio = gpio; in atmel_nand_controller_legacy_add_nands()
1844 nand_set_flash_node(&nand->base, nc->dev->of_node); in atmel_nand_controller_legacy_add_nands()
1846 return atmel_nand_controller_add_nand(nc, nand); in atmel_nand_controller_legacy_add_nands()
1852 struct device *dev = nc->dev; in atmel_nand_controller_add_nands()
1857 if (nc->caps->legacy_of_bindings) in atmel_nand_controller_add_nands()
1860 np = dev->of_node; in atmel_nand_controller_add_nands()
1862 ret = of_property_read_u32(np, "#address-cells", &val); in atmel_nand_controller_add_nands()
1864 dev_err(dev, "missing #address-cells property\n"); in atmel_nand_controller_add_nands()
1870 ret = of_property_read_u32(np, "#size-cells", &val); in atmel_nand_controller_add_nands()
1872 dev_err(dev, "missing #size-cells property\n"); in atmel_nand_controller_add_nands()
1879 struct atmel_nand *nand; in atmel_nand_controller_add_nands() local
1881 nand = atmel_nand_create(nc, nand_np, reg_cells); in atmel_nand_controller_add_nands()
1882 if (IS_ERR(nand)) { in atmel_nand_controller_add_nands()
1883 ret = PTR_ERR(nand); in atmel_nand_controller_add_nands()
1887 ret = atmel_nand_controller_add_nand(nc, nand); in atmel_nand_controller_add_nands()
1902 if (nc->dmac) in atmel_nand_controller_cleanup()
1903 dma_release_channel(nc->dmac); in atmel_nand_controller_cleanup()
1905 clk_put(nc->mck); in atmel_nand_controller_cleanup()
1943 .compatible = "atmel,at91sam9260-matrix",
1947 .compatible = "atmel,at91sam9261-matrix",
1951 .compatible = "atmel,at91sam9263-matrix",
1955 .compatible = "atmel,at91sam9rl-matrix",
1959 .compatible = "atmel,at91sam9g45-matrix",
1963 .compatible = "atmel,at91sam9n12-matrix",
1967 .compatible = "atmel,at91sam9x5-matrix",
1971 .compatible = "microchip,sam9x60-sfr",
1979 struct atmel_nand_controller *nc = to_nand_controller(chip->controller); in atmel_nand_attach_chip()
1980 struct atmel_nand *nand = to_atmel_nand(chip); in atmel_nand_attach_chip() local
1984 ret = nc->caps->ops->ecc_init(chip); in atmel_nand_attach_chip()
1988 if (nc->caps->legacy_of_bindings || !nc->dev->of_node) { in atmel_nand_attach_chip()
1994 mtd->name = "atmel_nand"; in atmel_nand_attach_chip()
1995 } else if (!mtd->name) { in atmel_nand_attach_chip()
1999 * should define the following property in your nand node: in atmel_nand_attach_chip()
2003 * This way, mtd->name will be set by the core when in atmel_nand_attach_chip()
2006 mtd->name = devm_kasprintf(nc->dev, GFP_KERNEL, in atmel_nand_attach_chip()
2007 "%s:nand.%d", dev_name(nc->dev), in atmel_nand_attach_chip()
2008 nand->cs[0].id); in atmel_nand_attach_chip()
2009 if (!mtd->name) { in atmel_nand_attach_chip()
2010 dev_err(nc->dev, "Failed to allocate mtd->name\n"); in atmel_nand_attach_chip()
2011 return -ENOMEM; in atmel_nand_attach_chip()
2028 struct device *dev = &pdev->dev; in atmel_nand_controller_init()
2029 struct device_node *np = dev->of_node; in atmel_nand_controller_init()
2032 nand_controller_init(&nc->base); in atmel_nand_controller_init()
2033 nc->base.ops = &atmel_nand_controller_ops; in atmel_nand_controller_init()
2034 INIT_LIST_HEAD(&nc->chips); in atmel_nand_controller_init()
2035 nc->dev = dev; in atmel_nand_controller_init()
2036 nc->caps = caps; in atmel_nand_controller_init()
2040 nc->pmecc = devm_atmel_pmecc_get(dev); in atmel_nand_controller_init()
2041 if (IS_ERR(nc->pmecc)) in atmel_nand_controller_init()
2042 return dev_err_probe(dev, PTR_ERR(nc->pmecc), in atmel_nand_controller_init()
2045 if (nc->caps->has_dma && !atmel_nand_avoid_dma) { in atmel_nand_controller_init()
2051 nc->dmac = dma_request_channel(mask, NULL, NULL); in atmel_nand_controller_init()
2052 if (!nc->dmac) in atmel_nand_controller_init()
2053 dev_err(nc->dev, "Failed to request DMA channel\n"); in atmel_nand_controller_init()
2057 if (nc->caps->legacy_of_bindings) in atmel_nand_controller_init()
2060 nc->mck = of_clk_get(dev->parent->of_node, 0); in atmel_nand_controller_init()
2061 if (IS_ERR(nc->mck)) { in atmel_nand_controller_init()
2063 return PTR_ERR(nc->mck); in atmel_nand_controller_init()
2066 np = of_parse_phandle(dev->parent->of_node, "atmel,smc", 0); in atmel_nand_controller_init()
2069 return -EINVAL; in atmel_nand_controller_init()
2072 nc->smc = syscon_node_to_regmap(np); in atmel_nand_controller_init()
2074 if (IS_ERR(nc->smc)) { in atmel_nand_controller_init()
2075 ret = PTR_ERR(nc->smc); in atmel_nand_controller_init()
2086 struct device *dev = nc->base.dev; in atmel_smc_nand_controller_init()
2092 if (nc->base.caps->legacy_of_bindings) in atmel_smc_nand_controller_init()
2095 np = of_parse_phandle(dev->parent->of_node, in atmel_smc_nand_controller_init()
2096 nc->base.caps->ebi_csa_regmap_name, 0); in atmel_smc_nand_controller_init()
2106 nc->ebi_csa_regmap = syscon_node_to_regmap(np); in atmel_smc_nand_controller_init()
2108 if (IS_ERR(nc->ebi_csa_regmap)) { in atmel_smc_nand_controller_init()
2109 ret = PTR_ERR(nc->ebi_csa_regmap); in atmel_smc_nand_controller_init()
2114 nc->ebi_csa = (struct atmel_smc_nand_ebi_csa_cfg *)match->data; in atmel_smc_nand_controller_init()
2117 * The at91sam9263 has 2 EBIs, if the NAND controller is under EBI1 in atmel_smc_nand_controller_init()
2118 * add 4 to ->ebi_csa->offs. in atmel_smc_nand_controller_init()
2120 if (of_device_is_compatible(dev->parent->of_node, in atmel_smc_nand_controller_init()
2121 "atmel,at91sam9263-ebi1")) in atmel_smc_nand_controller_init()
2122 nc->ebi_csa->offs += 4; in atmel_smc_nand_controller_init()
2136 struct device *dev = nc->base.dev; in atmel_hsmc_nand_controller_legacy_init()
2142 nand_np = dev->of_node; in atmel_hsmc_nand_controller_legacy_init()
2143 nfc_np = of_get_compatible_child(dev->of_node, "atmel,sama5d3-nfc"); in atmel_hsmc_nand_controller_legacy_init()
2145 dev_err(dev, "Could not find device node for sama5d3-nfc\n"); in atmel_hsmc_nand_controller_legacy_init()
2146 return -ENODEV; in atmel_hsmc_nand_controller_legacy_init()
2149 nc->clk = of_clk_get(nfc_np, 0); in atmel_hsmc_nand_controller_legacy_init()
2150 if (IS_ERR(nc->clk)) { in atmel_hsmc_nand_controller_legacy_init()
2151 ret = PTR_ERR(nc->clk); in atmel_hsmc_nand_controller_legacy_init()
2157 ret = clk_prepare_enable(nc->clk); in atmel_hsmc_nand_controller_legacy_init()
2164 nc->irq = of_irq_get(nand_np, 0); in atmel_hsmc_nand_controller_legacy_init()
2165 if (nc->irq <= 0) { in atmel_hsmc_nand_controller_legacy_init()
2166 ret = nc->irq ?: -ENXIO; in atmel_hsmc_nand_controller_legacy_init()
2167 if (ret != -EPROBE_DEFER) in atmel_hsmc_nand_controller_legacy_init()
2186 regmap_conf.name = "nfc-io"; in atmel_hsmc_nand_controller_legacy_init()
2187 regmap_conf.max_register = resource_size(&res) - 4; in atmel_hsmc_nand_controller_legacy_init()
2188 nc->io = devm_regmap_init_mmio(dev, iomem, ®map_conf); in atmel_hsmc_nand_controller_legacy_init()
2189 if (IS_ERR(nc->io)) { in atmel_hsmc_nand_controller_legacy_init()
2190 ret = PTR_ERR(nc->io); in atmel_hsmc_nand_controller_legacy_init()
2210 regmap_conf.max_register = resource_size(&res) - 4; in atmel_hsmc_nand_controller_legacy_init()
2211 nc->base.smc = devm_regmap_init_mmio(dev, iomem, ®map_conf); in atmel_hsmc_nand_controller_legacy_init()
2212 if (IS_ERR(nc->base.smc)) { in atmel_hsmc_nand_controller_legacy_init()
2213 ret = PTR_ERR(nc->base.smc); in atmel_hsmc_nand_controller_legacy_init()
2226 nc->sram.virt = devm_ioremap_resource(dev, &res); in atmel_hsmc_nand_controller_legacy_init()
2227 if (IS_ERR(nc->sram.virt)) { in atmel_hsmc_nand_controller_legacy_init()
2228 ret = PTR_ERR(nc->sram.virt); in atmel_hsmc_nand_controller_legacy_init()
2232 nc->sram.dma = res.start; in atmel_hsmc_nand_controller_legacy_init()
2243 struct device *dev = nc->base.dev; in atmel_hsmc_nand_controller_init()
2247 np = of_parse_phandle(dev->parent->of_node, "atmel,smc", 0); in atmel_hsmc_nand_controller_init()
2250 return -EINVAL; in atmel_hsmc_nand_controller_init()
2253 nc->hsmc_layout = atmel_hsmc_get_reg_layout(np); in atmel_hsmc_nand_controller_init()
2255 nc->irq = of_irq_get(np, 0); in atmel_hsmc_nand_controller_init()
2257 if (nc->irq <= 0) { in atmel_hsmc_nand_controller_init()
2258 ret = nc->irq ?: -ENXIO; in atmel_hsmc_nand_controller_init()
2259 if (ret != -EPROBE_DEFER) in atmel_hsmc_nand_controller_init()
2265 np = of_parse_phandle(dev->of_node, "atmel,nfc-io", 0); in atmel_hsmc_nand_controller_init()
2267 dev_err(dev, "Missing or invalid atmel,nfc-io property\n"); in atmel_hsmc_nand_controller_init()
2268 return -EINVAL; in atmel_hsmc_nand_controller_init()
2271 nc->io = syscon_node_to_regmap(np); in atmel_hsmc_nand_controller_init()
2273 if (IS_ERR(nc->io)) { in atmel_hsmc_nand_controller_init()
2274 ret = PTR_ERR(nc->io); in atmel_hsmc_nand_controller_init()
2279 nc->sram.pool = of_gen_pool_get(nc->base.dev->of_node, in atmel_hsmc_nand_controller_init()
2280 "atmel,nfc-sram", 0); in atmel_hsmc_nand_controller_init()
2281 if (!nc->sram.pool) { in atmel_hsmc_nand_controller_init()
2282 dev_err(nc->base.dev, "Missing SRAM\n"); in atmel_hsmc_nand_controller_init()
2283 return -ENOMEM; in atmel_hsmc_nand_controller_init()
2286 nc->sram.virt = (void __iomem *)gen_pool_dma_alloc(nc->sram.pool, in atmel_hsmc_nand_controller_init()
2288 &nc->sram.dma); in atmel_hsmc_nand_controller_init()
2289 if (!nc->sram.virt) { in atmel_hsmc_nand_controller_init()
2290 dev_err(nc->base.dev, in atmel_hsmc_nand_controller_init()
2292 return -ENOMEM; in atmel_hsmc_nand_controller_init()
2309 regmap_write(hsmc_nc->base.smc, ATMEL_HSMC_NFC_CTRL, in atmel_hsmc_nand_controller_remove()
2312 if (hsmc_nc->sram.pool) in atmel_hsmc_nand_controller_remove()
2313 gen_pool_free(hsmc_nc->sram.pool, in atmel_hsmc_nand_controller_remove()
2314 (unsigned long)hsmc_nc->sram.virt, in atmel_hsmc_nand_controller_remove()
2317 if (hsmc_nc->clk) { in atmel_hsmc_nand_controller_remove()
2318 clk_disable_unprepare(hsmc_nc->clk); in atmel_hsmc_nand_controller_remove()
2319 clk_put(hsmc_nc->clk); in atmel_hsmc_nand_controller_remove()
2330 struct device *dev = &pdev->dev; in atmel_hsmc_nand_controller_probe()
2336 return -ENOMEM; in atmel_hsmc_nand_controller_probe()
2338 ret = atmel_nand_controller_init(&nc->base, pdev, caps); in atmel_hsmc_nand_controller_probe()
2342 if (caps->legacy_of_bindings) in atmel_hsmc_nand_controller_probe()
2351 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, 0xffffffff); in atmel_hsmc_nand_controller_probe()
2352 ret = devm_request_irq(dev, nc->irq, atmel_nfc_interrupt, in atmel_hsmc_nand_controller_probe()
2362 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CFG, in atmel_hsmc_nand_controller_probe()
2364 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CTRL, in atmel_hsmc_nand_controller_probe()
2367 ret = atmel_nand_controller_add_nands(&nc->base); in atmel_hsmc_nand_controller_probe()
2374 atmel_hsmc_nand_controller_remove(&nc->base); in atmel_hsmc_nand_controller_probe()
2407 struct device *dev = &pdev->dev; in atmel_smc_nand_controller_probe()
2413 return -ENOMEM; in atmel_smc_nand_controller_probe()
2415 ret = atmel_nand_controller_init(&nc->base, pdev, caps); in atmel_smc_nand_controller_probe()
2423 return atmel_nand_controller_add_nands(&nc->base); in atmel_smc_nand_controller_probe()
2442 * from re-using atmel_smc_nand_setup_interface() for the
2443 * ->setup_interface() hook.
2445 * ->setup_interface() unassigned.
2526 .compatible = "atmel,at91rm9200-nand-controller",
2530 .compatible = "atmel,at91sam9260-nand-controller",
2534 .compatible = "atmel,at91sam9261-nand-controller",
2538 .compatible = "atmel,at91sam9g45-nand-controller",
2542 .compatible = "atmel,sama5d3-nand-controller",
2546 .compatible = "microchip,sam9x60-nand-controller",
2551 .compatible = "atmel,at91rm9200-nand",
2555 .compatible = "atmel,sama5d4-nand",
2559 .compatible = "atmel,sama5d2-nand",
2570 if (pdev->id_entry) in atmel_nand_controller_probe()
2571 caps = (void *)pdev->id_entry->driver_data; in atmel_nand_controller_probe()
2573 caps = of_device_get_match_data(&pdev->dev); in atmel_nand_controller_probe()
2576 dev_err(&pdev->dev, "Could not retrieve NFC caps\n"); in atmel_nand_controller_probe()
2577 return -EINVAL; in atmel_nand_controller_probe()
2580 if (caps->legacy_of_bindings) { in atmel_nand_controller_probe()
2588 nfc_node = of_get_compatible_child(pdev->dev.of_node, in atmel_nand_controller_probe()
2589 "atmel,sama5d3-nfc"); in atmel_nand_controller_probe()
2597 * at91rm9200 controller, the atmel,nand-has-dma specify that in atmel_nand_controller_probe()
2601 if (!caps->has_dma && in atmel_nand_controller_probe()
2602 of_property_read_bool(pdev->dev.of_node, in atmel_nand_controller_probe()
2603 "atmel,nand-has-dma")) in atmel_nand_controller_probe()
2608 * CLE to A22. If atmel,nand-addr-offset != 21 this means we're in atmel_nand_controller_probe()
2611 of_property_read_u32(pdev->dev.of_node, in atmel_nand_controller_probe()
2612 "atmel,nand-addr-offset", &ale_offs); in atmel_nand_controller_probe()
2617 return caps->ops->probe(pdev, caps); in atmel_nand_controller_probe()
2624 return nc->caps->ops->remove(nc); in atmel_nand_controller_remove()
2630 struct atmel_nand *nand; in atmel_nand_controller_resume() local
2632 if (nc->pmecc) in atmel_nand_controller_resume()
2633 atmel_pmecc_reset(nc->pmecc); in atmel_nand_controller_resume()
2635 list_for_each_entry(nand, &nc->chips, node) { in atmel_nand_controller_resume()
2638 for (i = 0; i < nand->numcs; i++) in atmel_nand_controller_resume()
2639 nand_reset(&nand->base, i); in atmel_nand_controller_resume()
2650 .name = "atmel-nand-controller",
2660 MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com>");
2661 MODULE_DESCRIPTION("NAND Flash Controller driver for Atmel SoCs");
2662 MODULE_ALIAS("platform:atmel-nand-controller");