1 // SPDX-License-Identifier: GPL-2.0
3  * sdhci_am654.c - SDHCI driver for TI's AM654 SOCs
5  * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com
18 #include "sdhci-pltfm.h"
105 	[MMC_TIMING_LEGACY]	= {"ti,otap-del-sel-legacy",
106 				   "ti,itap-del-sel-legacy",
108 	[MMC_TIMING_MMC_HS]	= {"ti,otap-del-sel-mmc-hs",
109 				   "ti,itap-del-sel-mmc-hs",
111 	[MMC_TIMING_SD_HS]	= {"ti,otap-del-sel-sd-hs",
112 				   "ti,itap-del-sel-sd-hs",
114 	[MMC_TIMING_UHS_SDR12]	= {"ti,otap-del-sel-sdr12",
115 				   "ti,itap-del-sel-sdr12",
117 	[MMC_TIMING_UHS_SDR25]	= {"ti,otap-del-sel-sdr25",
118 				   "ti,itap-del-sel-sdr25",
120 	[MMC_TIMING_UHS_SDR50]	= {"ti,otap-del-sel-sdr50",
123 	[MMC_TIMING_UHS_SDR104]	= {"ti,otap-del-sel-sdr104",
126 	[MMC_TIMING_UHS_DDR50]	= {"ti,otap-del-sel-ddr50",
129 	[MMC_TIMING_MMC_DDR52]	= {"ti,otap-del-sel-ddr52",
130 				   "ti,itap-del-sel-ddr52",
132 	[MMC_TIMING_MMC_HS200]	= {"ti,otap-del-sel-hs200",
135 	[MMC_TIMING_MMC_HS400]	= {"ti,otap-del-sel-hs400",
171 	regmap_update_bits(sdhci_am654->base, PHY_CTRL5,  in sdhci_am654_setup_dll()
174 	if (sdhci_am654->flags & FREQSEL_2_BIT) {  in sdhci_am654_setup_dll()
192 		regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val);  in sdhci_am654_setup_dll()
203 		regmap_update_bits(sdhci_am654->base, PHY_CTRL5, FREQSEL_MASK,  in sdhci_am654_setup_dll()
208 	val = sdhci_am654->trm_icp << DLL_TRIM_ICP_SHIFT;  in sdhci_am654_setup_dll()
212 	val |= sdhci_am654->drv_strength << DR_TY_SHIFT;  in sdhci_am654_setup_dll()
213 	regmap_update_bits(sdhci_am654->base, PHY_CTRL1, mask, val);  in sdhci_am654_setup_dll()
216 	regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK,  in sdhci_am654_setup_dll()
222 	ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1, val,  in sdhci_am654_setup_dll()
225 		dev_err(mmc_dev(host->mmc), "DLL failed to relock\n");  in sdhci_am654_setup_dll()
234 	regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK,  in sdhci_am654_write_itapdly()
236 	regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYSEL_MASK,  in sdhci_am654_write_itapdly()
238 	regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0);  in sdhci_am654_write_itapdly()
246 	regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0);  in sdhci_am654_setup_delay_chain()
250 	regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val);  in sdhci_am654_setup_delay_chain()
253 				  sdhci_am654->itap_del_sel[timing]);  in sdhci_am654_setup_delay_chain()
260 	unsigned char timing = host->mmc->ios.timing;  in sdhci_am654_set_clock()
265 	regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0);  in sdhci_am654_set_clock()
269 	/* Setup DLL Output TAP delay */  in sdhci_am654_set_clock()
270 	if (sdhci_am654->legacy_otapdly)  in sdhci_am654_set_clock()
271 		otap_del_sel = sdhci_am654->otap_del_sel[0];  in sdhci_am654_set_clock()
273 		otap_del_sel = sdhci_am654->otap_del_sel[timing];  in sdhci_am654_set_clock()
283 		if (sdhci_am654->flags & STRBSEL_4_BIT)  in sdhci_am654_set_clock()
288 		val |= sdhci_am654->strb_sel << STRBSEL_SHIFT;  in sdhci_am654_set_clock()
291 	regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val);  in sdhci_am654_set_clock()
298 	regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK,  in sdhci_am654_set_clock()
299 			   sdhci_am654->clkbuf_sel);  in sdhci_am654_set_clock()
307 	unsigned char timing = host->mmc->ios.timing;  in sdhci_j721e_4bit_set_clock()
311 	/* Setup DLL Output TAP delay */  in sdhci_j721e_4bit_set_clock()
312 	if (sdhci_am654->legacy_otapdly)  in sdhci_j721e_4bit_set_clock()
313 		otap_del_sel = sdhci_am654->otap_del_sel[0];  in sdhci_j721e_4bit_set_clock()
315 		otap_del_sel = sdhci_am654->otap_del_sel[timing];  in sdhci_j721e_4bit_set_clock()
320 	regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val);  in sdhci_j721e_4bit_set_clock()
322 	regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK,  in sdhci_j721e_4bit_set_clock()
323 			   sdhci_am654->clkbuf_sel);  in sdhci_j721e_4bit_set_clock()
330 	writeb(val, host->ioaddr + reg);  in sdhci_am654_write_power_on()
332 	return readb(host->ioaddr + reg);  in sdhci_am654_write_power_on()
338 	unsigned char timing = host->mmc->ios.timing;  in sdhci_am654_write_b()
356 	writeb(val, host->ioaddr + reg);  in sdhci_am654_write_b()
368 			dev_warn(mmc_dev(host->mmc), "Power on failed\n");  in sdhci_am654_write_b()
380 	 * Tuning data remains in the buffer after tuning.  in sdhci_am654_execute_tuning()
396 	cqhci_irq(host->mmc, intmask, cmd_error, data_error);  in sdhci_am654_cqhci_irq()
411 	regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYENA_MASK,  in sdhci_am654_platform_execute_tuning()
417 		cur_val = !mmc_send_tuning(host->mmc, opcode, NULL);  in sdhci_am654_platform_execute_tuning()
427 	 * Having determined the length of the failing window and start of  in sdhci_am654_platform_execute_tuning()
432 	pass_len = ITAP_MAX - fail_len;  in sdhci_am654_platform_execute_tuning()
561 	cq_host = devm_kzalloc(mmc_dev(host->mmc), sizeof(struct cqhci_host),  in sdhci_am654_cqe_add_host()
564 		return -ENOMEM;  in sdhci_am654_cqe_add_host()
566 	cq_host->mmio = host->ioaddr + SDHCI_AM654_CQE_BASE_ADDR;  in sdhci_am654_cqe_add_host()
567 	cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ;  in sdhci_am654_cqe_add_host()
568 	cq_host->caps |= CQHCI_TASK_DESC_SZ_128;  in sdhci_am654_cqe_add_host()
569 	cq_host->ops = &sdhci_am654_cqhci_ops;  in sdhci_am654_cqe_add_host()
571 	host->mmc->caps2 |= MMC_CAP2_CQE;  in sdhci_am654_cqe_add_host()
573 	ret = cqhci_init(cq_host, host->mmc, 1);  in sdhci_am654_cqe_add_host()
581 	struct device *dev = mmc_dev(host->mmc);  in sdhci_am654_get_otap_delay()
586 				 &sdhci_am654->otap_del_sel[MMC_TIMING_LEGACY]);  in sdhci_am654_get_otap_delay()
589 		 * ti,otap-del-sel-legacy is mandatory, look for old binding  in sdhci_am654_get_otap_delay()
592 		ret = device_property_read_u32(dev, "ti,otap-del-sel",  in sdhci_am654_get_otap_delay()
593 					       &sdhci_am654->otap_del_sel[0]);  in sdhci_am654_get_otap_delay()
595 			dev_err(dev, "Couldn't find otap-del-sel\n");  in sdhci_am654_get_otap_delay()
600 		dev_info(dev, "Using legacy binding ti,otap-del-sel\n");  in sdhci_am654_get_otap_delay()
601 		sdhci_am654->legacy_otapdly = true;  in sdhci_am654_get_otap_delay()
609 					       &sdhci_am654->otap_del_sel[i]);  in sdhci_am654_get_otap_delay()
615 			 * if an otap-del-sel value is not found  in sdhci_am654_get_otap_delay()
618 				host->mmc->caps &= ~td[i].capability;  in sdhci_am654_get_otap_delay()
620 				host->mmc->caps2 &= ~td[i].capability;  in sdhci_am654_get_otap_delay()
625 						 &sdhci_am654->itap_del_sel[i]);  in sdhci_am654_get_otap_delay()
642 	regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 0x0);  in sdhci_am654_init()
644 	if (sdhci_am654->flags & DLL_CALIB) {  in sdhci_am654_init()
645 		regmap_read(sdhci_am654->base, PHY_STAT1, &val);  in sdhci_am654_init()
648 			regmap_update_bits(sdhci_am654->base, PHY_CTRL1,  in sdhci_am654_init()
650 			ret = regmap_read_poll_timeout(sdhci_am654->base,  in sdhci_am654_init()
660 	if (sdhci_am654->flags & IOMUX_PRESENT)  in sdhci_am654_init()
661 		regmap_update_bits(sdhci_am654->base, PHY_CTRL1,  in sdhci_am654_init()
665 	if (host->mmc->caps & MMC_CAP_NONREMOVABLE)  in sdhci_am654_init()
668 	regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK,  in sdhci_am654_init()
671 	/* Enable tuning for SDR50 */  in sdhci_am654_init()
672 	regmap_update_bits(sdhci_am654->base, CTL_CFG_3, TUNINGFORSDR50_MASK,  in sdhci_am654_init()
701 	struct device *dev = &pdev->dev;  in sdhci_am654_get_of_property()
705 	if (sdhci_am654->flags & DLL_PRESENT) {  in sdhci_am654_get_of_property()
706 		ret = device_property_read_u32(dev, "ti,trm-icp",  in sdhci_am654_get_of_property()
707 					       &sdhci_am654->trm_icp);  in sdhci_am654_get_of_property()
711 		ret = device_property_read_u32(dev, "ti,driver-strength-ohm",  in sdhci_am654_get_of_property()
718 			sdhci_am654->drv_strength = DRIVER_STRENGTH_50_OHM;  in sdhci_am654_get_of_property()
721 			sdhci_am654->drv_strength = DRIVER_STRENGTH_33_OHM;  in sdhci_am654_get_of_property()
724 			sdhci_am654->drv_strength = DRIVER_STRENGTH_66_OHM;  in sdhci_am654_get_of_property()
727 			sdhci_am654->drv_strength = DRIVER_STRENGTH_100_OHM;  in sdhci_am654_get_of_property()
730 			sdhci_am654->drv_strength = DRIVER_STRENGTH_40_OHM;  in sdhci_am654_get_of_property()
734 			return -EINVAL;  in sdhci_am654_get_of_property()
738 	device_property_read_u32(dev, "ti,strobe-sel", &sdhci_am654->strb_sel);  in sdhci_am654_get_of_property()
739 	device_property_read_u32(dev, "ti,clkbuf-sel",  in sdhci_am654_get_of_property()
740 				 &sdhci_am654->clkbuf_sel);  in sdhci_am654_get_of_property()
749 		.compatible = "ti,am654-sdhci-5.1",
753 		.compatible = "ti,j721e-sdhci-8bit",
757 		.compatible = "ti,j721e-sdhci-4bit",
761 		.compatible = "ti,am64-sdhci-8bit",
765 		.compatible = "ti,am64-sdhci-4bit",
781 	struct device *dev = &pdev->dev;  in sdhci_am654_probe()
785 	match = of_match_node(sdhci_am654_of_match, pdev->dev.of_node);  in sdhci_am654_probe()
786 	drvdata = match->data;  in sdhci_am654_probe()
790 	if (soc && soc->data)  in sdhci_am654_probe()
791 		drvdata = soc->data;  in sdhci_am654_probe()
793 	host = sdhci_pltfm_init(pdev, drvdata->pdata, sizeof(*sdhci_am654));  in sdhci_am654_probe()
799 	sdhci_am654->flags = drvdata->flags;  in sdhci_am654_probe()
808 	pltfm_host->clk = clk_xin;  in sdhci_am654_probe()
822 	sdhci_am654->base = devm_regmap_init_mmio(dev, base,  in sdhci_am654_probe()
824 	if (IS_ERR(sdhci_am654->base)) {  in sdhci_am654_probe()
826 		ret = PTR_ERR(sdhci_am654->base);  in sdhci_am654_probe()
834 	ret = mmc_of_parse(host->mmc);  in sdhci_am654_probe()
840 	host->mmc_host_ops.execute_tuning = sdhci_am654_execute_tuning;  in sdhci_am654_probe()
863 	ret = pm_runtime_put_sync(&pdev->dev);  in sdhci_am654_remove()
867 	pm_runtime_disable(&pdev->dev);  in sdhci_am654_remove()
875 		.name = "sdhci-am654",