346 	reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);  in tegra_sdhci_set_tap()
365 	val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL);  in tegra_sdhci_hs400_enhanced_strobe()
390 	misc_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL);  in tegra_sdhci_reset()
391 	clk_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);  in tegra_sdhci_reset()
422 		pad_ctrl = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL);  in tegra_sdhci_reset()
441 	val = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL);  in tegra_sdhci_configure_cal_pad()
459 	reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG);  in tegra_sdhci_set_pad_autocal_offset()
504 			reg = sdhci_readl(host,  in tegra_sdhci_set_padctrl()
568 	reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG);  in tegra_sdhci_pad_autocalib()
586 		reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG);  in tegra_sdhci_pad_autocalib()
807 	val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CAP_OVERRIDES);  in tegra_sdhci_set_dqs_trim()
818 	reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_DLLCAL_CFG);  in tegra_sdhci_hs400_dll_cal()
855 		val = sdhci_readl(host, SDHCI_VNDR_TUN_CTRL0_0);  in tegra_sdhci_tap_correction()
859 		tun_status = sdhci_readl(host, SDHCI_TEGRA_VNDR_TUN_STATUS0);  in tegra_sdhci_tap_correction()
926 	val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);  in tegra_sdhci_post_tuning()
949 		val = sdhci_readl(host, SDHCI_TEGRA_VNDR_TUN_STATUS1);  in tegra_sdhci_post_tuning()
1019 	val = sdhci_readl(host, SDHCI_VNDR_TUN_CTRL0_0);  in tegra_sdhci_set_uhs_signaling()
1284 	val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL);  in tegra_sdhci_set_timeout()