Lines Matching +full:tuning +full:- +full:start +full:- +full:tap
1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/dma-mapping.h>
23 #include <linux/mmc/slot-gpio.h>
27 #include "sdhci-pltfm.h"
182 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; in tegra_sdhci_readw()
184 if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) && in tegra_sdhci_readw()
190 return readw(host->ioaddr + reg); in tegra_sdhci_readw()
203 pltfm_host->xfer_mode_shadow = val; in tegra_sdhci_writew()
206 writel((val << 16) | pltfm_host->xfer_mode_shadow, in tegra_sdhci_writew()
207 host->ioaddr + SDHCI_TRANSFER_MODE); in tegra_sdhci_writew()
211 writew(val, host->ioaddr + reg); in tegra_sdhci_writew()
218 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; in tegra_sdhci_writel()
227 writel(val, host->ioaddr + reg); in tegra_sdhci_writel()
229 if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) && in tegra_sdhci_writel()
232 u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); in tegra_sdhci_writel()
237 writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); in tegra_sdhci_writel()
277 writew(val, host->ioaddr + reg); in tegra210_sdhci_writew()
289 * Write-enable shall be assumed if GPIO is missing in a board's in tegra_sdhci_get_ro()
290 * device-tree because SDHCI's WRITE_PROTECT bit doesn't work on in tegra_sdhci_get_ro()
293 return mmc_gpio_get_ro(host->mmc); in tegra_sdhci_get_ro()
310 if (!(tegra_host->soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL)) in tegra_sdhci_is_pad_and_regulator_valid()
313 if (IS_ERR(host->mmc->supply.vqmmc)) in tegra_sdhci_is_pad_and_regulator_valid()
316 has_1v8 = regulator_is_supported_voltage(host->mmc->supply.vqmmc, in tegra_sdhci_is_pad_and_regulator_valid()
319 has_3v3 = regulator_is_supported_voltage(host->mmc->supply.vqmmc, in tegra_sdhci_is_pad_and_regulator_valid()
323 return tegra_host->pad_control_available; in tegra_sdhci_is_pad_and_regulator_valid()
329 static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned int tap) in tegra_sdhci_set_tap() argument
333 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; in tegra_sdhci_set_tap()
338 * Touching the tap values is a bit tricky on some SoC generations. in tegra_sdhci_set_tap()
340 * the tap values are changed. in tegra_sdhci_set_tap()
343 if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP) in tegra_sdhci_set_tap()
348 reg |= tap << SDHCI_CLOCK_CTRL_TAP_SHIFT; in tegra_sdhci_set_tap()
351 if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP && in tegra_sdhci_set_tap()
367 if (ios->enhanced_strobe) in tegra_sdhci_hs400_enhanced_strobe()
380 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; in tegra_sdhci_reset()
388 tegra_sdhci_set_tap(host, tegra_host->default_tap); in tegra_sdhci_reset()
403 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300) in tegra_sdhci_reset()
406 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50) in tegra_sdhci_reset()
408 if (soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) in tegra_sdhci_reset()
410 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR104) in tegra_sdhci_reset()
412 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50) in tegra_sdhci_reset()
416 clk_ctrl |= tegra_host->default_trim << SDHCI_CLOCK_CTRL_TRIM_SHIFT; in tegra_sdhci_reset()
421 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) { in tegra_sdhci_reset()
427 tegra_host->pad_calib_required = true; in tegra_sdhci_reset()
430 tegra_host->ddr_signaling = false; in tegra_sdhci_reset()
471 &tegra_host->autocal_offsets; in tegra_sdhci_set_padctrl()
480 if (tegra_host->pinctrl_state_1v8_drv) { in tegra_sdhci_set_padctrl()
482 tegra_host->pinctrl_state_1v8_drv; in tegra_sdhci_set_padctrl()
484 drvup = offsets->pull_up_1v8_timeout; in tegra_sdhci_set_padctrl()
485 drvdn = offsets->pull_down_1v8_timeout; in tegra_sdhci_set_padctrl()
488 if (tegra_host->pinctrl_state_3v3_drv) { in tegra_sdhci_set_padctrl()
490 tegra_host->pinctrl_state_3v3_drv; in tegra_sdhci_set_padctrl()
492 drvup = offsets->pull_up_3v3_timeout; in tegra_sdhci_set_padctrl()
493 drvdn = offsets->pull_down_3v3_timeout; in tegra_sdhci_set_padctrl()
498 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, in tegra_sdhci_set_padctrl()
501 dev_err(mmc_dev(host->mmc), in tegra_sdhci_set_padctrl()
514 if (!tegra_host->pad_control_available) in tegra_sdhci_set_padctrl()
518 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, in tegra_sdhci_set_padctrl()
519 tegra_host->pinctrl_state_1v8); in tegra_sdhci_set_padctrl()
521 dev_err(mmc_dev(host->mmc), in tegra_sdhci_set_padctrl()
524 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, in tegra_sdhci_set_padctrl()
525 tegra_host->pinctrl_state_3v3); in tegra_sdhci_set_padctrl()
527 dev_err(mmc_dev(host->mmc), in tegra_sdhci_set_padctrl()
540 tegra_host->autocal_offsets; in tegra_sdhci_pad_autocalib()
541 struct mmc_ios *ios = &host->mmc->ios; in tegra_sdhci_pad_autocalib()
547 switch (ios->timing) { in tegra_sdhci_pad_autocalib()
555 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) in tegra_sdhci_pad_autocalib()
561 /* Set initial offset before auto-calibration */ in tegra_sdhci_pad_autocalib()
574 ret = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_AUTO_CAL_STATUS, in tegra_sdhci_pad_autocalib()
583 dev_err(mmc_dev(host->mmc), "Pad autocal timed out\n"); in tegra_sdhci_pad_autocalib()
590 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, false); in tegra_sdhci_pad_autocalib()
592 dev_err(mmc_dev(host->mmc), in tegra_sdhci_pad_autocalib()
602 &tegra_host->autocal_offsets; in tegra_sdhci_parse_pad_autocal_dt()
605 err = device_property_read_u32(mmc_dev(host->mmc), in tegra_sdhci_parse_pad_autocal_dt()
606 "nvidia,pad-autocal-pull-up-offset-3v3", in tegra_sdhci_parse_pad_autocal_dt()
607 &autocal->pull_up_3v3); in tegra_sdhci_parse_pad_autocal_dt()
609 autocal->pull_up_3v3 = 0; in tegra_sdhci_parse_pad_autocal_dt()
611 err = device_property_read_u32(mmc_dev(host->mmc), in tegra_sdhci_parse_pad_autocal_dt()
612 "nvidia,pad-autocal-pull-down-offset-3v3", in tegra_sdhci_parse_pad_autocal_dt()
613 &autocal->pull_down_3v3); in tegra_sdhci_parse_pad_autocal_dt()
615 autocal->pull_down_3v3 = 0; in tegra_sdhci_parse_pad_autocal_dt()
617 err = device_property_read_u32(mmc_dev(host->mmc), in tegra_sdhci_parse_pad_autocal_dt()
618 "nvidia,pad-autocal-pull-up-offset-1v8", in tegra_sdhci_parse_pad_autocal_dt()
619 &autocal->pull_up_1v8); in tegra_sdhci_parse_pad_autocal_dt()
621 autocal->pull_up_1v8 = 0; in tegra_sdhci_parse_pad_autocal_dt()
623 err = device_property_read_u32(mmc_dev(host->mmc), in tegra_sdhci_parse_pad_autocal_dt()
624 "nvidia,pad-autocal-pull-down-offset-1v8", in tegra_sdhci_parse_pad_autocal_dt()
625 &autocal->pull_down_1v8); in tegra_sdhci_parse_pad_autocal_dt()
627 autocal->pull_down_1v8 = 0; in tegra_sdhci_parse_pad_autocal_dt()
629 err = device_property_read_u32(mmc_dev(host->mmc), in tegra_sdhci_parse_pad_autocal_dt()
630 "nvidia,pad-autocal-pull-up-offset-sdr104", in tegra_sdhci_parse_pad_autocal_dt()
631 &autocal->pull_up_sdr104); in tegra_sdhci_parse_pad_autocal_dt()
633 autocal->pull_up_sdr104 = autocal->pull_up_1v8; in tegra_sdhci_parse_pad_autocal_dt()
635 err = device_property_read_u32(mmc_dev(host->mmc), in tegra_sdhci_parse_pad_autocal_dt()
636 "nvidia,pad-autocal-pull-down-offset-sdr104", in tegra_sdhci_parse_pad_autocal_dt()
637 &autocal->pull_down_sdr104); in tegra_sdhci_parse_pad_autocal_dt()
639 autocal->pull_down_sdr104 = autocal->pull_down_1v8; in tegra_sdhci_parse_pad_autocal_dt()
641 err = device_property_read_u32(mmc_dev(host->mmc), in tegra_sdhci_parse_pad_autocal_dt()
642 "nvidia,pad-autocal-pull-up-offset-hs400", in tegra_sdhci_parse_pad_autocal_dt()
643 &autocal->pull_up_hs400); in tegra_sdhci_parse_pad_autocal_dt()
645 autocal->pull_up_hs400 = autocal->pull_up_1v8; in tegra_sdhci_parse_pad_autocal_dt()
647 err = device_property_read_u32(mmc_dev(host->mmc), in tegra_sdhci_parse_pad_autocal_dt()
648 "nvidia,pad-autocal-pull-down-offset-hs400", in tegra_sdhci_parse_pad_autocal_dt()
649 &autocal->pull_down_hs400); in tegra_sdhci_parse_pad_autocal_dt()
651 autocal->pull_down_hs400 = autocal->pull_down_1v8; in tegra_sdhci_parse_pad_autocal_dt()
654 * Different fail-safe drive strength values based on the signaling in tegra_sdhci_parse_pad_autocal_dt()
659 if (!(tegra_host->soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL)) in tegra_sdhci_parse_pad_autocal_dt()
662 err = device_property_read_u32(mmc_dev(host->mmc), in tegra_sdhci_parse_pad_autocal_dt()
663 "nvidia,pad-autocal-pull-up-offset-3v3-timeout", in tegra_sdhci_parse_pad_autocal_dt()
664 &autocal->pull_up_3v3_timeout); in tegra_sdhci_parse_pad_autocal_dt()
666 if (!IS_ERR(tegra_host->pinctrl_state_3v3) && in tegra_sdhci_parse_pad_autocal_dt()
667 (tegra_host->pinctrl_state_3v3_drv == NULL)) in tegra_sdhci_parse_pad_autocal_dt()
668 pr_warn("%s: Missing autocal timeout 3v3-pad drvs\n", in tegra_sdhci_parse_pad_autocal_dt()
669 mmc_hostname(host->mmc)); in tegra_sdhci_parse_pad_autocal_dt()
670 autocal->pull_up_3v3_timeout = 0; in tegra_sdhci_parse_pad_autocal_dt()
673 err = device_property_read_u32(mmc_dev(host->mmc), in tegra_sdhci_parse_pad_autocal_dt()
674 "nvidia,pad-autocal-pull-down-offset-3v3-timeout", in tegra_sdhci_parse_pad_autocal_dt()
675 &autocal->pull_down_3v3_timeout); in tegra_sdhci_parse_pad_autocal_dt()
677 if (!IS_ERR(tegra_host->pinctrl_state_3v3) && in tegra_sdhci_parse_pad_autocal_dt()
678 (tegra_host->pinctrl_state_3v3_drv == NULL)) in tegra_sdhci_parse_pad_autocal_dt()
679 pr_warn("%s: Missing autocal timeout 3v3-pad drvs\n", in tegra_sdhci_parse_pad_autocal_dt()
680 mmc_hostname(host->mmc)); in tegra_sdhci_parse_pad_autocal_dt()
681 autocal->pull_down_3v3_timeout = 0; in tegra_sdhci_parse_pad_autocal_dt()
684 err = device_property_read_u32(mmc_dev(host->mmc), in tegra_sdhci_parse_pad_autocal_dt()
685 "nvidia,pad-autocal-pull-up-offset-1v8-timeout", in tegra_sdhci_parse_pad_autocal_dt()
686 &autocal->pull_up_1v8_timeout); in tegra_sdhci_parse_pad_autocal_dt()
688 if (!IS_ERR(tegra_host->pinctrl_state_1v8) && in tegra_sdhci_parse_pad_autocal_dt()
689 (tegra_host->pinctrl_state_1v8_drv == NULL)) in tegra_sdhci_parse_pad_autocal_dt()
690 pr_warn("%s: Missing autocal timeout 1v8-pad drvs\n", in tegra_sdhci_parse_pad_autocal_dt()
691 mmc_hostname(host->mmc)); in tegra_sdhci_parse_pad_autocal_dt()
692 autocal->pull_up_1v8_timeout = 0; in tegra_sdhci_parse_pad_autocal_dt()
695 err = device_property_read_u32(mmc_dev(host->mmc), in tegra_sdhci_parse_pad_autocal_dt()
696 "nvidia,pad-autocal-pull-down-offset-1v8-timeout", in tegra_sdhci_parse_pad_autocal_dt()
697 &autocal->pull_down_1v8_timeout); in tegra_sdhci_parse_pad_autocal_dt()
699 if (!IS_ERR(tegra_host->pinctrl_state_1v8) && in tegra_sdhci_parse_pad_autocal_dt()
700 (tegra_host->pinctrl_state_1v8_drv == NULL)) in tegra_sdhci_parse_pad_autocal_dt()
701 pr_warn("%s: Missing autocal timeout 1v8-pad drvs\n", in tegra_sdhci_parse_pad_autocal_dt()
702 mmc_hostname(host->mmc)); in tegra_sdhci_parse_pad_autocal_dt()
703 autocal->pull_down_1v8_timeout = 0; in tegra_sdhci_parse_pad_autocal_dt()
712 ktime_t since_calib = ktime_sub(ktime_get(), tegra_host->last_calib); in tegra_sdhci_request()
717 tegra_host->last_calib = ktime_get(); in tegra_sdhci_request()
729 err = device_property_read_u32(mmc_dev(host->mmc), "nvidia,default-tap", in tegra_sdhci_parse_tap_and_trim()
730 &tegra_host->default_tap); in tegra_sdhci_parse_tap_and_trim()
732 tegra_host->default_tap = 0; in tegra_sdhci_parse_tap_and_trim()
734 err = device_property_read_u32(mmc_dev(host->mmc), "nvidia,default-trim", in tegra_sdhci_parse_tap_and_trim()
735 &tegra_host->default_trim); in tegra_sdhci_parse_tap_and_trim()
737 tegra_host->default_trim = 0; in tegra_sdhci_parse_tap_and_trim()
739 err = device_property_read_u32(mmc_dev(host->mmc), "nvidia,dqs-trim", in tegra_sdhci_parse_tap_and_trim()
740 &tegra_host->dqs_trim); in tegra_sdhci_parse_tap_and_trim()
742 tegra_host->dqs_trim = 0x11; in tegra_sdhci_parse_tap_and_trim()
750 if (device_property_read_bool(mmc_dev(host->mmc), "supports-cqe")) in tegra_sdhci_parse_dt()
751 tegra_host->enable_hwcq = true; in tegra_sdhci_parse_dt()
753 tegra_host->enable_hwcq = false; in tegra_sdhci_parse_dt()
772 * sdhci_calc_clk(). The divider is calculated from host->max_clk and in tegra_sdhci_set_clock()
775 * By setting the host->max_clk to clock * 2 the divider calculation in tegra_sdhci_set_clock()
780 host_clk = tegra_host->ddr_signaling ? clock * 2 : clock; in tegra_sdhci_set_clock()
781 clk_set_rate(pltfm_host->clk, host_clk); in tegra_sdhci_set_clock()
782 tegra_host->curr_clk_rate = host_clk; in tegra_sdhci_set_clock()
783 if (tegra_host->ddr_signaling) in tegra_sdhci_set_clock()
784 host->max_clk = host_clk; in tegra_sdhci_set_clock()
786 host->max_clk = clk_get_rate(pltfm_host->clk); in tegra_sdhci_set_clock()
790 if (tegra_host->pad_calib_required) { in tegra_sdhci_set_clock()
792 tegra_host->pad_calib_required = false; in tegra_sdhci_set_clock()
800 return clk_round_rate(pltfm_host->clk, UINT_MAX); in tegra_sdhci_get_max_clock()
823 err = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_VENDOR_DLLCAL_STA, in tegra_sdhci_hs400_dll_cal()
827 dev_err(mmc_dev(host->mmc), in tegra_sdhci_hs400_dll_cal()
837 u8 word, bit, edge1, tap, window; in tegra_sdhci_tap_correction() local
848 u8 total_tuning_words = host->tuning_loop_count / TUNING_WORD_BIT_SIZE; in tegra_sdhci_tap_correction()
851 * Read auto-tuned results and extract good valid passing window by in tegra_sdhci_tap_correction()
852 * filtering out un-wanted bubble/partial/merged windows. in tegra_sdhci_tap_correction()
862 tap = word * TUNING_WORD_BIT_SIZE + bit; in tegra_sdhci_tap_correction()
867 first_fail_tap = tap; in tegra_sdhci_tap_correction()
872 start_pass_tap = tap; in tegra_sdhci_tap_correction()
875 first_pass_tap = tap; in tegra_sdhci_tap_correction()
881 end_pass_tap = tap - 1; in tegra_sdhci_tap_correction()
885 window = end_pass_tap - start_pass_tap; in tegra_sdhci_tap_correction()
888 start_pass_tap = tap; in tegra_sdhci_tap_correction()
891 /* set tap at middle of valid window */ in tegra_sdhci_tap_correction()
892 tap = start_pass_tap + window / 2; in tegra_sdhci_tap_correction()
893 tegra_host->tuned_tap_delay = tap; in tegra_sdhci_tap_correction()
905 /* set tap location at fixed tap relative to the first edge */ in tegra_sdhci_tap_correction()
906 edge1 = first_fail_tap + (first_pass_tap - first_fail_tap) / 2; in tegra_sdhci_tap_correction()
907 if (edge1 - 1 > fixed_tap) in tegra_sdhci_tap_correction()
908 tegra_host->tuned_tap_delay = edge1 - fixed_tap; in tegra_sdhci_tap_correction()
910 tegra_host->tuned_tap_delay = edge1 + fixed_tap; in tegra_sdhci_tap_correction()
918 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; in tegra_sdhci_post_tuning()
925 /* retain HW tuned tap to use incase if no correction is needed */ in tegra_sdhci_post_tuning()
927 tegra_host->tuned_tap_delay = (val & SDHCI_CLOCK_CTRL_TAP_MASK) >> in tegra_sdhci_post_tuning()
929 if (soc_data->min_tap_delay && soc_data->max_tap_delay) { in tegra_sdhci_post_tuning()
930 min_tap_dly = soc_data->min_tap_delay; in tegra_sdhci_post_tuning()
931 max_tap_dly = soc_data->max_tap_delay; in tegra_sdhci_post_tuning()
932 clk_rate_mhz = tegra_host->curr_clk_rate / USEC_PER_SEC; in tegra_sdhci_post_tuning()
943 * fixed tap is used when HW tuning result contains single edge in tegra_sdhci_post_tuning()
944 * and tap is set at fixed tap delay relative to the first edge in tegra_sdhci_post_tuning()
953 window_width = end_tap - start_tap; in tegra_sdhci_post_tuning()
954 num_iter = host->tuning_loop_count; in tegra_sdhci_post_tuning()
956 * partial window includes edges of the tuning range. in tegra_sdhci_post_tuning()
960 if (start_tap == 0 || (end_tap == (num_iter - 1)) || in tegra_sdhci_post_tuning()
961 (end_tap == num_iter - 2) || window_width >= thdupper) { in tegra_sdhci_post_tuning()
962 pr_debug("%s: Apply tuning correction\n", in tegra_sdhci_post_tuning()
963 mmc_hostname(host->mmc)); in tegra_sdhci_post_tuning()
969 tegra_sdhci_set_tap(host, tegra_host->tuned_tap_delay); in tegra_sdhci_post_tuning()
978 if (!err && !host->tuning_err) in tegra_sdhci_execute_hw_tuning()
995 tegra_host->ddr_signaling = false; in tegra_sdhci_set_uhs_signaling()
1001 /* Don't set default tap on tunable modes. */ in tegra_sdhci_set_uhs_signaling()
1011 tegra_host->ddr_signaling = true; in tegra_sdhci_set_uhs_signaling()
1029 host->tuning_loop_count = (iter == TRIES_128) ? 128 : 256; in tegra_sdhci_set_uhs_signaling()
1035 if (tegra_host->tuned_tap_delay && !set_default_tap) in tegra_sdhci_set_uhs_signaling()
1036 tegra_sdhci_set_tap(host, tegra_host->tuned_tap_delay); in tegra_sdhci_set_uhs_signaling()
1038 tegra_sdhci_set_tap(host, tegra_host->default_tap); in tegra_sdhci_set_uhs_signaling()
1041 tegra_sdhci_set_dqs_trim(host, tegra_host->dqs_trim); in tegra_sdhci_set_uhs_signaling()
1052 * Start search for minimum tap value at 10, as smaller values are in tegra_sdhci_execute_tuning()
1059 if (!mmc_send_tuning(host->mmc, opcode, NULL)) in tegra_sdhci_execute_tuning()
1064 /* Find the maximum tap value that still passes. */ in tegra_sdhci_execute_tuning()
1068 if (mmc_send_tuning(host->mmc, opcode, NULL)) { in tegra_sdhci_execute_tuning()
1069 max--; in tegra_sdhci_execute_tuning()
1075 /* The TRM states the ideal tap value is at 75% in the passing range. */ in tegra_sdhci_execute_tuning()
1076 tegra_sdhci_set_tap(host, min + ((max - min) * 3 / 4)); in tegra_sdhci_execute_tuning()
1078 return mmc_send_tuning(host->mmc, opcode, NULL); in tegra_sdhci_execute_tuning()
1089 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) { in sdhci_tegra_start_signal_voltage_switch()
1090 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, true); in sdhci_tegra_start_signal_voltage_switch()
1094 } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) { in sdhci_tegra_start_signal_voltage_switch()
1098 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, true); in sdhci_tegra_start_signal_voltage_switch()
1101 if (tegra_host->pad_calib_required) in sdhci_tegra_start_signal_voltage_switch()
1110 tegra_host->pinctrl_sdmmc = devm_pinctrl_get(dev); in tegra_sdhci_init_pinctrl_info()
1111 if (IS_ERR(tegra_host->pinctrl_sdmmc)) { in tegra_sdhci_init_pinctrl_info()
1113 PTR_ERR(tegra_host->pinctrl_sdmmc)); in tegra_sdhci_init_pinctrl_info()
1114 return -1; in tegra_sdhci_init_pinctrl_info()
1117 tegra_host->pinctrl_state_1v8_drv = pinctrl_lookup_state( in tegra_sdhci_init_pinctrl_info()
1118 tegra_host->pinctrl_sdmmc, "sdmmc-1v8-drv"); in tegra_sdhci_init_pinctrl_info()
1119 if (IS_ERR(tegra_host->pinctrl_state_1v8_drv)) { in tegra_sdhci_init_pinctrl_info()
1120 if (PTR_ERR(tegra_host->pinctrl_state_1v8_drv) == -ENODEV) in tegra_sdhci_init_pinctrl_info()
1121 tegra_host->pinctrl_state_1v8_drv = NULL; in tegra_sdhci_init_pinctrl_info()
1124 tegra_host->pinctrl_state_3v3_drv = pinctrl_lookup_state( in tegra_sdhci_init_pinctrl_info()
1125 tegra_host->pinctrl_sdmmc, "sdmmc-3v3-drv"); in tegra_sdhci_init_pinctrl_info()
1126 if (IS_ERR(tegra_host->pinctrl_state_3v3_drv)) { in tegra_sdhci_init_pinctrl_info()
1127 if (PTR_ERR(tegra_host->pinctrl_state_3v3_drv) == -ENODEV) in tegra_sdhci_init_pinctrl_info()
1128 tegra_host->pinctrl_state_3v3_drv = NULL; in tegra_sdhci_init_pinctrl_info()
1131 tegra_host->pinctrl_state_3v3 = in tegra_sdhci_init_pinctrl_info()
1132 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-3v3"); in tegra_sdhci_init_pinctrl_info()
1133 if (IS_ERR(tegra_host->pinctrl_state_3v3)) { in tegra_sdhci_init_pinctrl_info()
1135 PTR_ERR(tegra_host->pinctrl_state_3v3)); in tegra_sdhci_init_pinctrl_info()
1136 return -1; in tegra_sdhci_init_pinctrl_info()
1139 tegra_host->pinctrl_state_1v8 = in tegra_sdhci_init_pinctrl_info()
1140 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-1v8"); in tegra_sdhci_init_pinctrl_info()
1141 if (IS_ERR(tegra_host->pinctrl_state_1v8)) { in tegra_sdhci_init_pinctrl_info()
1143 PTR_ERR(tegra_host->pinctrl_state_1v8)); in tegra_sdhci_init_pinctrl_info()
1144 return -1; in tegra_sdhci_init_pinctrl_info()
1147 tegra_host->pad_control_available = true; in tegra_sdhci_init_pinctrl_info()
1156 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; in tegra_sdhci_voltage_switch()
1158 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) in tegra_sdhci_voltage_switch()
1159 tegra_host->pad_calib_required = true; in tegra_sdhci_voltage_switch()
1164 struct mmc_host *mmc = cq_host->mmc; in tegra_cqhci_writel()
1173 * to be re-configured. in tegra_cqhci_writel()
1182 writel(val, cq_host->mmio + reg); in tegra_cqhci_writel()
1195 writel(val, cq_host->mmio + reg); in tegra_cqhci_writel()
1197 writel(val, cq_host->mmio + reg); in tegra_cqhci_writel()
1206 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; in sdhci_tegra_update_dcmd_desc()
1208 if (soc_data->nvquirks & NVQUIRK_CQHCI_DCMD_R1B_CMD_TIMING && in sdhci_tegra_update_dcmd_desc()
1209 mrq->cmd->flags & MMC_RSP_R1B) in sdhci_tegra_update_dcmd_desc()
1215 struct cqhci_host *cq_host = mmc->cqe_private; in sdhci_tegra_cqe_enable()
1225 if (!cq_host->activated) { in sdhci_tegra_cqe_enable()
1261 cqhci_irq(host->mmc, intmask, cmd_error, data_error); in sdhci_tegra_cqhci_irq()
1285 if (cmd && cmd->busy_timeout >= 11 * MSEC_PER_SEC) in tegra_sdhci_set_timeout()
1296 struct cqhci_host *cq_host = mmc->cqe_private; in sdhci_tegra_cqe_pre_enable()
1306 struct cqhci_host *cq_host = mmc->cqe_private; in sdhci_tegra_cqe_post_disable()
1330 const struct sdhci_tegra_soc_data *soc = tegra->soc_data; in tegra_sdhci_set_dma_mask()
1331 struct device *dev = mmc_dev(host->mmc); in tegra_sdhci_set_dma_mask()
1333 if (soc->dma_mask) in tegra_sdhci_set_dma_mask()
1334 return dma_set_mask_and_coherent(dev, soc->dma_mask); in tegra_sdhci_set_dma_mask()
1380 * Auto-CMD23 leads to "Got command interrupt 0x00010000 even
1540 { .compatible = "nvidia,tegra194-sdhci", .data = &soc_data_tegra194 },
1541 { .compatible = "nvidia,tegra186-sdhci", .data = &soc_data_tegra186 },
1542 { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 },
1543 { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra124 },
1544 { .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 },
1545 { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 },
1546 { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 },
1559 if (!tegra_host->enable_hwcq) in sdhci_tegra_add_host()
1568 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; in sdhci_tegra_add_host()
1570 cq_host = devm_kzalloc(mmc_dev(host->mmc), in sdhci_tegra_add_host()
1573 ret = -ENOMEM; in sdhci_tegra_add_host()
1577 cq_host->mmio = host->ioaddr + SDHCI_TEGRA_CQE_BASE_ADDR; in sdhci_tegra_add_host()
1578 cq_host->ops = &sdhci_tegra_cqhci_ops; in sdhci_tegra_add_host()
1580 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; in sdhci_tegra_add_host()
1582 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; in sdhci_tegra_add_host()
1584 ret = cqhci_init(cq_host, host->mmc, dma64); in sdhci_tegra_add_host()
1609 match = of_match_device(sdhci_tegra_dt_match, &pdev->dev); in sdhci_tegra_probe()
1611 return -EINVAL; in sdhci_tegra_probe()
1612 soc_data = match->data; in sdhci_tegra_probe()
1614 host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*tegra_host)); in sdhci_tegra_probe()
1620 tegra_host->ddr_signaling = false; in sdhci_tegra_probe()
1621 tegra_host->pad_calib_required = false; in sdhci_tegra_probe()
1622 tegra_host->pad_control_available = false; in sdhci_tegra_probe()
1623 tegra_host->soc_data = soc_data; in sdhci_tegra_probe()
1625 if (soc_data->nvquirks & NVQUIRK_HAS_ANDROID_GPT_SECTOR) in sdhci_tegra_probe()
1626 host->mmc->caps2 |= MMC_CAP2_ALT_GPT_TEGRA; in sdhci_tegra_probe()
1628 if (soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL) { in sdhci_tegra_probe()
1629 rc = tegra_sdhci_init_pinctrl_info(&pdev->dev, tegra_host); in sdhci_tegra_probe()
1631 host->mmc_host_ops.start_signal_voltage_switch = in sdhci_tegra_probe()
1636 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) in sdhci_tegra_probe()
1637 host->mmc_host_ops.request = tegra_sdhci_request; in sdhci_tegra_probe()
1639 host->mmc_host_ops.hs400_enhanced_strobe = in sdhci_tegra_probe()
1642 if (!host->ops->platform_execute_tuning) in sdhci_tegra_probe()
1643 host->mmc_host_ops.execute_tuning = in sdhci_tegra_probe()
1646 rc = mmc_of_parse(host->mmc); in sdhci_tegra_probe()
1650 if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) in sdhci_tegra_probe()
1651 host->mmc->caps |= MMC_CAP_1_8V_DDR; in sdhci_tegra_probe()
1654 host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_NEED_RSP_BUSY; in sdhci_tegra_probe()
1658 tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power", in sdhci_tegra_probe()
1660 if (IS_ERR(tegra_host->power_gpio)) { in sdhci_tegra_probe()
1661 rc = PTR_ERR(tegra_host->power_gpio); in sdhci_tegra_probe()
1680 if (soc_data->nvquirks & NVQUIRK_HAS_TMCLK) { in sdhci_tegra_probe()
1681 clk = devm_clk_get(&pdev->dev, "tmclk"); in sdhci_tegra_probe()
1684 if (rc == -EPROBE_DEFER) in sdhci_tegra_probe()
1687 dev_warn(&pdev->dev, "failed to get tmclk: %d\n", rc); in sdhci_tegra_probe()
1694 dev_err(&pdev->dev, in sdhci_tegra_probe()
1699 tegra_host->tmclk = clk; in sdhci_tegra_probe()
1702 clk = devm_clk_get(mmc_dev(host->mmc), NULL); in sdhci_tegra_probe()
1704 rc = dev_err_probe(&pdev->dev, PTR_ERR(clk), in sdhci_tegra_probe()
1709 pltfm_host->clk = clk; in sdhci_tegra_probe()
1711 tegra_host->rst = devm_reset_control_get_exclusive(&pdev->dev, in sdhci_tegra_probe()
1713 if (IS_ERR(tegra_host->rst)) { in sdhci_tegra_probe()
1714 rc = PTR_ERR(tegra_host->rst); in sdhci_tegra_probe()
1715 dev_err(&pdev->dev, "failed to get reset control: %d\n", rc); in sdhci_tegra_probe()
1719 rc = reset_control_assert(tegra_host->rst); in sdhci_tegra_probe()
1725 rc = reset_control_deassert(tegra_host->rst); in sdhci_tegra_probe()
1738 reset_control_assert(tegra_host->rst); in sdhci_tegra_probe()
1740 clk_disable_unprepare(pltfm_host->clk); in sdhci_tegra_probe()
1742 clk_disable_unprepare(tegra_host->tmclk); in sdhci_tegra_probe()
1757 reset_control_assert(tegra_host->rst); in sdhci_tegra_remove()
1759 clk_disable_unprepare(pltfm_host->clk); in sdhci_tegra_remove()
1760 clk_disable_unprepare(tegra_host->tmclk); in sdhci_tegra_remove()
1774 if (host->mmc->caps2 & MMC_CAP2_CQE) { in sdhci_tegra_suspend()
1775 ret = cqhci_suspend(host->mmc); in sdhci_tegra_suspend()
1782 cqhci_resume(host->mmc); in sdhci_tegra_suspend()
1786 clk_disable_unprepare(pltfm_host->clk); in sdhci_tegra_suspend()
1796 ret = clk_prepare_enable(pltfm_host->clk); in sdhci_tegra_resume()
1804 if (host->mmc->caps2 & MMC_CAP2_CQE) { in sdhci_tegra_resume()
1805 ret = cqhci_resume(host->mmc); in sdhci_tegra_resume()
1815 clk_disable_unprepare(pltfm_host->clk); in sdhci_tegra_resume()
1825 .name = "sdhci-tegra",