156 	u32 scratch_32;  in o2_pci_set_baseclk()  local
159 			      O2_SD_PLL_SETTING, &scratch_32);  in o2_pci_set_baseclk()
161 	scratch_32 &= 0x0000FFFF;  in o2_pci_set_baseclk()
162 	scratch_32 |= value;  in o2_pci_set_baseclk()
165 			       O2_SD_PLL_SETTING, scratch_32);  in o2_pci_set_baseclk()
235 	u32 scratch_32 = 0;  in sdhci_o2_dll_recovery()  local
250 		scratch_32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);  in sdhci_o2_dll_recovery()
251 		scratch_32 |= O2_PLL_SOFT_RESET;  in sdhci_o2_dll_recovery()
252 		sdhci_writel(host, scratch_32, O2_PLL_DLL_WDT_CONTROL1);  in sdhci_o2_dll_recovery()
256 					    &scratch_32);  in sdhci_o2_dll_recovery()
258 		scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET;  in sdhci_o2_dll_recovery()
259 		pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG4, scratch_32);  in sdhci_o2_dll_recovery()
377 	u32 scratch_32;  in o2_pci_led_enable()  local
381 				    O2_SD_FUNC_REG0, &scratch_32);  in o2_pci_led_enable()
385 	scratch_32 &= ~O2_SD_FREG0_LEDOFF;  in o2_pci_led_enable()
387 			       O2_SD_FUNC_REG0, scratch_32);  in o2_pci_led_enable()
390 				    O2_SD_TEST_REG, &scratch_32);  in o2_pci_led_enable()
394 	scratch_32 |= O2_SD_LED_ENABLE;  in o2_pci_led_enable()
396 			       O2_SD_TEST_REG, scratch_32);  in o2_pci_led_enable()
401 	u32 scratch_32;  in sdhci_pci_o2_fujin2_pci_init()  local
404 	ret = pci_read_config_dword(chip->pdev, O2_SD_DEV_CTRL, &scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
407 	scratch_32 &= ~((1 << 12) | (1 << 13) | (1 << 14));  in sdhci_pci_o2_fujin2_pci_init()
408 	pci_write_config_dword(chip->pdev, O2_SD_DEV_CTRL, scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
411 	ret = pci_read_config_dword(chip->pdev, O2_SD_MISC_REG5, &scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
414 	scratch_32 &= ~((1 << 19) | (1 << 11));  in sdhci_pci_o2_fujin2_pci_init()
415 	scratch_32 |= (1 << 10);  in sdhci_pci_o2_fujin2_pci_init()
416 	pci_write_config_dword(chip->pdev, O2_SD_MISC_REG5, scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
419 	ret = pci_read_config_dword(chip->pdev, O2_SD_TEST_REG, &scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
422 	scratch_32 |= (1 << 4);  in sdhci_pci_o2_fujin2_pci_init()
423 	pci_write_config_dword(chip->pdev, O2_SD_TEST_REG, scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
429 	ret = pci_read_config_dword(chip->pdev, O2_SD_LD0_CTRL, &scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
432 	scratch_32 &= ~(3 << 12);  in sdhci_pci_o2_fujin2_pci_init()
433 	pci_write_config_dword(chip->pdev, O2_SD_LD0_CTRL, scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
436 	ret = pci_read_config_dword(chip->pdev, O2_SD_CAP_REG0, &scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
439 	scratch_32 &= ~(0x01FE);  in sdhci_pci_o2_fujin2_pci_init()
440 	scratch_32 |= 0x00CC;  in sdhci_pci_o2_fujin2_pci_init()
441 	pci_write_config_dword(chip->pdev, O2_SD_CAP_REG0, scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
444 				    O2_SD_TUNING_CTRL, &scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
447 	scratch_32 &= ~(0x000000FF);  in sdhci_pci_o2_fujin2_pci_init()
448 	scratch_32 |= 0x00000066;  in sdhci_pci_o2_fujin2_pci_init()
449 	pci_write_config_dword(chip->pdev, O2_SD_TUNING_CTRL, scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
453 				    O2_SD_UHS2_L1_CTRL, &scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
456 	scratch_32 &= ~(0x000000FC);  in sdhci_pci_o2_fujin2_pci_init()
457 	scratch_32 |= 0x00000084;  in sdhci_pci_o2_fujin2_pci_init()
458 	pci_write_config_dword(chip->pdev, O2_SD_UHS2_L1_CTRL, scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
461 	ret = pci_read_config_dword(chip->pdev, O2_SD_FUNC_REG3, &scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
464 	scratch_32 &= ~((1 << 21) | (1 << 30));  in sdhci_pci_o2_fujin2_pci_init()
466 	pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG3, scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
469 	ret = pci_read_config_dword(chip->pdev, O2_SD_CAPS, &scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
472 	scratch_32 &= ~(0xf0000000);  in sdhci_pci_o2_fujin2_pci_init()
473 	scratch_32 |= 0x30000000;  in sdhci_pci_o2_fujin2_pci_init()
474 	pci_write_config_dword(chip->pdev, O2_SD_CAPS, scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
477 				    O2_SD_MISC_CTRL4, &scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
480 	scratch_32 &= ~(0x000f0000);  in sdhci_pci_o2_fujin2_pci_init()
481 	scratch_32 |= 0x00080000;  in sdhci_pci_o2_fujin2_pci_init()
482 	pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL4, scratch_32);  in sdhci_pci_o2_fujin2_pci_init()
525 	u32 scratch_32;  in sdhci_pci_o2_set_clock()  local
542 		pci_read_config_dword(chip->pdev, O2_SD_PLL_SETTING, &scratch_32);  in sdhci_pci_o2_set_clock()
544 		if ((scratch_32 & 0xFFFF0000) != 0x2c280000)  in sdhci_pci_o2_set_clock()
636 	u32 scratch_32;  in sdhci_pci_o2_probe()  local
708 						    &scratch_32);  in sdhci_pci_o2_probe()
711 			scratch_32 = ((scratch_32 & 0xFF000000) >> 24);  in sdhci_pci_o2_probe()
714 			if ((scratch_32 == 0x11) || (scratch_32 == 0x12)) {  in sdhci_pci_o2_probe()
715 				scratch_32 = 0x25100000;  in sdhci_pci_o2_probe()
717 				o2_pci_set_baseclk(chip, scratch_32);  in sdhci_pci_o2_probe()
720 							    &scratch_32);  in sdhci_pci_o2_probe()
725 				scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET;  in sdhci_pci_o2_probe()
728 						       scratch_32);  in sdhci_pci_o2_probe()
743 					    O2_SD_CLK_SETTING, &scratch_32);  in sdhci_pci_o2_probe()
747 		scratch_32 &= ~(0xFF00);  in sdhci_pci_o2_probe()
748 		scratch_32 |= 0x07E0C800;  in sdhci_pci_o2_probe()
750 				       O2_SD_CLK_SETTING, scratch_32);  in sdhci_pci_o2_probe()
753 					    O2_SD_CLKREQ, &scratch_32);  in sdhci_pci_o2_probe()
756 		scratch_32 |= 0x3;  in sdhci_pci_o2_probe()
757 		pci_write_config_dword(chip->pdev, O2_SD_CLKREQ, scratch_32);  in sdhci_pci_o2_probe()
760 					    O2_SD_PLL_SETTING, &scratch_32);  in sdhci_pci_o2_probe()
764 		scratch_32 &= ~(0x1F3F070E);  in sdhci_pci_o2_probe()
765 		scratch_32 |= 0x18270106;  in sdhci_pci_o2_probe()
767 				       O2_SD_PLL_SETTING, scratch_32);  in sdhci_pci_o2_probe()
771 					    O2_SD_CAP_REG2, &scratch_32);  in sdhci_pci_o2_probe()
774 		scratch_32 &= ~(0xE0);  in sdhci_pci_o2_probe()
776 				       O2_SD_CAP_REG2, scratch_32);  in sdhci_pci_o2_probe()
801 					    O2_SD_PLL_SETTING, &scratch_32);  in sdhci_pci_o2_probe()
805 		if ((scratch_32 & 0xff000000) == 0x01000000) {  in sdhci_pci_o2_probe()
806 			scratch_32 &= 0x0000FFFF;  in sdhci_pci_o2_probe()
807 			scratch_32 |= 0x1F340000;  in sdhci_pci_o2_probe()
810 					       O2_SD_PLL_SETTING, scratch_32);  in sdhci_pci_o2_probe()
812 			scratch_32 &= 0x0000FFFF;  in sdhci_pci_o2_probe()
813 			scratch_32 |= 0x25100000;  in sdhci_pci_o2_probe()
816 					       O2_SD_PLL_SETTING, scratch_32);  in sdhci_pci_o2_probe()
820 						    &scratch_32);  in sdhci_pci_o2_probe()
823 			scratch_32 |= (1 << 22);  in sdhci_pci_o2_probe()
825 					       O2_SD_FUNC_REG4, scratch_32);  in sdhci_pci_o2_probe()