Lines Matching +full:keembay +full:- +full:emmc +full:- +full:phy
1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>
9 * Based on sdhci-of-esdhc.c
18 #include <linux/clk-provider.h>
22 #include <linux/phy/phy.h>
25 #include <linux/firmware/xlnx-zynqmp.h>
28 #include "sdhci-pltfm.h"
55 * On some SoCs the syscon area has a feature where the upper 16-bits of
56 * each 32-bit register act as a write mask for the lower 16-bits. This allows
64 * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map
68 * @shift: Bit offset within @reg of this field (or -1 if not avail)
77 * struct sdhci_arasan_soc_ctl_map - Map in syscon to corecfg registers
96 * struct sdhci_arasan_clk_ops - Clock Operations for Arasan SD controller
107 * struct sdhci_arasan_clk_data - Arasan Controller Clock Data.
109 * @sdcardclk_hw: Struct for the clock we might provide to a PHY.
111 * @sampleclk_hw: Struct for the clock we might provide to a PHY.
130 * struct sdhci_arasan_data - Arasan Controller Data
134 * @phy: Pointer to the generic phy
135 * @is_phy_on: True if the PHY is on; false if not.
146 struct phy *phy; member
184 .clockmultiplier = { .reg = 0, .width = -1, .shift = -1 },
190 .clockmultiplier = { .reg = 0, .width = -1, .shift = -1 },
202 * sdhci_arasan_syscon_write - Write to a field in soc_ctl registers
221 struct regmap *soc_ctl_base = sdhci_arasan->soc_ctl_base; in sdhci_arasan_syscon_write()
222 u32 reg = fld->reg; in sdhci_arasan_syscon_write()
223 u16 width = fld->width; in sdhci_arasan_syscon_write()
224 s16 shift = fld->shift; in sdhci_arasan_syscon_write()
234 return -EINVAL; in sdhci_arasan_syscon_write()
236 if (sdhci_arasan->soc_ctl_map->hiword_update) in sdhci_arasan_syscon_write()
248 mmc_hostname(host->mmc), ret); in sdhci_arasan_syscon_write()
257 struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data; in sdhci_arasan_set_clock()
260 if (!IS_ERR(sdhci_arasan->phy)) { in sdhci_arasan_set_clock()
261 if (!sdhci_arasan->is_phy_on && clock <= PHY_CLK_TOO_SLOW_HZ) { in sdhci_arasan_set_clock()
263 * If PHY off, set clock to max speed and power PHY on. in sdhci_arasan_set_clock()
265 * Although PHY docs apparently suggest power cycling in sdhci_arasan_set_clock()
266 * when changing the clock the PHY doesn't like to be in sdhci_arasan_set_clock()
268 * mode. Even worse is powering the PHY on while the in sdhci_arasan_set_clock()
271 * To workaround the PHY limitations, the best we can in sdhci_arasan_set_clock()
275 sdhci_set_clock(host, host->max_clk); in sdhci_arasan_set_clock()
276 if (phy_power_on(sdhci_arasan->phy)) { in sdhci_arasan_set_clock()
277 pr_err("%s: Cannot power on phy.\n", in sdhci_arasan_set_clock()
278 mmc_hostname(host->mmc)); in sdhci_arasan_set_clock()
282 sdhci_arasan->is_phy_on = true; in sdhci_arasan_set_clock()
291 * At higher clock speeds the PHY is fine being power in sdhci_arasan_set_clock()
299 if (ctrl_phy && sdhci_arasan->is_phy_on) { in sdhci_arasan_set_clock()
300 phy_power_off(sdhci_arasan->phy); in sdhci_arasan_set_clock()
301 sdhci_arasan->is_phy_on = false; in sdhci_arasan_set_clock()
304 if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_CLOCK_25_BROKEN) { in sdhci_arasan_set_clock()
315 if (clk_data->set_clk_delays) in sdhci_arasan_set_clock()
316 clk_data->set_clk_delays(host); in sdhci_arasan_set_clock()
320 if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE) in sdhci_arasan_set_clock()
331 if (phy_power_on(sdhci_arasan->phy)) { in sdhci_arasan_set_clock()
332 pr_err("%s: Cannot power on phy.\n", in sdhci_arasan_set_clock()
333 mmc_hostname(host->mmc)); in sdhci_arasan_set_clock()
337 sdhci_arasan->is_phy_on = true; in sdhci_arasan_set_clock()
348 if (ios->enhanced_strobe) in sdhci_arasan_hs400_enhanced_strobe()
364 if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_FORCE_CDTEST) { in sdhci_arasan_reset()
374 switch (ios->signal_voltage) { in sdhci_arasan_voltage_switch()
390 return -EINVAL; in sdhci_arasan_voltage_switch()
411 cqhci_irq(host->mmc, intmask, cmd_error, data_error); in sdhci_arasan_cqhci_irq()
461 * sdhci_arasan_suspend - Suspend method for the driver
475 if (host->tuning_mode != SDHCI_TUNING_MODE_3) in sdhci_arasan_suspend()
476 mmc_retune_needed(host->mmc); in sdhci_arasan_suspend()
478 if (sdhci_arasan->has_cqe) { in sdhci_arasan_suspend()
479 ret = cqhci_suspend(host->mmc); in sdhci_arasan_suspend()
488 if (!IS_ERR(sdhci_arasan->phy) && sdhci_arasan->is_phy_on) { in sdhci_arasan_suspend()
489 ret = phy_power_off(sdhci_arasan->phy); in sdhci_arasan_suspend()
491 dev_err(dev, "Cannot power off phy.\n"); in sdhci_arasan_suspend()
497 sdhci_arasan->is_phy_on = false; in sdhci_arasan_suspend()
500 clk_disable(pltfm_host->clk); in sdhci_arasan_suspend()
501 clk_disable(sdhci_arasan->clk_ahb); in sdhci_arasan_suspend()
507 * sdhci_arasan_resume - Resume method for the driver
521 ret = clk_enable(sdhci_arasan->clk_ahb); in sdhci_arasan_resume()
527 ret = clk_enable(pltfm_host->clk); in sdhci_arasan_resume()
533 if (!IS_ERR(sdhci_arasan->phy) && host->mmc->actual_clock) { in sdhci_arasan_resume()
534 ret = phy_power_on(sdhci_arasan->phy); in sdhci_arasan_resume()
536 dev_err(dev, "Cannot power on phy.\n"); in sdhci_arasan_resume()
539 sdhci_arasan->is_phy_on = true; in sdhci_arasan_resume()
548 if (sdhci_arasan->has_cqe) in sdhci_arasan_resume()
549 return cqhci_resume(host->mmc); in sdhci_arasan_resume()
559 * sdhci_arasan_sdcardclk_recalc_rate - Return the card clock rate
565 * to communicate with out PHY.
576 struct sdhci_host *host = sdhci_arasan->host; in sdhci_arasan_sdcardclk_recalc_rate()
578 return host->mmc->actual_clock; in sdhci_arasan_sdcardclk_recalc_rate()
586 * sdhci_arasan_sampleclk_recalc_rate - Return the sampling clock rate
592 * to communicate with out PHY.
603 struct sdhci_host *host = sdhci_arasan->host; in sdhci_arasan_sampleclk_recalc_rate()
605 return host->mmc->actual_clock; in sdhci_arasan_sampleclk_recalc_rate()
613 * sdhci_zynqmp_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
616 * @degrees: The clock phase shift between 0 - 359.
628 struct sdhci_host *host = sdhci_arasan->host; in sdhci_zynqmp_sdcardclk_set_phase()
635 if (host->version < SDHCI_SPEC_300) in sdhci_zynqmp_sdcardclk_set_phase()
638 switch (host->timing) { in sdhci_zynqmp_sdcardclk_set_phase()
679 * sdhci_zynqmp_sampleclk_set_phase - Set the SD Input Clock Tap Delays
682 * @degrees: The clock phase shift between 0 - 359.
694 struct sdhci_host *host = sdhci_arasan->host; in sdhci_zynqmp_sampleclk_set_phase()
701 if (host->version < SDHCI_SPEC_300) in sdhci_zynqmp_sampleclk_set_phase()
707 switch (host->timing) { in sdhci_zynqmp_sampleclk_set_phase()
745 * sdhci_versal_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
748 * @degrees: The clock phase shift between 0 - 359.
760 struct sdhci_host *host = sdhci_arasan->host; in sdhci_versal_sdcardclk_set_phase()
764 if (host->version < SDHCI_SPEC_300) in sdhci_versal_sdcardclk_set_phase()
767 switch (host->timing) { in sdhci_versal_sdcardclk_set_phase()
812 * sdhci_versal_sampleclk_set_phase - Set the SD Input Clock Tap Delays
815 * @degrees: The clock phase shift between 0 - 359.
827 struct sdhci_host *host = sdhci_arasan->host; in sdhci_versal_sampleclk_set_phase()
831 if (host->version < SDHCI_SPEC_300) in sdhci_versal_sampleclk_set_phase()
834 switch (host->timing) { in sdhci_versal_sampleclk_set_phase()
903 struct clk_hw *hw = &sdhci_arasan->clk_data.sdcardclk_hw; in arasan_zynqmp_execute_tuning()
910 if (mmc->ios.timing == MMC_TIMING_UHS_DDR50) in arasan_zynqmp_execute_tuning()
925 * sdhci_arasan_update_clockmultiplier - Set corecfg_clockmultiplier
934 * - Many existing devices don't seem to do this and work fine. To keep
938 * - The value of corecfg_clockmultiplier should sync with that of corresponding
948 sdhci_arasan->soc_ctl_map; in sdhci_arasan_update_clockmultiplier()
955 if (!sdhci_arasan->soc_ctl_base) { in sdhci_arasan_update_clockmultiplier()
956 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n", in sdhci_arasan_update_clockmultiplier()
957 mmc_hostname(host->mmc)); in sdhci_arasan_update_clockmultiplier()
961 sdhci_arasan_syscon_write(host, &soc_ctl_map->clockmultiplier, value); in sdhci_arasan_update_clockmultiplier()
965 * sdhci_arasan_update_baseclkfreq - Set corecfg_baseclkfreq
973 * - Many existing devices don't seem to do this and work fine. To keep
977 * - It's assumed that clk_xin is not dynamic and that we use the SDHCI divider
986 sdhci_arasan->soc_ctl_map; in sdhci_arasan_update_baseclkfreq()
987 u32 mhz = DIV_ROUND_CLOSEST_ULL(clk_get_rate(pltfm_host->clk), 1000000); in sdhci_arasan_update_baseclkfreq()
994 if (!sdhci_arasan->soc_ctl_base) { in sdhci_arasan_update_baseclkfreq()
995 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n", in sdhci_arasan_update_baseclkfreq()
996 mmc_hostname(host->mmc)); in sdhci_arasan_update_baseclkfreq()
1000 sdhci_arasan_syscon_write(host, &soc_ctl_map->baseclkfreq, mhz); in sdhci_arasan_update_baseclkfreq()
1007 struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data; in sdhci_arasan_set_clk_delays()
1009 clk_set_phase(clk_data->sampleclk, in sdhci_arasan_set_clk_delays()
1010 clk_data->clk_phase_in[host->timing]); in sdhci_arasan_set_clk_delays()
1011 clk_set_phase(clk_data->sdcardclk, in sdhci_arasan_set_clk_delays()
1012 clk_data->clk_phase_out[host->timing]); in sdhci_arasan_set_clk_delays()
1019 struct device_node *np = dev->of_node; in arasan_dt_read_clk_phase()
1026 * Tap Values then use the pre-defined values. in arasan_dt_read_clk_phase()
1032 prop, clk_data->clk_phase_in[timing], in arasan_dt_read_clk_phase()
1033 clk_data->clk_phase_out[timing]); in arasan_dt_read_clk_phase()
1038 clk_data->clk_phase_in[timing] = clk_phase[0]; in arasan_dt_read_clk_phase()
1039 clk_data->clk_phase_out[timing] = clk_phase[1]; in arasan_dt_read_clk_phase()
1043 * arasan_dt_parse_clk_phases - Read Clock Delay values from DT
1061 clk_data->set_clk_delays = sdhci_arasan_set_clk_delays; in arasan_dt_parse_clk_phases()
1063 if (of_device_is_compatible(dev->of_node, "xlnx,zynqmp-8.9a")) { in arasan_dt_parse_clk_phases()
1069 of_property_read_u32(dev->of_node, "xlnx,mio-bank", &mio_bank); in arasan_dt_parse_clk_phases()
1076 clk_data->clk_phase_in[i] = zynqmp_iclk_phase[i]; in arasan_dt_parse_clk_phases()
1077 clk_data->clk_phase_out[i] = zynqmp_oclk_phase[i]; in arasan_dt_parse_clk_phases()
1081 if (of_device_is_compatible(dev->of_node, "xlnx,versal-8.9a")) { in arasan_dt_parse_clk_phases()
1088 clk_data->clk_phase_in[i] = versal_iclk_phase[i]; in arasan_dt_parse_clk_phases()
1089 clk_data->clk_phase_out[i] = versal_oclk_phase[i]; in arasan_dt_parse_clk_phases()
1094 "clk-phase-legacy"); in arasan_dt_parse_clk_phases()
1096 "clk-phase-mmc-hs"); in arasan_dt_parse_clk_phases()
1098 "clk-phase-sd-hs"); in arasan_dt_parse_clk_phases()
1100 "clk-phase-uhs-sdr12"); in arasan_dt_parse_clk_phases()
1102 "clk-phase-uhs-sdr25"); in arasan_dt_parse_clk_phases()
1104 "clk-phase-uhs-sdr50"); in arasan_dt_parse_clk_phases()
1106 "clk-phase-uhs-sdr104"); in arasan_dt_parse_clk_phases()
1108 "clk-phase-uhs-ddr50"); in arasan_dt_parse_clk_phases()
1110 "clk-phase-mmc-ddr52"); in arasan_dt_parse_clk_phases()
1112 "clk-phase-mmc-hs200"); in arasan_dt_parse_clk_phases()
1114 "clk-phase-mmc-hs400"); in arasan_dt_parse_clk_phases()
1243 /* SoC-specific compatible strings w/ soc_ctl_map */
1245 .compatible = "rockchip,rk3399-sdhci-5.1",
1249 .compatible = "intel,lgm-sdhci-5.1-emmc",
1253 .compatible = "intel,lgm-sdhci-5.1-sdxc",
1257 .compatible = "intel,keembay-sdhci-5.1-emmc",
1261 .compatible = "intel,keembay-sdhci-5.1-sd",
1265 .compatible = "intel,keembay-sdhci-5.1-sdio",
1270 .compatible = "arasan,sdhci-8.9a",
1274 .compatible = "arasan,sdhci-5.1",
1278 .compatible = "arasan,sdhci-4.9a",
1282 .compatible = "xlnx,zynqmp-8.9a",
1286 .compatible = "xlnx,versal-8.9a",
1294 * sdhci_arasan_register_sdcardclk - Register the sdcardclk for a PHY to use
1300 * Some PHY devices need to know what the actual card clock is. In order for
1311 struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data; in sdhci_arasan_register_sdcardclk()
1312 struct device_node *np = dev->of_node; in sdhci_arasan_register_sdcardclk()
1317 ret = of_property_read_string_index(np, "clock-output-names", 0, in sdhci_arasan_register_sdcardclk()
1320 dev_err(dev, "DT has #clock-cells but no clock-output-names\n"); in sdhci_arasan_register_sdcardclk()
1328 sdcardclk_init.ops = sdhci_arasan->clk_ops->sdcardclk_ops; in sdhci_arasan_register_sdcardclk()
1330 clk_data->sdcardclk_hw.init = &sdcardclk_init; in sdhci_arasan_register_sdcardclk()
1331 clk_data->sdcardclk = in sdhci_arasan_register_sdcardclk()
1332 devm_clk_register(dev, &clk_data->sdcardclk_hw); in sdhci_arasan_register_sdcardclk()
1333 if (IS_ERR(clk_data->sdcardclk)) in sdhci_arasan_register_sdcardclk()
1334 return PTR_ERR(clk_data->sdcardclk); in sdhci_arasan_register_sdcardclk()
1335 clk_data->sdcardclk_hw.init = NULL; in sdhci_arasan_register_sdcardclk()
1338 clk_data->sdcardclk); in sdhci_arasan_register_sdcardclk()
1346 * sdhci_arasan_register_sampleclk - Register the sampleclk for a PHY to use
1352 * Some PHY devices need to know what the actual card clock is. In order for
1363 struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data; in sdhci_arasan_register_sampleclk()
1364 struct device_node *np = dev->of_node; in sdhci_arasan_register_sampleclk()
1369 ret = of_property_read_string_index(np, "clock-output-names", 1, in sdhci_arasan_register_sampleclk()
1372 dev_err(dev, "DT has #clock-cells but no clock-output-names\n"); in sdhci_arasan_register_sampleclk()
1380 sampleclk_init.ops = sdhci_arasan->clk_ops->sampleclk_ops; in sdhci_arasan_register_sampleclk()
1382 clk_data->sampleclk_hw.init = &sampleclk_init; in sdhci_arasan_register_sampleclk()
1383 clk_data->sampleclk = in sdhci_arasan_register_sampleclk()
1384 devm_clk_register(dev, &clk_data->sampleclk_hw); in sdhci_arasan_register_sampleclk()
1385 if (IS_ERR(clk_data->sampleclk)) in sdhci_arasan_register_sampleclk()
1386 return PTR_ERR(clk_data->sampleclk); in sdhci_arasan_register_sampleclk()
1387 clk_data->sampleclk_hw.init = NULL; in sdhci_arasan_register_sampleclk()
1390 clk_data->sampleclk); in sdhci_arasan_register_sampleclk()
1398 * sdhci_arasan_unregister_sdclk - Undoes sdhci_arasan_register_sdclk()
1407 struct device_node *np = dev->of_node; in sdhci_arasan_unregister_sdclk()
1409 if (!of_find_property(np, "#clock-cells", NULL)) in sdhci_arasan_unregister_sdclk()
1412 of_clk_del_provider(dev->of_node); in sdhci_arasan_unregister_sdclk()
1416 * sdhci_arasan_update_support64b - Set SUPPORT_64B (64-bit System Bus Support)
1421 * 0: the Core supports only 32-bit System Address Bus.
1422 * 1: the Core supports 64-bit System Address Bus.
1426 * Keem Bay does not support 64-bit access.
1435 soc_ctl_map = sdhci_arasan->soc_ctl_map; in sdhci_arasan_update_support64b()
1440 if (!sdhci_arasan->soc_ctl_base) { in sdhci_arasan_update_support64b()
1441 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n", in sdhci_arasan_update_support64b()
1442 mmc_hostname(host->mmc)); in sdhci_arasan_update_support64b()
1446 sdhci_arasan_syscon_write(host, &soc_ctl_map->support64b, value); in sdhci_arasan_update_support64b()
1450 * sdhci_arasan_register_sdclk - Register the sdcardclk for a PHY to use
1456 * Some PHY devices need to know what the actual card clock is. In order for
1460 * Note: without seriously re-architecting SDHCI's clock code and testing on
1466 * re-architecting SDHCI if we see some benefit to it.
1474 struct device_node *np = dev->of_node; in sdhci_arasan_register_sdclk()
1478 /* Providing a clock to the PHY is optional; no error if missing */ in sdhci_arasan_register_sdclk()
1479 if (of_property_read_u32(np, "#clock-cells", &num_clks) < 0) in sdhci_arasan_register_sdclk()
1500 struct sdhci_host *host = sdhci_arasan->host; in sdhci_arasan_add_host()
1505 if (!sdhci_arasan->has_cqe) in sdhci_arasan_add_host()
1512 cq_host = devm_kzalloc(host->mmc->parent, in sdhci_arasan_add_host()
1515 ret = -ENOMEM; in sdhci_arasan_add_host()
1519 cq_host->mmio = host->ioaddr + SDHCI_ARASAN_CQE_BASE_ADDR; in sdhci_arasan_add_host()
1520 cq_host->ops = &sdhci_arasan_cqhci_ops; in sdhci_arasan_add_host()
1522 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; in sdhci_arasan_add_host()
1524 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; in sdhci_arasan_add_host()
1526 ret = cqhci_init(cq_host, host->mmc, dma64); in sdhci_arasan_add_host()
1548 struct device *dev = &pdev->dev; in sdhci_arasan_probe()
1549 struct device_node *np = dev->of_node; in sdhci_arasan_probe()
1554 host = sdhci_pltfm_init(pdev, data->pdata, sizeof(*sdhci_arasan)); in sdhci_arasan_probe()
1561 sdhci_arasan->host = host; in sdhci_arasan_probe()
1563 sdhci_arasan->soc_ctl_map = data->soc_ctl_map; in sdhci_arasan_probe()
1564 sdhci_arasan->clk_ops = data->clk_ops; in sdhci_arasan_probe()
1566 node = of_parse_phandle(np, "arasan,soc-ctl-syscon", 0); in sdhci_arasan_probe()
1568 sdhci_arasan->soc_ctl_base = syscon_node_to_regmap(node); in sdhci_arasan_probe()
1571 if (IS_ERR(sdhci_arasan->soc_ctl_base)) { in sdhci_arasan_probe()
1573 PTR_ERR(sdhci_arasan->soc_ctl_base), in sdhci_arasan_probe()
1581 sdhci_arasan->clk_ahb = devm_clk_get(dev, "clk_ahb"); in sdhci_arasan_probe()
1582 if (IS_ERR(sdhci_arasan->clk_ahb)) { in sdhci_arasan_probe()
1583 ret = dev_err_probe(dev, PTR_ERR(sdhci_arasan->clk_ahb), in sdhci_arasan_probe()
1594 ret = clk_prepare_enable(sdhci_arasan->clk_ahb); in sdhci_arasan_probe()
1600 /* If clock-frequency property is set, use the provided value */ in sdhci_arasan_probe()
1601 if (pltfm_host->clock && in sdhci_arasan_probe()
1602 pltfm_host->clock != clk_get_rate(clk_xin)) { in sdhci_arasan_probe()
1603 ret = clk_set_rate(clk_xin, pltfm_host->clock); in sdhci_arasan_probe()
1605 dev_err(&pdev->dev, "Failed to set SD clock rate\n"); in sdhci_arasan_probe()
1616 if (of_property_read_bool(np, "xlnx,fails-without-test-cd")) in sdhci_arasan_probe()
1617 sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_FORCE_CDTEST; in sdhci_arasan_probe()
1619 if (of_property_read_bool(np, "xlnx,int-clock-stable-broken")) in sdhci_arasan_probe()
1620 sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE; in sdhci_arasan_probe()
1622 pltfm_host->clk = clk_xin; in sdhci_arasan_probe()
1624 if (of_device_is_compatible(np, "rockchip,rk3399-sdhci-5.1")) in sdhci_arasan_probe()
1627 if (of_device_is_compatible(np, "intel,keembay-sdhci-5.1-emmc") || in sdhci_arasan_probe()
1628 of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sd") || in sdhci_arasan_probe()
1629 of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sdio")) { in sdhci_arasan_probe()
1633 host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; in sdhci_arasan_probe()
1642 if (of_device_is_compatible(np, "xlnx,zynqmp-8.9a")) { in sdhci_arasan_probe()
1643 host->mmc_host_ops.execute_tuning = in sdhci_arasan_probe()
1646 sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_CLOCK_25_BROKEN; in sdhci_arasan_probe()
1647 host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12; in sdhci_arasan_probe()
1650 arasan_dt_parse_clk_phases(dev, &sdhci_arasan->clk_data); in sdhci_arasan_probe()
1652 ret = mmc_of_parse(host->mmc); in sdhci_arasan_probe()
1658 sdhci_arasan->phy = ERR_PTR(-ENODEV); in sdhci_arasan_probe()
1659 if (of_device_is_compatible(np, "arasan,sdhci-5.1")) { in sdhci_arasan_probe()
1660 sdhci_arasan->phy = devm_phy_get(dev, "phy_arasan"); in sdhci_arasan_probe()
1661 if (IS_ERR(sdhci_arasan->phy)) { in sdhci_arasan_probe()
1662 ret = dev_err_probe(dev, PTR_ERR(sdhci_arasan->phy), in sdhci_arasan_probe()
1663 "No phy for arasan,sdhci-5.1.\n"); in sdhci_arasan_probe()
1667 ret = phy_init(sdhci_arasan->phy); in sdhci_arasan_probe()
1673 host->mmc_host_ops.hs400_enhanced_strobe = in sdhci_arasan_probe()
1675 host->mmc_host_ops.start_signal_voltage_switch = in sdhci_arasan_probe()
1677 sdhci_arasan->has_cqe = true; in sdhci_arasan_probe()
1678 host->mmc->caps2 |= MMC_CAP2_CQE; in sdhci_arasan_probe()
1680 if (!of_property_read_bool(np, "disable-cqe-dcmd")) in sdhci_arasan_probe()
1681 host->mmc->caps2 |= MMC_CAP2_CQE_DCMD; in sdhci_arasan_probe()
1691 if (!IS_ERR(sdhci_arasan->phy)) in sdhci_arasan_probe()
1692 phy_exit(sdhci_arasan->phy); in sdhci_arasan_probe()
1698 clk_disable_unprepare(sdhci_arasan->clk_ahb); in sdhci_arasan_probe()
1710 struct clk *clk_ahb = sdhci_arasan->clk_ahb; in sdhci_arasan_remove()
1712 if (!IS_ERR(sdhci_arasan->phy)) { in sdhci_arasan_remove()
1713 if (sdhci_arasan->is_phy_on) in sdhci_arasan_remove()
1714 phy_power_off(sdhci_arasan->phy); in sdhci_arasan_remove()
1715 phy_exit(sdhci_arasan->phy); in sdhci_arasan_remove()
1718 sdhci_arasan_unregister_sdclk(&pdev->dev); in sdhci_arasan_remove()
1729 .name = "sdhci-arasan",