Lines Matching +full:full +full:- +full:pwr +full:- +full:cycle
1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver
5 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
21 #include "sdhci-pltfm.h"
120 #define INVALID_TUNING_PHASE -1
134 /* Max load for eMMC Vdd-io supply */
138 msm_host->var_ops->msm_readl_relaxed(host, offset)
141 msm_host->var_ops->msm_writel_relaxed(val, host, offset)
295 return msm_host->offset; in sdhci_priv_msm_offset()
308 return readl_relaxed(msm_host->core_mem + offset); in sdhci_msm_mci_variant_readl_relaxed()
314 return readl_relaxed(host->ioaddr + offset); in sdhci_msm_v5_variant_readl_relaxed()
323 writel_relaxed(val, msm_host->core_mem + offset); in sdhci_msm_mci_variant_writel_relaxed()
329 writel_relaxed(val, host->ioaddr + offset); in sdhci_msm_v5_variant_writel_relaxed()
334 struct mmc_ios ios = host->mmc->ios; in msm_get_clock_mult_for_bus_mode()
344 host->flags & SDHCI_HS400_TUNING) in msm_get_clock_mult_for_bus_mode()
354 struct mmc_ios curr_ios = host->mmc->ios; in msm_set_clock_rate_for_bus_mode()
355 struct clk *core_clk = msm_host->bulk_clks[0].clk; in msm_set_clock_rate_for_bus_mode()
363 rc = dev_pm_opp_set_rate(mmc_dev(host->mmc), desired_rate); in msm_set_clock_rate_for_bus_mode()
366 mmc_hostname(host->mmc), desired_rate, curr_ios.timing); in msm_set_clock_rate_for_bus_mode()
378 mmc_hostname(host->mmc), desired_rate, achieved_rate); in msm_set_clock_rate_for_bus_mode()
379 host->mmc->actual_clock = achieved_rate / mult; in msm_set_clock_rate_for_bus_mode()
382 msm_host->clk_rate = desired_rate; in msm_set_clock_rate_for_bus_mode()
385 mmc_hostname(host->mmc), achieved_rate, curr_ios.timing); in msm_set_clock_rate_for_bus_mode()
393 struct mmc_host *mmc = host->mmc; in msm_dll_poll_ck_out_en()
398 ck_out_en = !!(readl_relaxed(host->ioaddr + in msm_dll_poll_ck_out_en()
399 msm_offset->core_dll_config) & CORE_CK_OUT_EN); in msm_dll_poll_ck_out_en()
402 if (--wait_cnt == 0) { in msm_dll_poll_ck_out_en()
405 return -ETIMEDOUT; in msm_dll_poll_ck_out_en()
409 ck_out_en = !!(readl_relaxed(host->ioaddr + in msm_dll_poll_ck_out_en()
410 msm_offset->core_dll_config) & CORE_CK_OUT_EN); in msm_dll_poll_ck_out_en()
425 struct mmc_host *mmc = host->mmc; in msm_config_cm_dll_phase()
430 return -EINVAL; in msm_config_cm_dll_phase()
432 spin_lock_irqsave(&host->lock, flags); in msm_config_cm_dll_phase()
434 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config); in msm_config_cm_dll_phase()
437 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config); in msm_config_cm_dll_phase()
448 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config); in msm_config_cm_dll_phase()
451 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config); in msm_config_cm_dll_phase()
453 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config); in msm_config_cm_dll_phase()
455 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config); in msm_config_cm_dll_phase()
462 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config); in msm_config_cm_dll_phase()
465 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config); in msm_config_cm_dll_phase()
472 spin_unlock_irqrestore(&host->lock, flags); in msm_config_cm_dll_phase()
479 * setting for SD3.0 UHS-I card read operation (in SDR104
495 struct mmc_host *mmc = host->mmc; in msm_find_most_appropriate_phase()
500 return -EINVAL; in msm_find_most_appropriate_phase()
518 return -EINVAL; in msm_find_most_appropriate_phase()
520 /* Check if phase-0 is present in first valid window? */ in msm_find_most_appropriate_phase()
524 /* Check if cycle exist between 2 valid windows */ in msm_find_most_appropriate_phase()
538 /* If 2 valid windows form cycle then merge them as single window */ in msm_find_most_appropriate_phase()
551 return -EINVAL; in msm_find_most_appropriate_phase()
575 i--; in msm_find_most_appropriate_phase()
580 ret = -EINVAL; in msm_find_most_appropriate_phase()
595 if (host->clock <= 112000000) in msm_cm_dll_set_freq()
597 else if (host->clock <= 125000000) in msm_cm_dll_set_freq()
599 else if (host->clock <= 137000000) in msm_cm_dll_set_freq()
601 else if (host->clock <= 150000000) in msm_cm_dll_set_freq()
603 else if (host->clock <= 162000000) in msm_cm_dll_set_freq()
605 else if (host->clock <= 175000000) in msm_cm_dll_set_freq()
607 else if (host->clock <= 187000000) in msm_cm_dll_set_freq()
609 else if (host->clock <= 200000000) in msm_cm_dll_set_freq()
612 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config); in msm_cm_dll_set_freq()
615 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config); in msm_cm_dll_set_freq()
621 struct mmc_host *mmc = host->mmc; in msm_init_cm_dll()
628 msm_host->offset; in msm_init_cm_dll()
630 if (msm_host->use_14lpp_dll_reset && !IS_ERR_OR_NULL(msm_host->xo_clk)) in msm_init_cm_dll()
631 xo_clk = clk_get_rate(msm_host->xo_clk); in msm_init_cm_dll()
633 spin_lock_irqsave(&host->lock, flags); in msm_init_cm_dll()
640 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec); in msm_init_cm_dll()
642 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec); in msm_init_cm_dll()
644 if (msm_host->dll_config) in msm_init_cm_dll()
645 writel_relaxed(msm_host->dll_config, in msm_init_cm_dll()
646 host->ioaddr + msm_offset->core_dll_config); in msm_init_cm_dll()
648 if (msm_host->use_14lpp_dll_reset) { in msm_init_cm_dll()
649 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
650 msm_offset->core_dll_config); in msm_init_cm_dll()
652 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
653 msm_offset->core_dll_config); in msm_init_cm_dll()
655 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
656 msm_offset->core_dll_config_2); in msm_init_cm_dll()
658 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
659 msm_offset->core_dll_config_2); in msm_init_cm_dll()
662 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
663 msm_offset->core_dll_config); in msm_init_cm_dll()
665 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
666 msm_offset->core_dll_config); in msm_init_cm_dll()
668 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
669 msm_offset->core_dll_config); in msm_init_cm_dll()
671 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
672 msm_offset->core_dll_config); in msm_init_cm_dll()
674 if (!msm_host->dll_config) in msm_init_cm_dll()
677 if (msm_host->use_14lpp_dll_reset && in msm_init_cm_dll()
678 !IS_ERR_OR_NULL(msm_host->xo_clk)) { in msm_init_cm_dll()
681 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
682 msm_offset->core_dll_config_2); in msm_init_cm_dll()
685 mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 8), in msm_init_cm_dll()
688 mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 4), in msm_init_cm_dll()
691 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
692 msm_offset->core_dll_config_2); in msm_init_cm_dll()
696 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
697 msm_offset->core_dll_config_2); in msm_init_cm_dll()
702 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
703 msm_offset->core_dll_config); in msm_init_cm_dll()
705 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
706 msm_offset->core_dll_config); in msm_init_cm_dll()
708 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
709 msm_offset->core_dll_config); in msm_init_cm_dll()
711 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
712 msm_offset->core_dll_config); in msm_init_cm_dll()
714 if (msm_host->use_14lpp_dll_reset) { in msm_init_cm_dll()
715 if (!msm_host->dll_config) in msm_init_cm_dll()
717 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
718 msm_offset->core_dll_config_2); in msm_init_cm_dll()
720 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
721 msm_offset->core_dll_config_2); in msm_init_cm_dll()
728 if (msm_host->uses_tassadar_dll) { in msm_init_cm_dll()
731 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
732 msm_offset->core_dll_usr_ctl); in msm_init_cm_dll()
734 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
735 msm_offset->core_dll_config_3); in msm_init_cm_dll()
737 if (msm_host->clk_rate < 150000000) in msm_init_cm_dll()
741 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
742 msm_offset->core_dll_config_3); in msm_init_cm_dll()
745 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
746 msm_offset->core_dll_config); in msm_init_cm_dll()
748 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
749 msm_offset->core_dll_config); in msm_init_cm_dll()
751 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
752 msm_offset->core_dll_config); in msm_init_cm_dll()
754 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
755 msm_offset->core_dll_config); in msm_init_cm_dll()
758 while (!(readl_relaxed(host->ioaddr + msm_offset->core_dll_status) & in msm_init_cm_dll()
761 if (--wait_cnt == 0) { in msm_init_cm_dll()
764 spin_unlock_irqrestore(&host->lock, flags); in msm_init_cm_dll()
765 return -ETIMEDOUT; in msm_init_cm_dll()
770 spin_unlock_irqrestore(&host->lock, flags); in msm_init_cm_dll()
780 msm_host->offset; in msm_hc_select_default()
782 if (!msm_host->use_cdclp533) { in msm_hc_select_default()
783 config = readl_relaxed(host->ioaddr + in msm_hc_select_default()
784 msm_offset->core_vendor_spec3); in msm_hc_select_default()
786 writel_relaxed(config, host->ioaddr + in msm_hc_select_default()
787 msm_offset->core_vendor_spec3); in msm_hc_select_default()
790 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec); in msm_hc_select_default()
793 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec); in msm_hc_select_default()
802 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec); in msm_hc_select_default()
805 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec); in msm_hc_select_default()
818 struct mmc_ios ios = host->mmc->ios; in msm_hc_select_hs400()
822 msm_host->offset; in msm_hc_select_hs400()
825 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec); in msm_hc_select_hs400()
829 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec); in msm_hc_select_hs400()
834 if ((msm_host->tuning_done || ios.enhanced_strobe) && in msm_hc_select_hs400()
835 !msm_host->calibration_done) { in msm_hc_select_hs400()
836 config = readl_relaxed(host->ioaddr + in msm_hc_select_hs400()
837 msm_offset->core_vendor_spec); in msm_hc_select_hs400()
840 writel_relaxed(config, host->ioaddr + in msm_hc_select_hs400()
841 msm_offset->core_vendor_spec); in msm_hc_select_hs400()
843 if (!msm_host->clk_rate && !msm_host->use_cdclp533) { in msm_hc_select_hs400()
849 rc = readl_relaxed_poll_timeout(host->ioaddr + in msm_hc_select_hs400()
850 msm_offset->core_dll_status, in msm_hc_select_hs400()
856 if (rc == -ETIMEDOUT) in msm_hc_select_hs400()
858 mmc_hostname(host->mmc), dll_lock); in msm_hc_select_hs400()
868 * sdhci_msm_hc_select_mode :- In general all timing modes are
873 * HS200 - SDR104 (Since they both are equivalent in functionality)
874 * HS400 - This involves multiple configurations
875 * Initially SDR104 - when tuning is required as HS200
882 * HS400 - divided clock (free running MCLK/2)
883 * All other modes - default (free running MCLK)
887 struct mmc_ios ios = host->mmc->ios; in sdhci_msm_hc_select_mode()
890 host->flags & SDHCI_HS400_TUNING) in sdhci_msm_hc_select_mode()
903 msm_host->offset; in sdhci_msm_cdclp533_calibration()
905 pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__); in sdhci_msm_cdclp533_calibration()
916 ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase); in sdhci_msm_cdclp533_calibration()
920 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config); in sdhci_msm_cdclp533_calibration()
922 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config); in sdhci_msm_cdclp533_calibration()
924 config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg); in sdhci_msm_cdclp533_calibration()
926 writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg); in sdhci_msm_cdclp533_calibration()
928 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG); in sdhci_msm_cdclp533_calibration()
930 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG); in sdhci_msm_cdclp533_calibration()
932 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG); in sdhci_msm_cdclp533_calibration()
934 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG); in sdhci_msm_cdclp533_calibration()
936 config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg); in sdhci_msm_cdclp533_calibration()
938 writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg); in sdhci_msm_cdclp533_calibration()
942 writel_relaxed(0x11800EC, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); in sdhci_msm_cdclp533_calibration()
943 writel_relaxed(0x3011111, host->ioaddr + CORE_CSR_CDC_CTLR_CFG1); in sdhci_msm_cdclp533_calibration()
944 writel_relaxed(0x1201000, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0); in sdhci_msm_cdclp533_calibration()
945 writel_relaxed(0x4, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG1); in sdhci_msm_cdclp533_calibration()
946 writel_relaxed(0xCB732020, host->ioaddr + CORE_CSR_CDC_REFCOUNT_CFG); in sdhci_msm_cdclp533_calibration()
947 writel_relaxed(0xB19, host->ioaddr + CORE_CSR_CDC_COARSE_CAL_CFG); in sdhci_msm_cdclp533_calibration()
948 writel_relaxed(0x4E2, host->ioaddr + CORE_CSR_CDC_DELAY_CFG); in sdhci_msm_cdclp533_calibration()
949 writel_relaxed(0x0, host->ioaddr + CORE_CDC_OFFSET_CFG); in sdhci_msm_cdclp533_calibration()
950 writel_relaxed(0x16334, host->ioaddr + CORE_CDC_SLAVE_DDA_CFG); in sdhci_msm_cdclp533_calibration()
954 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); in sdhci_msm_cdclp533_calibration()
956 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); in sdhci_msm_cdclp533_calibration()
958 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); in sdhci_msm_cdclp533_calibration()
960 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); in sdhci_msm_cdclp533_calibration()
962 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); in sdhci_msm_cdclp533_calibration()
964 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); in sdhci_msm_cdclp533_calibration()
966 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0); in sdhci_msm_cdclp533_calibration()
968 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0); in sdhci_msm_cdclp533_calibration()
970 ret = readl_relaxed_poll_timeout(host->ioaddr + CORE_CSR_CDC_STATUS0, in sdhci_msm_cdclp533_calibration()
975 if (ret == -ETIMEDOUT) { in sdhci_msm_cdclp533_calibration()
977 mmc_hostname(host->mmc), __func__); in sdhci_msm_cdclp533_calibration()
981 ret = readl_relaxed(host->ioaddr + CORE_CSR_CDC_STATUS0) in sdhci_msm_cdclp533_calibration()
985 mmc_hostname(host->mmc), __func__, ret); in sdhci_msm_cdclp533_calibration()
986 ret = -EINVAL; in sdhci_msm_cdclp533_calibration()
990 config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg); in sdhci_msm_cdclp533_calibration()
992 writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg); in sdhci_msm_cdclp533_calibration()
994 pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc), in sdhci_msm_cdclp533_calibration()
1001 struct mmc_host *mmc = host->mmc; in sdhci_msm_cm_dll_sdc4_calibration()
1009 pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__); in sdhci_msm_cm_dll_sdc4_calibration()
1018 if (msm_host->updated_ddr_cfg) in sdhci_msm_cm_dll_sdc4_calibration()
1019 ddr_cfg_offset = msm_offset->core_ddr_config; in sdhci_msm_cm_dll_sdc4_calibration()
1021 ddr_cfg_offset = msm_offset->core_ddr_config_old; in sdhci_msm_cm_dll_sdc4_calibration()
1022 writel_relaxed(msm_host->ddr_config, host->ioaddr + ddr_cfg_offset); in sdhci_msm_cm_dll_sdc4_calibration()
1024 if (mmc->ios.enhanced_strobe) { in sdhci_msm_cm_dll_sdc4_calibration()
1025 config = readl_relaxed(host->ioaddr + in sdhci_msm_cm_dll_sdc4_calibration()
1026 msm_offset->core_ddr_200_cfg); in sdhci_msm_cm_dll_sdc4_calibration()
1028 writel_relaxed(config, host->ioaddr + in sdhci_msm_cm_dll_sdc4_calibration()
1029 msm_offset->core_ddr_200_cfg); in sdhci_msm_cm_dll_sdc4_calibration()
1032 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config_2); in sdhci_msm_cm_dll_sdc4_calibration()
1034 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config_2); in sdhci_msm_cm_dll_sdc4_calibration()
1036 ret = readl_relaxed_poll_timeout(host->ioaddr + in sdhci_msm_cm_dll_sdc4_calibration()
1037 msm_offset->core_dll_status, in sdhci_msm_cm_dll_sdc4_calibration()
1042 if (ret == -ETIMEDOUT) { in sdhci_msm_cm_dll_sdc4_calibration()
1044 mmc_hostname(host->mmc), __func__); in sdhci_msm_cm_dll_sdc4_calibration()
1051 * and MCLK must be switched on for at-least 1us before DATA in sdhci_msm_cm_dll_sdc4_calibration()
1056 if (!msm_host->use_14lpp_dll_reset) { in sdhci_msm_cm_dll_sdc4_calibration()
1057 config = readl_relaxed(host->ioaddr + in sdhci_msm_cm_dll_sdc4_calibration()
1058 msm_offset->core_vendor_spec3); in sdhci_msm_cm_dll_sdc4_calibration()
1060 writel_relaxed(config, host->ioaddr + in sdhci_msm_cm_dll_sdc4_calibration()
1061 msm_offset->core_vendor_spec3); in sdhci_msm_cm_dll_sdc4_calibration()
1070 pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc), in sdhci_msm_cm_dll_sdc4_calibration()
1079 struct mmc_host *mmc = host->mmc; in sdhci_msm_hs400_dll_calibration()
1083 msm_host->offset; in sdhci_msm_hs400_dll_calibration()
1085 pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__); in sdhci_msm_hs400_dll_calibration()
1095 if (!mmc->ios.enhanced_strobe) { in sdhci_msm_hs400_dll_calibration()
1098 msm_host->saved_tuning_phase); in sdhci_msm_hs400_dll_calibration()
1101 config = readl_relaxed(host->ioaddr + in sdhci_msm_hs400_dll_calibration()
1102 msm_offset->core_dll_config); in sdhci_msm_hs400_dll_calibration()
1104 writel_relaxed(config, host->ioaddr + in sdhci_msm_hs400_dll_calibration()
1105 msm_offset->core_dll_config); in sdhci_msm_hs400_dll_calibration()
1108 if (msm_host->use_cdclp533) in sdhci_msm_hs400_dll_calibration()
1113 pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc), in sdhci_msm_hs400_dll_calibration()
1120 struct mmc_ios *ios = &host->mmc->ios; in sdhci_msm_is_tuning_needed()
1126 if (host->clock <= CORE_FREQ_100MHZ || in sdhci_msm_is_tuning_needed()
1127 !(ios->timing == MMC_TIMING_MMC_HS400 || in sdhci_msm_is_tuning_needed()
1128 ios->timing == MMC_TIMING_MMC_HS200 || in sdhci_msm_is_tuning_needed()
1129 ios->timing == MMC_TIMING_UHS_SDR104) || in sdhci_msm_is_tuning_needed()
1130 ios->enhanced_strobe) in sdhci_msm_is_tuning_needed()
1155 ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase); in sdhci_msm_restore_sdr_dll_config()
1163 u32 config, oldconfig = readl_relaxed(host->ioaddr + in sdhci_msm_set_cdr()
1164 msm_offset->core_dll_config); in sdhci_msm_set_cdr()
1176 writel_relaxed(config, host->ioaddr + in sdhci_msm_set_cdr()
1177 msm_offset->core_dll_config); in sdhci_msm_set_cdr()
1187 struct mmc_ios ios = host->mmc->ios; in sdhci_msm_execute_tuning()
1192 msm_host->use_cdr = false; in sdhci_msm_execute_tuning()
1197 /* Clock-Data-Recovery used to dynamically adjust RX sampling point */ in sdhci_msm_execute_tuning()
1198 msm_host->use_cdr = true; in sdhci_msm_execute_tuning()
1204 msm_host->tuning_done = 0; in sdhci_msm_execute_tuning()
1208 * - select MCLK/2 in VENDOR_SPEC in sdhci_msm_execute_tuning()
1209 * - program MCLK to 400MHz (or nearest supported) in GCC in sdhci_msm_execute_tuning()
1211 if (host->flags & SDHCI_HS400_TUNING) { in sdhci_msm_execute_tuning()
1214 host->flags &= ~SDHCI_HS400_TUNING; in sdhci_msm_execute_tuning()
1250 if (--tuning_seq_cnt) { in sdhci_msm_execute_tuning()
1270 msm_host->saved_tuning_phase = phase; in sdhci_msm_execute_tuning()
1274 if (--tuning_seq_cnt) in sdhci_msm_execute_tuning()
1279 rc = -EIO; in sdhci_msm_execute_tuning()
1283 msm_host->tuning_done = true; in sdhci_msm_execute_tuning()
1288 * sdhci_msm_hs400 - Calibrate the DLL for HS400 bus speed mode operation.
1299 if (host->clock > CORE_FREQ_100MHZ && in sdhci_msm_hs400()
1300 (msm_host->tuning_done || ios->enhanced_strobe) && in sdhci_msm_hs400()
1301 !msm_host->calibration_done) { in sdhci_msm_hs400()
1304 msm_host->calibration_done = true; in sdhci_msm_hs400()
1307 mmc_hostname(host->mmc), ret); in sdhci_msm_hs400()
1314 struct mmc_host *mmc = host->mmc; in sdhci_msm_set_uhs_signaling()
1320 msm_host->offset; in sdhci_msm_set_uhs_signaling()
1352 if (host->clock <= CORE_FREQ_100MHZ) { in sdhci_msm_set_uhs_signaling()
1361 config = readl_relaxed(host->ioaddr + in sdhci_msm_set_uhs_signaling()
1362 msm_offset->core_dll_config); in sdhci_msm_set_uhs_signaling()
1364 writel_relaxed(config, host->ioaddr + in sdhci_msm_set_uhs_signaling()
1365 msm_offset->core_dll_config); in sdhci_msm_set_uhs_signaling()
1367 config = readl_relaxed(host->ioaddr + in sdhci_msm_set_uhs_signaling()
1368 msm_offset->core_dll_config); in sdhci_msm_set_uhs_signaling()
1370 writel_relaxed(config, host->ioaddr + in sdhci_msm_set_uhs_signaling()
1371 msm_offset->core_dll_config); in sdhci_msm_set_uhs_signaling()
1377 msm_host->calibration_done = false; in sdhci_msm_set_uhs_signaling()
1381 mmc_hostname(host->mmc), host->clock, uhs, ctrl_2); in sdhci_msm_set_uhs_signaling()
1384 if (mmc->ios.timing == MMC_TIMING_MMC_HS400) in sdhci_msm_set_uhs_signaling()
1385 sdhci_msm_hs400(host, &mmc->ios); in sdhci_msm_set_uhs_signaling()
1390 struct platform_device *pdev = msm_host->pdev; in sdhci_msm_set_pincfg()
1394 ret = pinctrl_pm_select_default_state(&pdev->dev); in sdhci_msm_set_pincfg()
1396 ret = pinctrl_pm_select_sleep_state(&pdev->dev); in sdhci_msm_set_pincfg()
1403 if (IS_ERR(mmc->supply.vmmc)) in sdhci_msm_set_vmmc()
1406 return mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, mmc->ios.vdd); in sdhci_msm_set_vmmc()
1415 if (msm_host->vqmmc_enabled == level) in msm_toggle_vqmmc()
1420 if (msm_host->caps_0 & CORE_3_0V_SUPPORT) in msm_toggle_vqmmc()
1422 else if (msm_host->caps_0 & CORE_1_8V_SUPPORT) in msm_toggle_vqmmc()
1425 if (msm_host->caps_0 & CORE_VOLT_SUPPORT) { in msm_toggle_vqmmc()
1433 ret = regulator_enable(mmc->supply.vqmmc); in msm_toggle_vqmmc()
1435 ret = regulator_disable(mmc->supply.vqmmc); in msm_toggle_vqmmc()
1442 msm_host->vqmmc_enabled = level; in msm_toggle_vqmmc()
1453 ret = regulator_set_load(mmc->supply.vqmmc, load); in msm_config_vqmmc_mode()
1466 if (IS_ERR(mmc->supply.vqmmc) || in sdhci_msm_set_vqmmc()
1467 (mmc->ios.power_mode == MMC_POWER_UNDEFINED)) in sdhci_msm_set_vqmmc()
1480 mmc->card && mmc_card_mmc(mmc->card); in sdhci_msm_set_vqmmc()
1492 init_waitqueue_head(&msm_host->pwr_irq_wait); in sdhci_msm_init_pwr_irq_wait()
1498 wake_up(&msm_host->pwr_irq_wait); in sdhci_msm_complete_pwr_irq_wait()
1517 msm_host->offset; in sdhci_msm_check_power_status()
1520 mmc_hostname(host->mmc), __func__, req_type, in sdhci_msm_check_power_status()
1521 msm_host->curr_pwr_state, msm_host->curr_io_level); in sdhci_msm_check_power_status()
1526 * Since sdhci-msm-v5, this bit has been removed and SW must consider in sdhci_msm_check_power_status()
1529 if (!msm_host->mci_removed) in sdhci_msm_check_power_status()
1531 msm_offset->core_generics); in sdhci_msm_check_power_status()
1538 * The IRQ for request type IO High/LOW will be generated when - in sdhci_msm_check_power_status()
1546 * for host->pwr to handle a case where IO voltage high request is in sdhci_msm_check_power_status()
1549 if ((req_type & REQ_IO_HIGH) && !host->pwr) { in sdhci_msm_check_power_status()
1551 mmc_hostname(host->mmc), req_type); in sdhci_msm_check_power_status()
1554 if ((req_type & msm_host->curr_pwr_state) || in sdhci_msm_check_power_status()
1555 (req_type & msm_host->curr_io_level)) in sdhci_msm_check_power_status()
1564 if (!wait_event_timeout(msm_host->pwr_irq_wait, in sdhci_msm_check_power_status()
1565 msm_host->pwr_irq_flag, in sdhci_msm_check_power_status()
1567 dev_warn(&msm_host->pdev->dev, in sdhci_msm_check_power_status()
1569 mmc_hostname(host->mmc), req_type); in sdhci_msm_check_power_status()
1571 pr_debug("%s: %s: request %d done\n", mmc_hostname(host->mmc), in sdhci_msm_check_power_status()
1580 msm_host->offset; in sdhci_msm_dump_pwr_ctrl_regs()
1583 mmc_hostname(host->mmc), in sdhci_msm_dump_pwr_ctrl_regs()
1584 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_status), in sdhci_msm_dump_pwr_ctrl_regs()
1585 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_mask), in sdhci_msm_dump_pwr_ctrl_regs()
1586 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_ctl)); in sdhci_msm_dump_pwr_ctrl_regs()
1593 struct mmc_host *mmc = host->mmc; in sdhci_msm_handle_pwr_irq()
1598 const struct sdhci_msm_offset *msm_offset = msm_host->offset; in sdhci_msm_handle_pwr_irq()
1601 msm_offset->core_pwrctl_status); in sdhci_msm_handle_pwr_irq()
1605 msm_offset->core_pwrctl_clear); in sdhci_msm_handle_pwr_irq()
1615 msm_offset->core_pwrctl_status)) { in sdhci_msm_handle_pwr_irq()
1618 mmc_hostname(host->mmc), irq_status); in sdhci_msm_handle_pwr_irq()
1624 msm_offset->core_pwrctl_clear); in sdhci_msm_handle_pwr_irq()
1625 retry--; in sdhci_msm_handle_pwr_irq()
1663 if (io_level && !IS_ERR(mmc->supply.vqmmc) && !pwr_state) { in sdhci_msm_handle_pwr_irq()
1664 ret = mmc_regulator_set_vqmmc(mmc, &mmc->ios); in sdhci_msm_handle_pwr_irq()
1668 mmc->ios.signal_voltage, mmc->ios.vdd, in sdhci_msm_handle_pwr_irq()
1680 msm_offset->core_pwrctl_ctl); in sdhci_msm_handle_pwr_irq()
1684 * regulators, don't change the IO PAD PWR SWITCH. in sdhci_msm_handle_pwr_irq()
1686 if (msm_host->caps_0 & CORE_VOLT_SUPPORT) { in sdhci_msm_handle_pwr_irq()
1689 * We should unset IO PAD PWR switch only if the register write in sdhci_msm_handle_pwr_irq()
1691 * Else, we should keep the IO PAD PWR switch set. in sdhci_msm_handle_pwr_irq()
1694 * IO PAD PWR switch must be kept set to reflect actual in sdhci_msm_handle_pwr_irq()
1699 config = readl_relaxed(host->ioaddr + in sdhci_msm_handle_pwr_irq()
1700 msm_offset->core_vendor_spec); in sdhci_msm_handle_pwr_irq()
1704 (msm_host->caps_0 & CORE_3_0V_SUPPORT)) in sdhci_msm_handle_pwr_irq()
1707 (msm_host->caps_0 & CORE_1_8V_SUPPORT)) in sdhci_msm_handle_pwr_irq()
1711 writel_relaxed(new_config, host->ioaddr + in sdhci_msm_handle_pwr_irq()
1712 msm_offset->core_vendor_spec); in sdhci_msm_handle_pwr_irq()
1716 msm_host->curr_pwr_state = pwr_state; in sdhci_msm_handle_pwr_irq()
1718 msm_host->curr_io_level = io_level; in sdhci_msm_handle_pwr_irq()
1721 mmc_hostname(msm_host->mmc), __func__, irq, irq_status, in sdhci_msm_handle_pwr_irq()
1732 msm_host->pwr_irq_flag = 1; in sdhci_msm_pwr_irq()
1743 struct clk *core_clk = msm_host->bulk_clks[0].clk; in sdhci_msm_get_max_clock()
1754 * __sdhci_msm_set_clock - sdhci_msm clock control.
1779 /* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */
1786 host->mmc->actual_clock = msm_host->clk_rate = 0; in sdhci_msm_set_clock()
1822 writel((val), (host)->ice_mem + (reg))
1824 readl((host)->ice_mem + (reg))
1828 struct device *dev = mmc_dev(msm_host->mmc); in sdhci_msm_ice_supported()
1863 struct mmc_host *mmc = msm_host->mmc; in sdhci_msm_ice_init()
1870 res = platform_get_resource_byname(msm_host->pdev, IORESOURCE_MEM, in sdhci_msm_ice_init()
1882 msm_host->ice_mem = devm_ioremap_resource(dev, res); in sdhci_msm_ice_init()
1883 if (IS_ERR(msm_host->ice_mem)) in sdhci_msm_ice_init()
1884 return PTR_ERR(msm_host->ice_mem); in sdhci_msm_ice_init()
1889 mmc->caps2 |= MMC_CAP2_CRYPTO; in sdhci_msm_ice_init()
1904 * [0]-0, [1]-0, [2]-0, [3]-E, [4]-0, [5]-0, [6]-0, [7]-0 in sdhci_msm_ice_low_power_mode_enable()
1924 * Wait until the ICE BIST (built-in self-test) has completed.
1933 * the full storage stack anyway, and not relying on hardware-level self-tests.
1940 err = readl_poll_timeout(msm_host->ice_mem + QCOM_ICE_REG_BIST_STATUS, in sdhci_msm_ice_wait_bist_status()
1944 dev_err(mmc_dev(msm_host->mmc), in sdhci_msm_ice_wait_bist_status()
1945 "Timed out waiting for ICE self-test to complete\n"); in sdhci_msm_ice_wait_bist_status()
1951 if (!(msm_host->mmc->caps2 & MMC_CAP2_CRYPTO)) in sdhci_msm_ice_enable()
1960 if (!(msm_host->mmc->caps2 & MMC_CAP2_CRYPTO)) in sdhci_msm_ice_resume()
1967 * vendor-specific SCM calls for this; it doesn't support the standard way.
1973 struct device *dev = mmc_dev(cq_host->mmc); in sdhci_msm_program_key()
1982 if (!(cfg->config_enable & CQHCI_CRYPTO_CONFIGURATION_ENABLE)) in sdhci_msm_program_key()
1985 /* Only AES-256-XTS has been tested so far. */ in sdhci_msm_program_key()
1986 cap = cq_host->crypto_cap_array[cfg->crypto_cap_idx]; in sdhci_msm_program_key()
1992 return -EINVAL; in sdhci_msm_program_key()
1995 memcpy(key.bytes, cfg->crypto_key, AES_256_XTS_KEY_SIZE); in sdhci_msm_program_key()
1998 * The SCM call byte-swaps the 32-bit words of the key. So we have to in sdhci_msm_program_key()
2006 cfg->data_unit_size); in sdhci_msm_program_key()
2047 cqhci_irq(host->mmc, intmask, cmd_error, data_error); in sdhci_msm_cqe_irq()
2069 * on 16-byte descriptors in 64bit mode. in sdhci_msm_cqe_disable()
2071 if (host->flags & SDHCI_USE_64_BIT_DMA) in sdhci_msm_cqe_disable()
2072 host->desc_sz = 16; in sdhci_msm_cqe_disable()
2074 spin_lock_irqsave(&host->lock, flags); in sdhci_msm_cqe_disable()
2087 spin_unlock_irqrestore(&host->lock, flags); in sdhci_msm_cqe_disable()
2101 * using 4 * MCLK * 2^(count + 13). where MCLK = 1 / host->clock. in sdhci_msm_set_timeout()
2103 if (cmd && cmd->data && host->clock > 400000 && in sdhci_msm_set_timeout()
2104 host->clock <= 50000000 && in sdhci_msm_set_timeout()
2105 ((1 << (count + start)) > (10 * host->clock))) in sdhci_msm_set_timeout()
2106 host->data_timeout = 22LL * NSEC_PER_SEC; in sdhci_msm_set_timeout()
2131 if (host->caps & SDHCI_CAN_64BIT) in sdhci_msm_cqe_add_host()
2132 host->alloc_desc_sz = 16; in sdhci_msm_cqe_add_host()
2141 dev_err(&pdev->dev, "cqhci-pltfm init: failed: %d\n", ret); in sdhci_msm_cqe_add_host()
2145 msm_host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; in sdhci_msm_cqe_add_host()
2146 cq_host->ops = &sdhci_msm_cqhci_ops; in sdhci_msm_cqe_add_host()
2148 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; in sdhci_msm_cqe_add_host()
2154 ret = cqhci_init(cq_host, host->mmc, dma64); in sdhci_msm_cqe_add_host()
2156 dev_err(&pdev->dev, "%s: CQE init: failed (%d)\n", in sdhci_msm_cqe_add_host()
2157 mmc_hostname(host->mmc), ret); in sdhci_msm_cqe_add_host()
2172 if (host->flags & SDHCI_USE_64_BIT_DMA) in sdhci_msm_cqe_add_host()
2173 host->desc_sz = 12; in sdhci_msm_cqe_add_host()
2179 dev_info(&pdev->dev, "%s: CQE init: success\n", in sdhci_msm_cqe_add_host()
2180 mmc_hostname(host->mmc)); in sdhci_msm_cqe_add_host()
2207 if (host->pwr && (val & SDHCI_RESET_ALL)) in __sdhci_msm_check_write()
2214 msm_host->transfer_mode = val; in __sdhci_msm_check_write()
2217 if (!msm_host->use_cdr) in __sdhci_msm_check_write()
2219 if ((msm_host->transfer_mode & SDHCI_TRNS_READ) && in __sdhci_msm_check_write()
2229 msm_host->pwr_irq_flag = 0; in __sdhci_msm_check_write()
2245 writew_relaxed(val, host->ioaddr + reg); in sdhci_msm_writew()
2258 writeb_relaxed(val, host->ioaddr + reg); in sdhci_msm_writeb()
2266 struct mmc_host *mmc = msm_host->mmc; in sdhci_msm_set_regulator_caps()
2267 struct regulator *supply = mmc->supply.vqmmc; in sdhci_msm_set_regulator_caps()
2270 const struct sdhci_msm_offset *msm_offset = msm_host->offset; in sdhci_msm_set_regulator_caps()
2272 if (!IS_ERR(mmc->supply.vqmmc)) { in sdhci_msm_set_regulator_caps()
2288 u32 io_level = msm_host->curr_io_level; in sdhci_msm_set_regulator_caps()
2290 config = readl_relaxed(host->ioaddr + in sdhci_msm_set_regulator_caps()
2291 msm_offset->core_vendor_spec); in sdhci_msm_set_regulator_caps()
2300 host->ioaddr + msm_offset->core_vendor_spec); in sdhci_msm_set_regulator_caps()
2302 msm_host->caps_0 |= caps; in sdhci_msm_set_regulator_caps()
2308 if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL)) in sdhci_msm_reset()
2309 cqhci_deactivate(host->mmc); in sdhci_msm_reset()
2317 ret = mmc_regulator_get_supply(msm_host->mmc); in sdhci_msm_register_vreg()
2336 if (host->version < SDHCI_SPEC_300) in sdhci_msm_start_signal_voltage_switch()
2341 switch (ios->signal_voltage) { in sdhci_msm_start_signal_voltage_switch()
2343 if (!(host->flags & SDHCI_SIGNALING_330)) in sdhci_msm_start_signal_voltage_switch()
2344 return -EINVAL; in sdhci_msm_start_signal_voltage_switch()
2350 if (!(host->flags & SDHCI_SIGNALING_180)) in sdhci_msm_start_signal_voltage_switch()
2351 return -EINVAL; in sdhci_msm_start_signal_voltage_switch()
2358 return -EINVAL; in sdhci_msm_start_signal_voltage_switch()
2375 return -EAGAIN; in sdhci_msm_start_signal_voltage_switch()
2380 pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
2386 const struct sdhci_msm_offset *msm_offset = msm_host->offset; in sdhci_msm_dump_vendor_regs()
2388 SDHCI_MSM_DUMP("----------- VENDOR REGISTER DUMP -----------\n"); in sdhci_msm_dump_vendor_regs()
2392 readl_relaxed(host->ioaddr + msm_offset->core_dll_status), in sdhci_msm_dump_vendor_regs()
2393 readl_relaxed(host->ioaddr + msm_offset->core_dll_config), in sdhci_msm_dump_vendor_regs()
2394 readl_relaxed(host->ioaddr + msm_offset->core_dll_config_2)); in sdhci_msm_dump_vendor_regs()
2397 readl_relaxed(host->ioaddr + msm_offset->core_dll_config_3), in sdhci_msm_dump_vendor_regs()
2398 readl_relaxed(host->ioaddr + msm_offset->core_dll_usr_ctl), in sdhci_msm_dump_vendor_regs()
2399 readl_relaxed(host->ioaddr + msm_offset->core_ddr_config)); in sdhci_msm_dump_vendor_regs()
2402 readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec), in sdhci_msm_dump_vendor_regs()
2403 readl_relaxed(host->ioaddr + in sdhci_msm_dump_vendor_regs()
2404 msm_offset->core_vendor_spec_func2), in sdhci_msm_dump_vendor_regs()
2405 readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec3)); in sdhci_msm_dump_vendor_regs()
2437 {.compatible = "qcom,sdhci-msm-v4", .data = &sdhci_msm_mci_var},
2438 {.compatible = "qcom,sdhci-msm-v5", .data = &sdhci_msm_v5_var},
2439 {.compatible = "qcom,sdm845-sdhci", .data = &sdm845_sdhci_var},
2440 {.compatible = "qcom,sc7180-sdhci", .data = &sdm845_sdhci_var},
2474 struct device_node *node = pdev->dev.of_node; in sdhci_msm_get_of_property()
2478 if (of_property_read_u32(node, "qcom,ddr-config", in sdhci_msm_get_of_property()
2479 &msm_host->ddr_config)) in sdhci_msm_get_of_property()
2480 msm_host->ddr_config = DDR_CONFIG_POR_VAL; in sdhci_msm_get_of_property()
2482 of_property_read_u32(node, "qcom,dll-config", &msm_host->dll_config); in sdhci_msm_get_of_property()
2498 struct device_node *node = pdev->dev.of_node; in sdhci_msm_probe()
2504 host->sdma_boundary = 0; in sdhci_msm_probe()
2507 msm_host->mmc = host->mmc; in sdhci_msm_probe()
2508 msm_host->pdev = pdev; in sdhci_msm_probe()
2510 ret = mmc_of_parse(host->mmc); in sdhci_msm_probe()
2518 var_info = of_device_get_match_data(&pdev->dev); in sdhci_msm_probe()
2520 msm_host->mci_removed = var_info->mci_removed; in sdhci_msm_probe()
2521 msm_host->restore_dll_config = var_info->restore_dll_config; in sdhci_msm_probe()
2522 msm_host->var_ops = var_info->var_ops; in sdhci_msm_probe()
2523 msm_host->offset = var_info->offset; in sdhci_msm_probe()
2525 msm_offset = msm_host->offset; in sdhci_msm_probe()
2530 msm_host->saved_tuning_phase = INVALID_TUNING_PHASE; in sdhci_msm_probe()
2533 msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus"); in sdhci_msm_probe()
2534 if (!IS_ERR(msm_host->bus_clk)) { in sdhci_msm_probe()
2536 ret = clk_set_rate(msm_host->bus_clk, INT_MAX); in sdhci_msm_probe()
2539 ret = clk_prepare_enable(msm_host->bus_clk); in sdhci_msm_probe()
2545 clk = devm_clk_get(&pdev->dev, "iface"); in sdhci_msm_probe()
2548 dev_err(&pdev->dev, "Peripheral clk setup failed (%d)\n", ret); in sdhci_msm_probe()
2551 msm_host->bulk_clks[1].clk = clk; in sdhci_msm_probe()
2554 clk = devm_clk_get(&pdev->dev, "core"); in sdhci_msm_probe()
2557 dev_err(&pdev->dev, "SDC MMC clk setup failed (%d)\n", ret); in sdhci_msm_probe()
2560 msm_host->bulk_clks[0].clk = clk; in sdhci_msm_probe()
2563 ret = dev_pm_opp_of_find_icc_paths(&pdev->dev, NULL); in sdhci_msm_probe()
2567 ret = devm_pm_opp_set_clkname(&pdev->dev, "core"); in sdhci_msm_probe()
2572 ret = devm_pm_opp_of_add_table(&pdev->dev); in sdhci_msm_probe()
2573 if (ret && ret != -ENODEV) { in sdhci_msm_probe()
2574 dev_err(&pdev->dev, "Invalid OPP table in Device tree\n"); in sdhci_msm_probe()
2579 ret = dev_pm_opp_set_rate(&pdev->dev, INT_MAX); in sdhci_msm_probe()
2581 dev_warn(&pdev->dev, "core clock boost failed\n"); in sdhci_msm_probe()
2583 clk = devm_clk_get(&pdev->dev, "cal"); in sdhci_msm_probe()
2586 msm_host->bulk_clks[2].clk = clk; in sdhci_msm_probe()
2588 clk = devm_clk_get(&pdev->dev, "sleep"); in sdhci_msm_probe()
2591 msm_host->bulk_clks[3].clk = clk; in sdhci_msm_probe()
2593 clk = sdhci_msm_ice_get_clk(&pdev->dev); in sdhci_msm_probe()
2596 msm_host->bulk_clks[4].clk = clk; in sdhci_msm_probe()
2598 ret = clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks), in sdhci_msm_probe()
2599 msm_host->bulk_clks); in sdhci_msm_probe()
2607 msm_host->xo_clk = devm_clk_get(&pdev->dev, "xo"); in sdhci_msm_probe()
2608 if (IS_ERR(msm_host->xo_clk)) { in sdhci_msm_probe()
2609 ret = PTR_ERR(msm_host->xo_clk); in sdhci_msm_probe()
2610 dev_warn(&pdev->dev, "TCXO clk not present (%d)\n", ret); in sdhci_msm_probe()
2613 if (!msm_host->mci_removed) { in sdhci_msm_probe()
2614 msm_host->core_mem = devm_platform_ioremap_resource(pdev, 1); in sdhci_msm_probe()
2615 if (IS_ERR(msm_host->core_mem)) { in sdhci_msm_probe()
2616 ret = PTR_ERR(msm_host->core_mem); in sdhci_msm_probe()
2623 host->ioaddr + msm_offset->core_vendor_spec); in sdhci_msm_probe()
2625 if (!msm_host->mci_removed) { in sdhci_msm_probe()
2628 msm_offset->core_hc_mode); in sdhci_msm_probe()
2630 msm_offset->core_hc_mode); in sdhci_msm_probe()
2633 msm_offset->core_hc_mode); in sdhci_msm_probe()
2636 host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION)); in sdhci_msm_probe()
2637 dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n", in sdhci_msm_probe()
2642 msm_offset->core_mci_version); in sdhci_msm_probe()
2646 dev_dbg(&pdev->dev, "MCI Version: 0x%08x, major: 0x%04x, minor: 0x%02x\n", in sdhci_msm_probe()
2650 msm_host->use_14lpp_dll_reset = true; in sdhci_msm_probe()
2657 msm_host->use_cdclp533 = true; in sdhci_msm_probe()
2664 config = readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES); in sdhci_msm_probe()
2666 writel_relaxed(config, host->ioaddr + in sdhci_msm_probe()
2667 msm_offset->core_vendor_spec_capabilities0); in sdhci_msm_probe()
2671 msm_host->updated_ddr_cfg = true; in sdhci_msm_probe()
2674 msm_host->uses_tassadar_dll = true; in sdhci_msm_probe()
2682 * PWRCTL was either BUS_ON or IO_HIGH_V. So before enabling pwr irq in sdhci_msm_probe()
2696 msm_host->pwr_irq = platform_get_irq_byname(pdev, "pwr_irq"); in sdhci_msm_probe()
2697 if (msm_host->pwr_irq < 0) { in sdhci_msm_probe()
2698 ret = msm_host->pwr_irq; in sdhci_msm_probe()
2703 /* Enable pwr irq interrupts */ in sdhci_msm_probe()
2705 msm_offset->core_pwrctl_mask); in sdhci_msm_probe()
2707 ret = devm_request_threaded_irq(&pdev->dev, msm_host->pwr_irq, NULL, in sdhci_msm_probe()
2709 dev_name(&pdev->dev), host); in sdhci_msm_probe()
2711 dev_err(&pdev->dev, "Request IRQ failed (%d)\n", ret); in sdhci_msm_probe()
2715 msm_host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_NEED_RSP_BUSY; in sdhci_msm_probe()
2718 host->max_timeout_count = 0xF; in sdhci_msm_probe()
2720 pm_runtime_get_noresume(&pdev->dev); in sdhci_msm_probe()
2721 pm_runtime_set_active(&pdev->dev); in sdhci_msm_probe()
2722 pm_runtime_enable(&pdev->dev); in sdhci_msm_probe()
2723 pm_runtime_set_autosuspend_delay(&pdev->dev, in sdhci_msm_probe()
2725 pm_runtime_use_autosuspend(&pdev->dev); in sdhci_msm_probe()
2727 host->mmc_host_ops.start_signal_voltage_switch = in sdhci_msm_probe()
2729 host->mmc_host_ops.execute_tuning = sdhci_msm_execute_tuning; in sdhci_msm_probe()
2730 if (of_property_read_bool(node, "supports-cqe")) in sdhci_msm_probe()
2737 pm_runtime_mark_last_busy(&pdev->dev); in sdhci_msm_probe()
2738 pm_runtime_put_autosuspend(&pdev->dev); in sdhci_msm_probe()
2743 pm_runtime_disable(&pdev->dev); in sdhci_msm_probe()
2744 pm_runtime_set_suspended(&pdev->dev); in sdhci_msm_probe()
2745 pm_runtime_put_noidle(&pdev->dev); in sdhci_msm_probe()
2747 clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks), in sdhci_msm_probe()
2748 msm_host->bulk_clks); in sdhci_msm_probe()
2750 if (!IS_ERR(msm_host->bus_clk)) in sdhci_msm_probe()
2751 clk_disable_unprepare(msm_host->bus_clk); in sdhci_msm_probe()
2762 int dead = (readl_relaxed(host->ioaddr + SDHCI_INT_STATUS) == in sdhci_msm_remove()
2767 pm_runtime_get_sync(&pdev->dev); in sdhci_msm_remove()
2768 pm_runtime_disable(&pdev->dev); in sdhci_msm_remove()
2769 pm_runtime_put_noidle(&pdev->dev); in sdhci_msm_remove()
2771 clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks), in sdhci_msm_remove()
2772 msm_host->bulk_clks); in sdhci_msm_remove()
2773 if (!IS_ERR(msm_host->bus_clk)) in sdhci_msm_remove()
2774 clk_disable_unprepare(msm_host->bus_clk); in sdhci_msm_remove()
2787 clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks), in sdhci_msm_runtime_suspend()
2788 msm_host->bulk_clks); in sdhci_msm_runtime_suspend()
2800 ret = clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks), in sdhci_msm_runtime_resume()
2801 msm_host->bulk_clks); in sdhci_msm_runtime_resume()
2805 * Whenever core-clock is gated dynamically, it's needed to in sdhci_msm_runtime_resume()
2808 if (msm_host->restore_dll_config && msm_host->clk_rate) { in sdhci_msm_runtime_resume()
2814 dev_pm_opp_set_rate(dev, msm_host->clk_rate); in sdhci_msm_runtime_resume()