Lines Matching full:usdhc

148  * The flag tells that the ESDHC controller is an USDHC block that is
160  * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow,
172  * uSDHC: Due to the I/O timing limit, for SDR mode, SD card clock can't
341 	{ .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, },
342 	{ .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, },
343 	{ .compatible = "fsl,imx6sll-usdhc", .data = &usdhc_imx6sll_data, },
344 	{ .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, },
345 	{ .compatible = "fsl,imx6ull-usdhc", .data = &usdhc_imx6ull_data, },
346 	{ .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, },
347 	{ .compatible = "fsl,imx7ulp-usdhc", .data = &usdhc_imx7ulp_data, },
348 	{ .compatible = "fsl,imx8qxp-usdhc", .data = &usdhc_imx8qxp_data, },
349 	{ .compatible = "fsl,imx8mm-usdhc", .data = &usdhc_imx8mm_data, },
588 			 * The usdhc register returns a wrong host version.  in esdhc_readw_le()
721 				 * tuning, when send tuning command, usdhc will  in esdhc_writew_le()
839 			 * The reset on usdhc fails to clear MIX_CTRL register.  in esdhc_writeb_le()
1006 	 * i.MX uSDHC internally already uses a fixed optimized timing for  in usdhc_execute_tuning()
1024 	/* IC suggest to reset USDHC before every tuning command */  in esdhc_prepare_tuning()
1166 	 * for the uSDHC loopback read clock  in esdhc_set_strobe_dll()
1213 			 * usdhc IP internal logic flag execute_tuning_with_clr_buf, which  in esdhc_reset_tuning()
1289 	/* Doc Erratum: the uSDHC actual maximum timeout count is 1 << 29 */  in esdhc_get_max_timeout_count()
1361 		 * to zero if this usdhc is chosen to boot system. Change  in sdhci_esdhc_imx_hwinit()
1386 		 * ESDHC_VEND_SPEC2_EN_BUSY_IRQ, USDHC will generate a  in sdhci_esdhc_imx_hwinit()
1421 			 * the buffer read ready interrupt immediately. If usdhc send  in sdhci_esdhc_imx_hwinit()
1642 		 * Link usdhc specific mmc_host_ops execute_tuning function,  in sdhci_esdhc_imx_probe()