69 /* Tuning bits */
105 /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
152 /* The IP supports manual tuning process */
154 /* The IP supports standard tuning process */
226 	unsigned int tuning_step;       /* The delay cell steps in tuning procedure */
227 	unsigned int tuning_start_tap;	/* The start delay cell point in tuning procedure */
416 /* Enable the auto tuning circuit to check the CMD line and BUS line */
604 				/* the std tuning bits is in ACMD12_ERR for imx6sl */  in esdhc_readw_le()
721 				 * tuning, when send tuning command, usdhc will  in esdhc_writew_le()
844 				 * the tuning bits should be kept during reset  in esdhc_writeb_le()
1007 	 * DDR50, normally does not require tuning for DDR50 mode.  in usdhc_execute_tuning()
1021 	/* FIXME: delay a bit for card to be ready for next tuning due to errors */  in esdhc_prepare_tuning()
1024 	/* IC suggest to reset USDHC before every tuning command */  in esdhc_prepare_tuning()
1030 		"warning! RESET_ALL never complete before sending tuning command\n");  in esdhc_prepare_tuning()
1038 		"tuning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n",  in esdhc_prepare_tuning()
1058 	/* find the mininum delay first which can pass tuning */  in esdhc_executing_tuning()
1067 	/* find the maxinum delay which can not pass tuning */  in esdhc_executing_tuning()
1084 	dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n",  in esdhc_executing_tuning()
1192 	/* Reset the tuning circuit */  in esdhc_reset_tuning()
1210 				 "Warning! clear execute tuning bit failed\n");  in esdhc_reset_tuning()
1416 			/* Disable the CMD CRC check for tuning, if not, need to  in sdhci_esdhc_imx_hwinit()
1417 			 * add some delay after every tuning command, because  in sdhci_esdhc_imx_hwinit()
1418 			 * hardware standard tuning logic will directly go to next  in sdhci_esdhc_imx_hwinit()
1420 			 * the card side to finally send out the tuning data, trigger  in sdhci_esdhc_imx_hwinit()
1422 			 * the next tuning command some eMMC card will stuck, can't  in sdhci_esdhc_imx_hwinit()
1423 			 * response, block the tuning procedure or the first command  in sdhci_esdhc_imx_hwinit()
1424 			 * after the whole tuning procedure always can't get any response.  in sdhci_esdhc_imx_hwinit()
1432 			 * the manual tuning can work.  in sdhci_esdhc_imx_hwinit()
1466 	 * the case after tuning, so ensure the buffer is drained.  in esdhc_cqe_enable()
1538 	of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step);  in sdhci_esdhc_imx_probe_dt()
1539 	of_property_read_u32(np, "fsl,tuning-start-tap",  in sdhci_esdhc_imx_probe_dt()
1636 		/* clear tuning bits in case ROM has set it already */  in sdhci_esdhc_imx_probe()