Lines Matching +full:imx35 +full:- +full:esdhc
1 // SPDX-License-Identifier: GPL-2.0
3 * Freescale eSDHC i.MX controller driver for the platform bus.
5 * derived from the OF-version.
23 #include <linux/mmc/slot-gpio.h>
28 #include "sdhci-pltfm.h"
29 #include "sdhci-esdhc.h"
81 #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1)
125 * There is an INT DMA ERR mismatch between eSDHC and STD SDHC SPEC:
126 * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
127 * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
128 * Define this macro DMA error INT for fsl eSDHC
138 * open ended multi-blk IO. Otherwise the TC INT wouldn't
148 * The flag tells that the ESDHC controller is an USDHC block that is
213 * struct esdhc_platform_data - platform data for esdhc on i.MX
337 { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, },
338 { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, },
339 { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, },
340 { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, },
341 { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, },
342 { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, },
343 { .compatible = "fsl,imx6sll-usdhc", .data = &usdhc_imx6sll_data, },
344 { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, },
345 { .compatible = "fsl,imx6ull-usdhc", .data = &usdhc_imx6ull_data, },
346 { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, },
347 { .compatible = "fsl,imx7ulp-usdhc", .data = &usdhc_imx7ulp_data, },
348 { .compatible = "fsl,imx8qxp-usdhc", .data = &usdhc_imx8qxp_data, },
349 { .compatible = "fsl,imx8mm-usdhc", .data = &usdhc_imx8mm_data, },
356 return data->socdata == &esdhc_imx25_data; in is_imx25_esdhc()
361 return data->socdata == &esdhc_imx53_data; in is_imx53_esdhc()
366 return !!(data->socdata->flags & ESDHC_FLAG_USDHC); in esdhc_is_usdhc()
371 void __iomem *base = host->ioaddr + (reg & ~0x3); in esdhc_clrset_le()
377 #define DRIVER_NAME "sdhci-esdhc-imx"
379 pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
393 ESDHC_IMX_DUMP("========= ESDHC IMX DEBUG STATUS DUMP =========\n"); in esdhc_dump_debug_regs()
398 readw(host->ioaddr + ESDHC_DEBUG_SEL_AND_STATUS_REG)); in esdhc_dump_debug_regs()
410 ret = readl_poll_timeout(host->ioaddr + ESDHC_PRSSTAT, present_state, in esdhc_wait_for_card_clock_gate_off()
412 if (ret == -ETIMEDOUT) in esdhc_wait_for_card_clock_gate_off()
413 dev_warn(mmc_dev(host->mmc), "%s: card clock still not gate off in 100us!.\n", __func__); in esdhc_wait_for_card_clock_gate_off()
421 buswidth = USDHC_GET_BUSWIDTH(readl(host->ioaddr + SDHCI_HOST_CONTROL)); in usdhc_auto_tuning_mode_sel()
444 u32 val = readl(host->ioaddr + reg); in esdhc_readl_le()
450 /* move dat[0-3] bits */ in esdhc_readl_le()
457 /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */ in esdhc_readl_le()
458 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) in esdhc_readl_le()
461 /* In FSL esdhc IC module, only bit20 is used to indicate the in esdhc_readl_le()
462 * ADMA2 capability of esdhc, but this bit is messed up on in esdhc_readl_le()
476 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) in esdhc_readl_le()
477 val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF; in esdhc_readl_le()
490 if (IS_ERR_OR_NULL(imx_data->pins_100mhz)) in esdhc_readl_le()
492 if (IS_ERR_OR_NULL(imx_data->pins_200mhz)) in esdhc_readl_le()
514 if ((imx_data->multiblock_status == WAIT_FOR_INT) && in esdhc_readl_le()
517 writel(SDHCI_INT_RESPONSE, host->ioaddr + in esdhc_readl_le()
519 imx_data->multiblock_status = NO_CMD_PENDING; in esdhc_readl_le()
537 * card interrupt. This is an eSDHC controller problem in esdhc_writel_le()
539 * and set D3CD bit will make eSDHC re-sample the card in esdhc_writel_le()
541 * re-sample it by the following steps. in esdhc_writel_le()
543 data = readl(host->ioaddr + SDHCI_HOST_CONTROL); in esdhc_writel_le()
545 writel(data, host->ioaddr + SDHCI_HOST_CONTROL); in esdhc_writel_le()
547 writel(data, host->ioaddr + SDHCI_HOST_CONTROL); in esdhc_writel_le()
556 if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) in esdhc_writel_le()
560 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_writel_le()
562 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_writel_le()
564 if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS) in esdhc_writel_le()
569 writel(data, host->ioaddr + SDHCI_TRANSFER_MODE); in esdhc_writel_le()
570 imx_data->multiblock_status = WAIT_FOR_INT; in esdhc_writel_le()
574 writel(val, host->ioaddr + reg); in esdhc_writel_le()
596 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_readw_le()
601 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) in esdhc_readw_le()
602 val = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_readw_le()
603 else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) in esdhc_readw_le()
605 val = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); in esdhc_readw_le()
620 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_readw_le()
628 ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE); in esdhc_readw_le()
634 return readw(host->ioaddr + reg); in esdhc_readw_le()
645 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_writew_le()
650 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_writew_le()
655 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_writew_le()
660 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_writew_le()
661 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { in esdhc_writew_le()
662 u32 v = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); in esdhc_writew_le()
663 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_writew_le()
681 writel(v, host->ioaddr + SDHCI_AUTO_CMD_STATUS); in esdhc_writew_le()
682 writel(m, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_writew_le()
686 if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) in esdhc_writew_le()
687 && (host->cmd->opcode == SD_IO_RW_EXTENDED) in esdhc_writew_le()
688 && (host->cmd->data->blocks > 1) in esdhc_writew_le()
689 && (host->cmd->data->flags & MMC_DATA_READ)) { in esdhc_writew_le()
691 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_writew_le()
693 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_writew_le()
698 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_writew_le()
705 writel(m, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_writew_le()
711 m = readl(host->ioaddr + ESDHC_WTMK_LVL); in esdhc_writew_le()
734 writel(m, host->ioaddr + ESDHC_WTMK_LVL); in esdhc_writew_le()
740 imx_data->scratchpad = val; in esdhc_writew_le()
744 if (host->cmd->opcode == MMC_STOP_TRANSMISSION) in esdhc_writew_le()
747 if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) && in esdhc_writew_le()
748 (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)) in esdhc_writew_le()
749 imx_data->multiblock_status = MULTIBLK_IN_PROCESS; in esdhc_writew_le()
753 host->ioaddr + SDHCI_TRANSFER_MODE); in esdhc_writew_le()
755 writel(val << 16 | imx_data->scratchpad, in esdhc_writew_le()
756 host->ioaddr + SDHCI_TRANSFER_MODE); in esdhc_writew_le()
772 val = readl(host->ioaddr + reg); in esdhc_readb_le()
781 return readb(host->ioaddr + reg); in esdhc_readb_le()
821 new_val = readl(host->ioaddr + SDHCI_HOST_CONTROL); in esdhc_writeb_le()
829 * The esdhc has a design violation to SDHC spec which in esdhc_writeb_le()
831 * detection circuit. But esdhc clears its SYSCTL in esdhc_writeb_le()
846 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_writeb_le()
848 host->ioaddr + ESDHC_MIX_CTRL); in esdhc_writeb_le()
849 imx_data->is_ddr = 0; in esdhc_writeb_le()
853 * The eSDHC DAT line software reset clears at least the in esdhc_writeb_le()
867 return pltfm_host->clock; in esdhc_pltfm_get_max_clock()
874 return pltfm_host->clock / 256 / 16; in esdhc_pltfm_get_min_clock()
882 unsigned int host_clock = pltfm_host->clock; in esdhc_pltfm_set_clock()
883 int ddr_pre_div = imx_data->is_ddr ? 2 : 1; in esdhc_pltfm_set_clock()
890 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_pltfm_set_clock()
892 host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_pltfm_set_clock()
897 host->mmc->actual_clock = 0; in esdhc_pltfm_set_clock()
907 val = readl(host->ioaddr + ESDHC_DLL_CTRL); in esdhc_pltfm_set_clock()
908 writel(val | BIT(10), host->ioaddr + ESDHC_DLL_CTRL); in esdhc_pltfm_set_clock()
909 temp = readl(host->ioaddr + ESDHC_DLL_CTRL); in esdhc_pltfm_set_clock()
910 writel(val, host->ioaddr + ESDHC_DLL_CTRL); in esdhc_pltfm_set_clock()
920 if (imx_data->socdata->flags & ESDHC_FLAG_ERR010450) { in esdhc_pltfm_set_clock()
923 max_clock = imx_data->is_ddr ? 45000000 : 150000000; in esdhc_pltfm_set_clock()
935 host->mmc->actual_clock = host_clock / (div * pre_div * ddr_pre_div); in esdhc_pltfm_set_clock()
936 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", in esdhc_pltfm_set_clock()
937 clock, host->mmc->actual_clock); in esdhc_pltfm_set_clock()
940 div--; in esdhc_pltfm_set_clock()
949 ret = readl_poll_timeout(host->ioaddr + ESDHC_PRSSTAT, temp, in esdhc_pltfm_set_clock()
951 if (ret == -ETIMEDOUT) in esdhc_pltfm_set_clock()
952 dev_warn(mmc_dev(host->mmc), "card clock still not stable in 100us!.\n"); in esdhc_pltfm_set_clock()
955 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_pltfm_set_clock()
957 host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_pltfm_set_clock()
966 struct esdhc_platform_data *boarddata = &imx_data->boarddata; in esdhc_pltfm_get_ro()
968 switch (boarddata->wp_type) { in esdhc_pltfm_get_ro()
970 return mmc_gpio_get_ro(host->mmc); in esdhc_pltfm_get_ro()
972 return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) & in esdhc_pltfm_get_ro()
978 return -ENOSYS; in esdhc_pltfm_get_ro()
1009 if (host->timing == MMC_TIMING_UHS_DDR50) in usdhc_execute_tuning()
1026 ret = readb_poll_timeout(host->ioaddr + SDHCI_SOFTWARE_RESET, sw_rst, in esdhc_prepare_tuning()
1028 if (ret == -ETIMEDOUT) in esdhc_prepare_tuning()
1029 dev_warn(mmc_dev(host->mmc), in esdhc_prepare_tuning()
1032 reg = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_prepare_tuning()
1035 writel(reg, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_prepare_tuning()
1036 writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); in esdhc_prepare_tuning()
1037 dev_dbg(mmc_dev(host->mmc), in esdhc_prepare_tuning()
1039 val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS)); in esdhc_prepare_tuning()
1048 reg = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_post_tuning()
1051 writel(reg, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_post_tuning()
1062 if (!mmc_send_tuning(host->mmc, opcode, NULL)) in esdhc_executing_tuning()
1071 if (mmc_send_tuning(host->mmc, opcode, NULL)) { in esdhc_executing_tuning()
1072 max -= ESDHC_TUNE_CTRL_STEP; in esdhc_executing_tuning()
1081 ret = mmc_send_tuning(host->mmc, opcode, NULL); in esdhc_executing_tuning()
1084 dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n", in esdhc_executing_tuning()
1095 m = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_hs400_enhanced_strobe()
1096 if (ios->enhanced_strobe) in esdhc_hs400_enhanced_strobe()
1100 writel(m, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_hs400_enhanced_strobe()
1110 dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs); in esdhc_change_pinstate()
1112 if (IS_ERR(imx_data->pinctrl) || in esdhc_change_pinstate()
1113 IS_ERR(imx_data->pins_100mhz) || in esdhc_change_pinstate()
1114 IS_ERR(imx_data->pins_200mhz)) in esdhc_change_pinstate()
1115 return -EINVAL; in esdhc_change_pinstate()
1120 pinctrl = imx_data->pins_100mhz; in esdhc_change_pinstate()
1125 pinctrl = imx_data->pins_200mhz; in esdhc_change_pinstate()
1129 return pinctrl_select_default_state(mmc_dev(host->mmc)); in esdhc_change_pinstate()
1132 return pinctrl_select_state(imx_data->pinctrl, pinctrl); in esdhc_change_pinstate()
1153 writel(readl(host->ioaddr + ESDHC_VENDOR_SPEC) & in esdhc_set_strobe_dll()
1155 host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_set_strobe_dll()
1160 host->ioaddr + ESDHC_STROBE_DLL_CTRL); in esdhc_set_strobe_dll()
1162 writel(0, host->ioaddr + ESDHC_STROBE_DLL_CTRL); in esdhc_set_strobe_dll()
1168 if (imx_data->boarddata.strobe_dll_delay_target) in esdhc_set_strobe_dll()
1169 strobe_delay = imx_data->boarddata.strobe_dll_delay_target; in esdhc_set_strobe_dll()
1175 writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL); in esdhc_set_strobe_dll()
1178 ret = readl_poll_timeout(host->ioaddr + ESDHC_STROBE_DLL_STATUS, v, in esdhc_set_strobe_dll()
1180 if (ret == -ETIMEDOUT) in esdhc_set_strobe_dll()
1181 dev_warn(mmc_dev(host->mmc), in esdhc_set_strobe_dll()
1194 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { in esdhc_reset_tuning()
1195 ctrl = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_reset_tuning()
1198 writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_reset_tuning()
1199 writel(0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); in esdhc_reset_tuning()
1200 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { in esdhc_reset_tuning()
1201 ctrl = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); in esdhc_reset_tuning()
1204 writel(ctrl, host->ioaddr + SDHCI_AUTO_CMD_STATUS); in esdhc_reset_tuning()
1206 ret = readl_poll_timeout(host->ioaddr + SDHCI_AUTO_CMD_STATUS, in esdhc_reset_tuning()
1208 if (ret == -ETIMEDOUT) in esdhc_reset_tuning()
1209 dev_warn(mmc_dev(host->mmc), in esdhc_reset_tuning()
1216 ctrl = readl(host->ioaddr + SDHCI_INT_STATUS); in esdhc_reset_tuning()
1218 writel(ctrl, host->ioaddr + SDHCI_INT_STATUS); in esdhc_reset_tuning()
1228 struct esdhc_platform_data *boarddata = &imx_data->boarddata; in esdhc_set_uhs_signaling()
1231 m = readl(host->ioaddr + ESDHC_MIX_CTRL); in esdhc_set_uhs_signaling()
1233 imx_data->is_ddr = 0; in esdhc_set_uhs_signaling()
1242 writel(m, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_set_uhs_signaling()
1247 writel(m, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_set_uhs_signaling()
1248 imx_data->is_ddr = 1; in esdhc_set_uhs_signaling()
1249 if (boarddata->delay_line) { in esdhc_set_uhs_signaling()
1251 v = boarddata->delay_line << in esdhc_set_uhs_signaling()
1256 writel(v, host->ioaddr + ESDHC_DLL_CTRL); in esdhc_set_uhs_signaling()
1261 writel(m, host->ioaddr + ESDHC_MIX_CTRL); in esdhc_set_uhs_signaling()
1262 imx_data->is_ddr = 1; in esdhc_set_uhs_signaling()
1264 host->ops->set_clock(host, host->clock); in esdhc_set_uhs_signaling()
1280 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); in esdhc_reset()
1281 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); in esdhc_reset()
1312 cqhci_irq(host->mmc, intmask, cmd_error, data_error); in esdhc_cqhci_irq()
1349 struct cqhci_host *cq_host = host->mmc->cqe_private; in sdhci_esdhc_imx_hwinit()
1357 writel(ESDHC_WTMK_DEFAULT_VAL, host->ioaddr + ESDHC_WTMK_LVL); in sdhci_esdhc_imx_hwinit()
1370 writel(readl(host->ioaddr + SDHCI_HOST_CONTROL) in sdhci_esdhc_imx_hwinit()
1372 host->ioaddr + SDHCI_HOST_CONTROL); in sdhci_esdhc_imx_hwinit()
1378 writel(readl(host->ioaddr + 0x6c) & ~BIT(7), in sdhci_esdhc_imx_hwinit()
1379 host->ioaddr + 0x6c); in sdhci_esdhc_imx_hwinit()
1382 writel(0x0, host->ioaddr + ESDHC_DLL_CTRL); in sdhci_esdhc_imx_hwinit()
1393 if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) { in sdhci_esdhc_imx_hwinit()
1394 tmp = readl(host->ioaddr + ESDHC_VEND_SPEC2); in sdhci_esdhc_imx_hwinit()
1396 writel(tmp, host->ioaddr + ESDHC_VEND_SPEC2); in sdhci_esdhc_imx_hwinit()
1398 host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ; in sdhci_esdhc_imx_hwinit()
1401 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { in sdhci_esdhc_imx_hwinit()
1402 tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL); in sdhci_esdhc_imx_hwinit()
1405 if (imx_data->boarddata.tuning_start_tap) { in sdhci_esdhc_imx_hwinit()
1407 tmp |= imx_data->boarddata.tuning_start_tap; in sdhci_esdhc_imx_hwinit()
1410 if (imx_data->boarddata.tuning_step) { in sdhci_esdhc_imx_hwinit()
1412 tmp |= imx_data->boarddata.tuning_step in sdhci_esdhc_imx_hwinit()
1427 writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL); in sdhci_esdhc_imx_hwinit()
1428 } else if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { in sdhci_esdhc_imx_hwinit()
1434 tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL); in sdhci_esdhc_imx_hwinit()
1436 writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL); in sdhci_esdhc_imx_hwinit()
1459 struct cqhci_host *cq_host = mmc->cqe_private; in esdhc_cqe_enable()
1472 if (count-- == 0) { in esdhc_cqe_enable()
1473 dev_warn(mmc_dev(host->mmc), in esdhc_cqe_enable()
1486 if (host->flags & SDHCI_REQ_USE_DMA) in esdhc_cqe_enable()
1488 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE)) in esdhc_cqe_enable()
1500 dev_err(mmc_dev(host->mmc), in esdhc_cqe_enable()
1523 struct device_node *np = pdev->dev.of_node; in sdhci_esdhc_imx_probe_dt()
1524 struct esdhc_platform_data *boarddata = &imx_data->boarddata; in sdhci_esdhc_imx_probe_dt()
1527 if (of_get_property(np, "fsl,wp-controller", NULL)) in sdhci_esdhc_imx_probe_dt()
1528 boarddata->wp_type = ESDHC_WP_CONTROLLER; in sdhci_esdhc_imx_probe_dt()
1535 if (of_property_read_bool(np, "wp-gpios")) in sdhci_esdhc_imx_probe_dt()
1536 boarddata->wp_type = ESDHC_WP_GPIO; in sdhci_esdhc_imx_probe_dt()
1538 of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step); in sdhci_esdhc_imx_probe_dt()
1539 of_property_read_u32(np, "fsl,tuning-start-tap", in sdhci_esdhc_imx_probe_dt()
1540 &boarddata->tuning_start_tap); in sdhci_esdhc_imx_probe_dt()
1542 of_property_read_u32(np, "fsl,strobe-dll-delay-target", in sdhci_esdhc_imx_probe_dt()
1543 &boarddata->strobe_dll_delay_target); in sdhci_esdhc_imx_probe_dt()
1544 if (of_find_property(np, "no-1-8-v", NULL)) in sdhci_esdhc_imx_probe_dt()
1545 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; in sdhci_esdhc_imx_probe_dt()
1547 if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line)) in sdhci_esdhc_imx_probe_dt()
1548 boarddata->delay_line = 0; in sdhci_esdhc_imx_probe_dt()
1550 mmc_of_parse_voltage(host->mmc, &host->ocr_mask); in sdhci_esdhc_imx_probe_dt()
1552 if (esdhc_is_usdhc(imx_data) && !IS_ERR(imx_data->pinctrl)) { in sdhci_esdhc_imx_probe_dt()
1553 imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl, in sdhci_esdhc_imx_probe_dt()
1555 imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl, in sdhci_esdhc_imx_probe_dt()
1560 ret = mmc_of_parse(host->mmc); in sdhci_esdhc_imx_probe_dt()
1564 if (mmc_gpio_get_cd(host->mmc) >= 0) in sdhci_esdhc_imx_probe_dt()
1565 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; in sdhci_esdhc_imx_probe_dt()
1587 imx_data->socdata = device_get_match_data(&pdev->dev); in sdhci_esdhc_imx_probe()
1589 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) in sdhci_esdhc_imx_probe()
1590 cpu_latency_qos_add_request(&imx_data->pm_qos_req, 0); in sdhci_esdhc_imx_probe()
1592 imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); in sdhci_esdhc_imx_probe()
1593 if (IS_ERR(imx_data->clk_ipg)) { in sdhci_esdhc_imx_probe()
1594 err = PTR_ERR(imx_data->clk_ipg); in sdhci_esdhc_imx_probe()
1598 imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); in sdhci_esdhc_imx_probe()
1599 if (IS_ERR(imx_data->clk_ahb)) { in sdhci_esdhc_imx_probe()
1600 err = PTR_ERR(imx_data->clk_ahb); in sdhci_esdhc_imx_probe()
1604 imx_data->clk_per = devm_clk_get(&pdev->dev, "per"); in sdhci_esdhc_imx_probe()
1605 if (IS_ERR(imx_data->clk_per)) { in sdhci_esdhc_imx_probe()
1606 err = PTR_ERR(imx_data->clk_per); in sdhci_esdhc_imx_probe()
1610 pltfm_host->clk = imx_data->clk_per; in sdhci_esdhc_imx_probe()
1611 pltfm_host->clock = clk_get_rate(pltfm_host->clk); in sdhci_esdhc_imx_probe()
1612 err = clk_prepare_enable(imx_data->clk_per); in sdhci_esdhc_imx_probe()
1615 err = clk_prepare_enable(imx_data->clk_ipg); in sdhci_esdhc_imx_probe()
1618 err = clk_prepare_enable(imx_data->clk_ahb); in sdhci_esdhc_imx_probe()
1622 imx_data->pinctrl = devm_pinctrl_get(&pdev->dev); in sdhci_esdhc_imx_probe()
1623 if (IS_ERR(imx_data->pinctrl)) in sdhci_esdhc_imx_probe()
1624 dev_warn(mmc_dev(host->mmc), "could not get pinctrl\n"); in sdhci_esdhc_imx_probe()
1627 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; in sdhci_esdhc_imx_probe()
1628 host->mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR; in sdhci_esdhc_imx_probe()
1631 host->mmc->caps |= MMC_CAP_CD_WAKE; in sdhci_esdhc_imx_probe()
1633 if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200)) in sdhci_esdhc_imx_probe()
1634 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; in sdhci_esdhc_imx_probe()
1637 writel(0x0, host->ioaddr + ESDHC_MIX_CTRL); in sdhci_esdhc_imx_probe()
1638 writel(0x0, host->ioaddr + SDHCI_AUTO_CMD_STATUS); in sdhci_esdhc_imx_probe()
1639 writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); in sdhci_esdhc_imx_probe()
1645 host->mmc_host_ops.execute_tuning = usdhc_execute_tuning; in sdhci_esdhc_imx_probe()
1648 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) in sdhci_esdhc_imx_probe()
1652 if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536) in sdhci_esdhc_imx_probe()
1653 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; in sdhci_esdhc_imx_probe()
1655 if (imx_data->socdata->flags & ESDHC_FLAG_HS400) in sdhci_esdhc_imx_probe()
1656 host->mmc->caps2 |= MMC_CAP2_HS400; in sdhci_esdhc_imx_probe()
1658 if (imx_data->socdata->flags & ESDHC_FLAG_BROKEN_AUTO_CMD23) in sdhci_esdhc_imx_probe()
1659 host->quirks2 |= SDHCI_QUIRK2_ACMD23_BROKEN; in sdhci_esdhc_imx_probe()
1661 if (imx_data->socdata->flags & ESDHC_FLAG_HS400_ES) { in sdhci_esdhc_imx_probe()
1662 host->mmc->caps2 |= MMC_CAP2_HS400_ES; in sdhci_esdhc_imx_probe()
1663 host->mmc_host_ops.hs400_enhanced_strobe = in sdhci_esdhc_imx_probe()
1667 if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) { in sdhci_esdhc_imx_probe()
1668 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; in sdhci_esdhc_imx_probe()
1669 cq_host = devm_kzalloc(&pdev->dev, sizeof(*cq_host), GFP_KERNEL); in sdhci_esdhc_imx_probe()
1671 err = -ENOMEM; in sdhci_esdhc_imx_probe()
1675 cq_host->mmio = host->ioaddr + ESDHC_CQHCI_ADDR_OFFSET; in sdhci_esdhc_imx_probe()
1676 cq_host->ops = &esdhc_cqhci_ops; in sdhci_esdhc_imx_probe()
1678 err = cqhci_init(cq_host, host->mmc, false); in sdhci_esdhc_imx_probe()
1697 if ((host->mmc->pm_caps & MMC_PM_KEEP_POWER) && in sdhci_esdhc_imx_probe()
1698 (host->mmc->pm_caps & MMC_PM_WAKE_SDIO_IRQ)) in sdhci_esdhc_imx_probe()
1699 device_set_wakeup_capable(&pdev->dev, true); in sdhci_esdhc_imx_probe()
1701 pm_runtime_set_active(&pdev->dev); in sdhci_esdhc_imx_probe()
1702 pm_runtime_set_autosuspend_delay(&pdev->dev, 50); in sdhci_esdhc_imx_probe()
1703 pm_runtime_use_autosuspend(&pdev->dev); in sdhci_esdhc_imx_probe()
1704 pm_suspend_ignore_children(&pdev->dev, 1); in sdhci_esdhc_imx_probe()
1705 pm_runtime_enable(&pdev->dev); in sdhci_esdhc_imx_probe()
1710 clk_disable_unprepare(imx_data->clk_ahb); in sdhci_esdhc_imx_probe()
1712 clk_disable_unprepare(imx_data->clk_ipg); in sdhci_esdhc_imx_probe()
1714 clk_disable_unprepare(imx_data->clk_per); in sdhci_esdhc_imx_probe()
1716 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) in sdhci_esdhc_imx_probe()
1717 cpu_latency_qos_remove_request(&imx_data->pm_qos_req); in sdhci_esdhc_imx_probe()
1729 pm_runtime_get_sync(&pdev->dev); in sdhci_esdhc_imx_remove()
1730 dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff); in sdhci_esdhc_imx_remove()
1731 pm_runtime_disable(&pdev->dev); in sdhci_esdhc_imx_remove()
1732 pm_runtime_put_noidle(&pdev->dev); in sdhci_esdhc_imx_remove()
1736 clk_disable_unprepare(imx_data->clk_per); in sdhci_esdhc_imx_remove()
1737 clk_disable_unprepare(imx_data->clk_ipg); in sdhci_esdhc_imx_remove()
1738 clk_disable_unprepare(imx_data->clk_ahb); in sdhci_esdhc_imx_remove()
1740 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) in sdhci_esdhc_imx_remove()
1741 cpu_latency_qos_remove_request(&imx_data->pm_qos_req); in sdhci_esdhc_imx_remove()
1756 if (host->mmc->caps2 & MMC_CAP2_CQE) { in sdhci_esdhc_suspend()
1757 ret = cqhci_suspend(host->mmc); in sdhci_esdhc_suspend()
1762 if ((imx_data->socdata->flags & ESDHC_FLAG_STATE_LOST_IN_LPMODE) && in sdhci_esdhc_suspend()
1763 (host->tuning_mode != SDHCI_TUNING_MODE_1)) { in sdhci_esdhc_suspend()
1764 mmc_retune_timer_stop(host->mmc); in sdhci_esdhc_suspend()
1765 mmc_retune_needed(host->mmc); in sdhci_esdhc_suspend()
1768 if (host->tuning_mode != SDHCI_TUNING_MODE_3) in sdhci_esdhc_suspend()
1769 mmc_retune_needed(host->mmc); in sdhci_esdhc_suspend()
1779 ret = mmc_gpio_set_cd_wake(host->mmc, true); in sdhci_esdhc_suspend()
1793 /* re-initialize hw state in case it's lost in low power mode */ in sdhci_esdhc_resume()
1800 if (host->mmc->caps2 & MMC_CAP2_CQE) in sdhci_esdhc_resume()
1801 ret = cqhci_resume(host->mmc); in sdhci_esdhc_resume()
1804 ret = mmc_gpio_set_cd_wake(host->mmc, false); in sdhci_esdhc_resume()
1818 if (host->mmc->caps2 & MMC_CAP2_CQE) { in sdhci_esdhc_runtime_suspend()
1819 ret = cqhci_suspend(host->mmc); in sdhci_esdhc_runtime_suspend()
1828 if (host->tuning_mode != SDHCI_TUNING_MODE_3) in sdhci_esdhc_runtime_suspend()
1829 mmc_retune_needed(host->mmc); in sdhci_esdhc_runtime_suspend()
1831 imx_data->actual_clock = host->mmc->actual_clock; in sdhci_esdhc_runtime_suspend()
1833 clk_disable_unprepare(imx_data->clk_per); in sdhci_esdhc_runtime_suspend()
1834 clk_disable_unprepare(imx_data->clk_ipg); in sdhci_esdhc_runtime_suspend()
1835 clk_disable_unprepare(imx_data->clk_ahb); in sdhci_esdhc_runtime_suspend()
1837 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) in sdhci_esdhc_runtime_suspend()
1838 cpu_latency_qos_remove_request(&imx_data->pm_qos_req); in sdhci_esdhc_runtime_suspend()
1850 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) in sdhci_esdhc_runtime_resume()
1851 cpu_latency_qos_add_request(&imx_data->pm_qos_req, 0); in sdhci_esdhc_runtime_resume()
1853 if (imx_data->socdata->flags & ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME) in sdhci_esdhc_runtime_resume()
1854 clk_set_rate(imx_data->clk_per, pltfm_host->clock); in sdhci_esdhc_runtime_resume()
1856 err = clk_prepare_enable(imx_data->clk_ahb); in sdhci_esdhc_runtime_resume()
1860 err = clk_prepare_enable(imx_data->clk_per); in sdhci_esdhc_runtime_resume()
1864 err = clk_prepare_enable(imx_data->clk_ipg); in sdhci_esdhc_runtime_resume()
1868 esdhc_pltfm_set_clock(host, imx_data->actual_clock); in sdhci_esdhc_runtime_resume()
1874 if (host->mmc->caps2 & MMC_CAP2_CQE) in sdhci_esdhc_runtime_resume()
1875 err = cqhci_resume(host->mmc); in sdhci_esdhc_runtime_resume()
1880 clk_disable_unprepare(imx_data->clk_ipg); in sdhci_esdhc_runtime_resume()
1882 clk_disable_unprepare(imx_data->clk_per); in sdhci_esdhc_runtime_resume()
1884 clk_disable_unprepare(imx_data->clk_ahb); in sdhci_esdhc_runtime_resume()
1886 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) in sdhci_esdhc_runtime_resume()
1887 cpu_latency_qos_remove_request(&imx_data->pm_qos_req); in sdhci_esdhc_runtime_resume()
1900 .name = "sdhci-esdhc-imx",
1911 MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC");