1 // SPDX-License-Identifier: GPL-2.0-or-later
3  * Actions Semi Owl SoCs SD/MMC driver
14 #include <linux/dma-direction.h>
15 #include <linux/dma-mapping.h>
17 #include <linux/mmc/host.h>
18 #include <linux/mmc/slot-gpio.h>
114 	struct mmc_host	*mmc;  member
139 	spin_lock(&owl_host->lock);  in owl_irq_handler()
141 	state = readl(owl_host->base + OWL_REG_SD_STATE);  in owl_irq_handler()
143 		state = readl(owl_host->base + OWL_REG_SD_STATE);  in owl_irq_handler()
145 		writel(state, owl_host->base + OWL_REG_SD_STATE);  in owl_irq_handler()
146 		complete(&owl_host->sdc_complete);  in owl_irq_handler()
149 	spin_unlock(&owl_host->lock);  in owl_irq_handler()
156 	struct mmc_request *mrq = owl_host->mrq;  in owl_mmc_finish_request()
157 	struct mmc_data *data = mrq->data;  in owl_mmc_finish_request()
162 	owl_host->mrq = NULL;  in owl_mmc_finish_request()
165 		dma_unmap_sg(owl_host->dma->device->dev, data->sg, data->sg_len,  in owl_mmc_finish_request()
166 			     owl_host->dma_dir);  in owl_mmc_finish_request()
169 	mmc_request_done(owl_host->mmc, mrq);  in owl_mmc_finish_request()
180 	init_completion(&owl_host->sdc_complete);  in owl_mmc_send_cmd()
189 			if (data->flags & MMC_DATA_READ)  in owl_mmc_send_cmd()
216 		dev_warn(owl_host->dev, "Unknown MMC command\n");  in owl_mmc_send_cmd()
217 		cmd->error = -EINVAL;  in owl_mmc_send_cmd()
222 	mode |= (readl(owl_host->base + OWL_REG_SD_CTL) & (0xff << 16));  in owl_mmc_send_cmd()
225 	writel(cmd->arg, owl_host->base + OWL_REG_SD_ARG);  in owl_mmc_send_cmd()
226 	writel(cmd->opcode, owl_host->base + OWL_REG_SD_CMD);  in owl_mmc_send_cmd()
236 	owl_host->cmd = cmd;  in owl_mmc_send_cmd()
239 	writel(mode, owl_host->base + OWL_REG_SD_CTL);  in owl_mmc_send_cmd()
244 	timeout = msecs_to_jiffies(cmd->busy_timeout ? cmd->busy_timeout :  in owl_mmc_send_cmd()
247 	if (!wait_for_completion_timeout(&owl_host->sdc_complete, timeout)) {  in owl_mmc_send_cmd()
248 		dev_err(owl_host->dev, "CMD interrupt timeout\n");  in owl_mmc_send_cmd()
249 		cmd->error = -ETIMEDOUT;  in owl_mmc_send_cmd()
253 	state = readl(owl_host->base + OWL_REG_SD_STATE);  in owl_mmc_send_cmd()
257 				dev_err(owl_host->dev, "Error CMD_NO_RSP\n");  in owl_mmc_send_cmd()
258 				cmd->error = -EILSEQ;  in owl_mmc_send_cmd()
263 				dev_err(owl_host->dev, "Error CMD_RSP_CRC\n");  in owl_mmc_send_cmd()
264 				cmd->error = -EILSEQ;  in owl_mmc_send_cmd()
270 			cmd->resp[3] = readl(owl_host->base + OWL_REG_SD_RSPBUF0);  in owl_mmc_send_cmd()
271 			cmd->resp[2] = readl(owl_host->base + OWL_REG_SD_RSPBUF1);  in owl_mmc_send_cmd()
272 			cmd->resp[1] = readl(owl_host->base + OWL_REG_SD_RSPBUF2);  in owl_mmc_send_cmd()
273 			cmd->resp[0] = readl(owl_host->base + OWL_REG_SD_RSPBUF3);  in owl_mmc_send_cmd()
275 			resp[0] = readl(owl_host->base + OWL_REG_SD_RSPBUF0);  in owl_mmc_send_cmd()
276 			resp[1] = readl(owl_host->base + OWL_REG_SD_RSPBUF1);  in owl_mmc_send_cmd()
277 			cmd->resp[0] = resp[1] << 24 | resp[0] >> 8;  in owl_mmc_send_cmd()
278 			cmd->resp[1] = resp[1] >> 8;  in owl_mmc_send_cmd()
286 	struct mmc_data *data = owl_host->data;  in owl_mmc_dma_complete()
289 		complete(&owl_host->dma_complete);  in owl_mmc_dma_complete()
297 	owl_mmc_update_reg(owl_host->base + OWL_REG_SD_EN, OWL_SD_EN_BSEL,  in owl_mmc_prepare_data()
299 	writel(data->blocks, owl_host->base + OWL_REG_SD_BLK_NUM);  in owl_mmc_prepare_data()
300 	writel(data->blksz, owl_host->base + OWL_REG_SD_BLK_SIZE);  in owl_mmc_prepare_data()
301 	total = data->blksz * data->blocks;  in owl_mmc_prepare_data()
304 		writel(total, owl_host->base + OWL_REG_SD_BUF_SIZE);  in owl_mmc_prepare_data()
306 		writel(512, owl_host->base + OWL_REG_SD_BUF_SIZE);  in owl_mmc_prepare_data()
308 	if (data->flags & MMC_DATA_WRITE) {  in owl_mmc_prepare_data()
309 		owl_host->dma_dir = DMA_TO_DEVICE;  in owl_mmc_prepare_data()
310 		owl_host->dma_cfg.direction = DMA_MEM_TO_DEV;  in owl_mmc_prepare_data()
312 		owl_host->dma_dir = DMA_FROM_DEVICE;  in owl_mmc_prepare_data()
313 		owl_host->dma_cfg.direction = DMA_DEV_TO_MEM;  in owl_mmc_prepare_data()
316 	dma_map_sg(owl_host->dma->device->dev, data->sg,  in owl_mmc_prepare_data()
317 		   data->sg_len, owl_host->dma_dir);  in owl_mmc_prepare_data()
319 	dmaengine_slave_config(owl_host->dma, &owl_host->dma_cfg);  in owl_mmc_prepare_data()
320 	owl_host->desc = dmaengine_prep_slave_sg(owl_host->dma, data->sg,  in owl_mmc_prepare_data()
321 						 data->sg_len,  in owl_mmc_prepare_data()
322 						 owl_host->dma_cfg.direction,  in owl_mmc_prepare_data()
325 	if (!owl_host->desc) {  in owl_mmc_prepare_data()
326 		dev_err(owl_host->dev, "Can't prepare slave sg\n");  in owl_mmc_prepare_data()
327 		return -EBUSY;  in owl_mmc_prepare_data()
330 	owl_host->data = data;  in owl_mmc_prepare_data()
332 	owl_host->desc->callback = owl_mmc_dma_complete;  in owl_mmc_prepare_data()
333 	owl_host->desc->callback_param = (void *)owl_host;  in owl_mmc_prepare_data()
334 	data->error = 0;  in owl_mmc_prepare_data()
339 static void owl_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)  in owl_mmc_request()  argument
341 	struct owl_mmc_host *owl_host = mmc_priv(mmc);  in owl_mmc_request()
342 	struct mmc_data *data = mrq->data;  in owl_mmc_request()
345 	owl_host->mrq = mrq;  in owl_mmc_request()
346 	if (mrq->data) {  in owl_mmc_request()
349 			data->error = ret;  in owl_mmc_request()
353 		init_completion(&owl_host->dma_complete);  in owl_mmc_request()
354 		dmaengine_submit(owl_host->desc);  in owl_mmc_request()
355 		dma_async_issue_pending(owl_host->dma);  in owl_mmc_request()
358 	owl_mmc_send_cmd(owl_host, mrq->cmd, data);  in owl_mmc_request()
361 		if (!wait_for_completion_timeout(&owl_host->sdc_complete,  in owl_mmc_request()
363 			dev_err(owl_host->dev, "CMD interrupt timeout\n");  in owl_mmc_request()
364 			mrq->cmd->error = -ETIMEDOUT;  in owl_mmc_request()
365 			dmaengine_terminate_all(owl_host->dma);  in owl_mmc_request()
369 		if (!wait_for_completion_timeout(&owl_host->dma_complete,  in owl_mmc_request()
371 			dev_err(owl_host->dev, "DMA interrupt timeout\n");  in owl_mmc_request()
372 			mrq->cmd->error = -ETIMEDOUT;  in owl_mmc_request()
373 			dmaengine_terminate_all(owl_host->dma);  in owl_mmc_request()
377 		if (data->stop)  in owl_mmc_request()
378 			owl_mmc_send_cmd(owl_host, data->stop, NULL);  in owl_mmc_request()
380 		data->bytes_xfered = data->blocks * data->blksz;  in owl_mmc_request()
394 	reg = readl(owl_host->base + OWL_REG_SD_CTL);  in owl_mmc_set_clk_rate()
401 		       owl_host->base + OWL_REG_SD_CTL);  in owl_mmc_set_clk_rate()
405 		       owl_host->base + OWL_REG_SD_CTL);  in owl_mmc_set_clk_rate()
406 	} else if ((rate > 26000000) && (rate <= 52000000) && !owl_host->ddr_50) {  in owl_mmc_set_clk_rate()
409 		       owl_host->base + OWL_REG_SD_CTL);  in owl_mmc_set_clk_rate()
411 	} else if ((rate > 26000000) && (rate <= 52000000) && owl_host->ddr_50) {  in owl_mmc_set_clk_rate()
414 		       owl_host->base + OWL_REG_SD_CTL);  in owl_mmc_set_clk_rate()
416 		dev_err(owl_host->dev, "SD clock rate not supported\n");  in owl_mmc_set_clk_rate()
417 		return -EINVAL;  in owl_mmc_set_clk_rate()
420 	clk_rate = clk_round_rate(owl_host->clk, rate << 1);  in owl_mmc_set_clk_rate()
421 	ret = clk_set_rate(owl_host->clk, clk_rate);  in owl_mmc_set_clk_rate()
428 	if (!ios->clock)  in owl_mmc_set_clk()
431 	owl_host->clock = ios->clock;  in owl_mmc_set_clk()
432 	owl_mmc_set_clk_rate(owl_host, ios->clock);  in owl_mmc_set_clk()
440 	reg = readl(owl_host->base + OWL_REG_SD_EN);  in owl_mmc_set_bus_width()
442 	switch (ios->bus_width) {  in owl_mmc_set_bus_width()
453 	writel(reg, owl_host->base + OWL_REG_SD_EN);  in owl_mmc_set_bus_width()
458 	reset_control_assert(owl_host->reset);  in owl_mmc_ctr_reset()
460 	reset_control_deassert(owl_host->reset);  in owl_mmc_ctr_reset()
467 	init_completion(&owl_host->sdc_complete);  in owl_mmc_power_on()
470 	owl_mmc_update_reg(owl_host->base + OWL_REG_SD_STATE,  in owl_mmc_power_on()
474 	mode = (readl(owl_host->base + OWL_REG_SD_CTL) & (0xff << 16));  in owl_mmc_power_on()
476 	writel(mode, owl_host->base + OWL_REG_SD_CTL);  in owl_mmc_power_on()
478 	if (!wait_for_completion_timeout(&owl_host->sdc_complete, HZ)) {  in owl_mmc_power_on()
479 		dev_err(owl_host->dev, "CMD interrupt timeout\n");  in owl_mmc_power_on()
484 static void owl_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)  in owl_mmc_set_ios()  argument
486 	struct owl_mmc_host *owl_host = mmc_priv(mmc);  in owl_mmc_set_ios()
488 	switch (ios->power_mode) {  in owl_mmc_set_ios()
490 		dev_dbg(owl_host->dev, "Powering card up\n");  in owl_mmc_set_ios()
494 		clk_prepare_enable(owl_host->clk);  in owl_mmc_set_ios()
496 		       owl_host->base + OWL_REG_SD_EN);  in owl_mmc_set_ios()
501 		dev_dbg(owl_host->dev, "Powering card on\n");  in owl_mmc_set_ios()
507 		dev_dbg(owl_host->dev, "Powering card off\n");  in owl_mmc_set_ios()
508 		clk_disable_unprepare(owl_host->clk);  in owl_mmc_set_ios()
513 		dev_dbg(owl_host->dev, "Ignoring unknown card power state\n");  in owl_mmc_set_ios()
517 	if (ios->clock != owl_host->clock)  in owl_mmc_set_ios()
523 	if (ios->timing == MMC_TIMING_UHS_DDR50) {  in owl_mmc_set_ios()
524 		owl_host->ddr_50 = true;  in owl_mmc_set_ios()
525 		owl_mmc_update_reg(owl_host->base + OWL_REG_SD_EN,  in owl_mmc_set_ios()
528 		owl_host->ddr_50 = false;  in owl_mmc_set_ios()
532 static int owl_mmc_start_signal_voltage_switch(struct mmc_host *mmc,  in owl_mmc_start_signal_voltage_switch()  argument
535 	struct owl_mmc_host *owl_host = mmc_priv(mmc);  in owl_mmc_start_signal_voltage_switch()
538 	switch (ios->signal_voltage) {  in owl_mmc_start_signal_voltage_switch()
540 		owl_mmc_update_reg(owl_host->base + OWL_REG_SD_EN,  in owl_mmc_start_signal_voltage_switch()
544 		owl_mmc_update_reg(owl_host->base + OWL_REG_SD_EN,  in owl_mmc_start_signal_voltage_switch()
548 		return -ENOTSUPP;  in owl_mmc_start_signal_voltage_switch()
565 	struct mmc_host *mmc;  in owl_mmc_probe()  local
569 	mmc = mmc_alloc_host(sizeof(struct owl_mmc_host), &pdev->dev);  in owl_mmc_probe()
570 	if (!mmc) {  in owl_mmc_probe()
571 		dev_err(&pdev->dev, "mmc alloc host failed\n");  in owl_mmc_probe()
572 		return -ENOMEM;  in owl_mmc_probe()
574 	platform_set_drvdata(pdev, mmc);  in owl_mmc_probe()
576 	owl_host = mmc_priv(mmc);  in owl_mmc_probe()
577 	owl_host->dev = &pdev->dev;  in owl_mmc_probe()
578 	owl_host->mmc = mmc;  in owl_mmc_probe()
579 	spin_lock_init(&owl_host->lock);  in owl_mmc_probe()
582 	owl_host->base = devm_ioremap_resource(&pdev->dev, res);  in owl_mmc_probe()
583 	if (IS_ERR(owl_host->base)) {  in owl_mmc_probe()
584 		ret = PTR_ERR(owl_host->base);  in owl_mmc_probe()
588 	owl_host->clk = devm_clk_get(&pdev->dev, NULL);  in owl_mmc_probe()
589 	if (IS_ERR(owl_host->clk)) {  in owl_mmc_probe()
590 		dev_err(&pdev->dev, "No clock defined\n");  in owl_mmc_probe()
591 		ret = PTR_ERR(owl_host->clk);  in owl_mmc_probe()
595 	owl_host->reset = devm_reset_control_get_exclusive(&pdev->dev, NULL);  in owl_mmc_probe()
596 	if (IS_ERR(owl_host->reset)) {  in owl_mmc_probe()
597 		dev_err(&pdev->dev, "Could not get reset control\n");  in owl_mmc_probe()
598 		ret = PTR_ERR(owl_host->reset);  in owl_mmc_probe()
602 	mmc->ops		= &owl_mmc_ops;  in owl_mmc_probe()
603 	mmc->max_blk_count	= 512;  in owl_mmc_probe()
604 	mmc->max_blk_size	= 512;  in owl_mmc_probe()
605 	mmc->max_segs		= 256;  in owl_mmc_probe()
606 	mmc->max_seg_size	= 262144;  in owl_mmc_probe()
607 	mmc->max_req_size	= 262144;  in owl_mmc_probe()
609 	mmc->f_min		= 100000;  in owl_mmc_probe()
610 	mmc->f_max		= 52000000;  in owl_mmc_probe()
611 	mmc->caps	       |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |  in owl_mmc_probe()
613 	mmc->caps2		= (MMC_CAP2_BOOTPART_NOACC | MMC_CAP2_NO_SDIO);  in owl_mmc_probe()
614 	mmc->ocr_avail		= MMC_VDD_32_33 | MMC_VDD_33_34 |  in owl_mmc_probe()
617 	ret = mmc_of_parse(mmc);  in owl_mmc_probe()
621 	pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);  in owl_mmc_probe()
622 	pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;  in owl_mmc_probe()
623 	owl_host->dma = dma_request_chan(&pdev->dev, "mmc");  in owl_mmc_probe()
624 	if (IS_ERR(owl_host->dma)) {  in owl_mmc_probe()
625 		dev_err(owl_host->dev, "Failed to get external DMA channel.\n");  in owl_mmc_probe()
626 		ret = PTR_ERR(owl_host->dma);  in owl_mmc_probe()
630 	dev_info(&pdev->dev, "Using %s for DMA transfers\n",  in owl_mmc_probe()
631 		 dma_chan_name(owl_host->dma));  in owl_mmc_probe()
633 	owl_host->dma_cfg.src_addr = res->start + OWL_REG_SD_DAT;  in owl_mmc_probe()
634 	owl_host->dma_cfg.dst_addr = res->start + OWL_REG_SD_DAT;  in owl_mmc_probe()
635 	owl_host->dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;  in owl_mmc_probe()
636 	owl_host->dma_cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;  in owl_mmc_probe()
637 	owl_host->dma_cfg.device_fc = false;  in owl_mmc_probe()
639 	owl_host->irq = platform_get_irq(pdev, 0);  in owl_mmc_probe()
640 	if (owl_host->irq < 0) {  in owl_mmc_probe()
641 		ret = -EINVAL;  in owl_mmc_probe()
645 	ret = devm_request_irq(&pdev->dev, owl_host->irq, owl_irq_handler,  in owl_mmc_probe()
646 			       0, dev_name(&pdev->dev), owl_host);  in owl_mmc_probe()
648 		dev_err(&pdev->dev, "Failed to request irq %d\n",  in owl_mmc_probe()
649 			owl_host->irq);  in owl_mmc_probe()
653 	ret = mmc_add_host(mmc);  in owl_mmc_probe()
655 		dev_err(&pdev->dev, "Failed to add host\n");  in owl_mmc_probe()
659 	dev_dbg(&pdev->dev, "Owl MMC Controller Initialized\n");  in owl_mmc_probe()
664 	dma_release_channel(owl_host->dma);  in owl_mmc_probe()
666 	mmc_free_host(mmc);  in owl_mmc_probe()
673 	struct mmc_host	*mmc = platform_get_drvdata(pdev);  in owl_mmc_remove()  local
674 	struct owl_mmc_host *owl_host = mmc_priv(mmc);  in owl_mmc_remove()
676 	mmc_remove_host(mmc);  in owl_mmc_remove()
677 	disable_irq(owl_host->irq);  in owl_mmc_remove()
678 	dma_release_channel(owl_host->dma);  in owl_mmc_remove()
679 	mmc_free_host(mmc);  in owl_mmc_remove()
685 	{.compatible = "actions,owl-mmc",},
701 MODULE_DESCRIPTION("Actions Semi Owl SoCs SD/MMC Driver");