Lines Matching defs:msdc_host

412 struct msdc_host {  struct
413 	struct device *dev;
414 	const struct mtk_mmc_compatible *dev_comp;
415 	int cmd_rsp;
417 	spinlock_t lock;
418 	struct mmc_request *mrq;
419 	struct mmc_command *cmd;
420 	struct mmc_data *data;
421 	int error;
423 	void __iomem *base;		/* host base address */
424 	void __iomem *top_base;		/* host top register base address */
426 	struct msdc_dma dma;	/* dma channel */
427 	u64 dma_mask;
429 	u32 timeout_ns;		/* data timeout ns */
430 	u32 timeout_clks;	/* data timeout clks */
432 	struct pinctrl *pinctrl;
433 	struct pinctrl_state *pins_default;
434 	struct pinctrl_state *pins_uhs;
435 	struct delayed_work req_timeout;
436 	int irq;		/* host interrupt */
437 	struct reset_control *reset;
439 	struct clk *src_clk;	/* msdc source clock */
440 	struct clk *h_clk;      /* msdc h_clk */
441 	struct clk *bus_clk;	/* bus clock which used to access register */
442 	struct clk *src_clk_cg; /* msdc source clock control gate */
443 	struct clk *sys_clk_cg;	/* msdc subsys clock control gate */
444 	struct clk_bulk_data bulk_clks[MSDC_NR_CLOCKS];
445 	u32 mclk;		/* mmc subsystem clock frequency */
446 	u32 src_clk_freq;	/* source clock frequency */
447 	unsigned char timing;
448 	bool vqmmc_enabled;
449 	u32 latch_ck;
450 	u32 hs400_ds_delay;
451 	u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */
452 	u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */
453 	bool hs400_cmd_resp_sel_rising;
455 	bool hs400_mode;	/* current eMMC will run at hs400 mode */
456 	bool internal_cd;	/* Use internal card-detect logic */
457 	bool cqhci;		/* support eMMC hw cmdq */
458 	struct msdc_save_para save_para; /* used when gate HCLK */
459 	struct msdc_tune_para def_tune_para; /* default tune setting */
460 	struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */
461 	struct cqhci_host *cq_host;