Lines Matching +full:fifo +full:- +full:watermark +full:- +full:aligned
1 // SPDX-License-Identifier: GPL-2.0-or-later
14 #include <linux/dma-mapping.h>
39 #include <linux/mmc/slot-gpio.h>
74 ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \
79 u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/
80 u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/
82 u32 des6; /* Lower 32-bits of Next Descriptor Address */
83 u32 des7; /* Upper 32-bits of Next Descriptor Address */
98 ((d)->des1 = ((d)->des1 & cpu_to_le32(0x03ffe000)) | (cpu_to_le32((s) & 0x1fff)))
111 struct dw_mci_slot *slot = s->private; in dw_mci_req_show()
118 spin_lock_bh(&slot->host->lock); in dw_mci_req_show()
119 mrq = slot->mrq; in dw_mci_req_show()
122 cmd = mrq->cmd; in dw_mci_req_show()
123 data = mrq->data; in dw_mci_req_show()
124 stop = mrq->stop; in dw_mci_req_show()
129 cmd->opcode, cmd->arg, cmd->flags, in dw_mci_req_show()
130 cmd->resp[0], cmd->resp[1], cmd->resp[2], in dw_mci_req_show()
131 cmd->resp[2], cmd->error); in dw_mci_req_show()
134 data->bytes_xfered, data->blocks, in dw_mci_req_show()
135 data->blksz, data->flags, data->error); in dw_mci_req_show()
139 stop->opcode, stop->arg, stop->flags, in dw_mci_req_show()
140 stop->resp[0], stop->resp[1], stop->resp[2], in dw_mci_req_show()
141 stop->resp[2], stop->error); in dw_mci_req_show()
144 spin_unlock_bh(&slot->host->lock); in dw_mci_req_show()
152 struct dw_mci *host = s->private; in dw_mci_regs_show()
154 pm_runtime_get_sync(host->dev); in dw_mci_regs_show()
163 pm_runtime_put_autosuspend(host->dev); in dw_mci_regs_show()
171 struct mmc_host *mmc = slot->mmc; in dw_mci_init_debugfs()
172 struct dw_mci *host = slot->host; in dw_mci_init_debugfs()
175 root = mmc->debugfs_root; in dw_mci_init_debugfs()
181 debugfs_create_u32("state", S_IRUSR, root, &host->state); in dw_mci_init_debugfs()
183 &host->pending_events); in dw_mci_init_debugfs()
185 &host->completed_events); in dw_mci_init_debugfs()
187 fault_create_debugfs_attr("fail_data_crc", root, &host->fail_data_crc); in dw_mci_init_debugfs()
201 if (readl_poll_timeout_atomic(host->regs + SDMMC_CTRL, ctrl, in dw_mci_ctrl_reset()
204 dev_err(host->dev, in dw_mci_ctrl_reset()
227 if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS, in dw_mci_wait_while_busy()
231 dev_err(host->dev, "Busy; trying anyway\n"); in dw_mci_wait_while_busy()
237 struct dw_mci *host = slot->host; in mci_send_cmd()
245 if (readl_poll_timeout_atomic(host->regs + SDMMC_CMD, cmd_status, in mci_send_cmd()
248 dev_err(&slot->mmc->class_dev, in mci_send_cmd()
256 struct dw_mci *host = slot->host; in dw_mci_prepare_command()
259 cmd->error = -EINPROGRESS; in dw_mci_prepare_command()
260 cmdr = cmd->opcode; in dw_mci_prepare_command()
262 if (cmd->opcode == MMC_STOP_TRANSMISSION || in dw_mci_prepare_command()
263 cmd->opcode == MMC_GO_IDLE_STATE || in dw_mci_prepare_command()
264 cmd->opcode == MMC_GO_INACTIVE_STATE || in dw_mci_prepare_command()
265 (cmd->opcode == SD_IO_RW_DIRECT && in dw_mci_prepare_command()
266 ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT)) in dw_mci_prepare_command()
268 else if (cmd->opcode != MMC_SEND_STATUS && cmd->data) in dw_mci_prepare_command()
271 if (cmd->opcode == SD_SWITCH_VOLTAGE) { in dw_mci_prepare_command()
278 WARN_ON(slot->host->state != STATE_SENDING_CMD); in dw_mci_prepare_command()
279 slot->host->state = STATE_SENDING_CMD11; in dw_mci_prepare_command()
289 * ever called with a non-zero clock. That shouldn't happen in dw_mci_prepare_command()
293 clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id); in dw_mci_prepare_command()
299 if (cmd->flags & MMC_RSP_PRESENT) { in dw_mci_prepare_command()
302 if (cmd->flags & MMC_RSP_136) in dw_mci_prepare_command()
306 if (cmd->flags & MMC_RSP_CRC) in dw_mci_prepare_command()
309 if (cmd->data) { in dw_mci_prepare_command()
311 if (cmd->data->flags & MMC_DATA_WRITE) in dw_mci_prepare_command()
315 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &slot->flags)) in dw_mci_prepare_command()
326 if (!cmd->data) in dw_mci_prep_stop_abort()
329 stop = &host->stop_abort; in dw_mci_prep_stop_abort()
330 cmdr = cmd->opcode; in dw_mci_prep_stop_abort()
339 stop->opcode = MMC_STOP_TRANSMISSION; in dw_mci_prep_stop_abort()
340 stop->arg = 0; in dw_mci_prep_stop_abort()
341 stop->flags = MMC_RSP_R1B | MMC_CMD_AC; in dw_mci_prep_stop_abort()
343 stop->opcode = SD_IO_RW_DIRECT; in dw_mci_prep_stop_abort()
344 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) | in dw_mci_prep_stop_abort()
345 ((cmd->arg >> 28) & 0x7); in dw_mci_prep_stop_abort()
346 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC; in dw_mci_prep_stop_abort()
351 cmdr = stop->opcode | SDMMC_CMD_STOP | in dw_mci_prep_stop_abort()
354 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &host->slot->flags)) in dw_mci_prep_stop_abort()
373 host->bus_hz); in dw_mci_set_cto()
391 spin_lock_irqsave(&host->irq_lock, irqflags); in dw_mci_set_cto()
392 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) in dw_mci_set_cto()
393 mod_timer(&host->cto_timer, in dw_mci_set_cto()
395 spin_unlock_irqrestore(&host->irq_lock, irqflags); in dw_mci_set_cto()
401 host->cmd = cmd; in dw_mci_start_command()
402 dev_vdbg(host->dev, in dw_mci_start_command()
404 cmd->arg, cmd_flags); in dw_mci_start_command()
406 mci_writel(host, CMDARG, cmd->arg); in dw_mci_start_command()
419 struct mmc_command *stop = &host->stop_abort; in send_stop_abort()
421 dw_mci_start_command(host, stop, host->stop_cmdr); in send_stop_abort()
427 if (host->using_dma) { in dw_mci_stop_dma()
428 host->dma_ops->stop(host); in dw_mci_stop_dma()
429 host->dma_ops->cleanup(host); in dw_mci_stop_dma()
433 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); in dw_mci_stop_dma()
438 struct mmc_data *data = host->data; in dw_mci_dma_cleanup()
440 if (data && data->host_cookie == COOKIE_MAPPED) { in dw_mci_dma_cleanup()
441 dma_unmap_sg(host->dev, in dw_mci_dma_cleanup()
442 data->sg, in dw_mci_dma_cleanup()
443 data->sg_len, in dw_mci_dma_cleanup()
445 data->host_cookie = COOKIE_UNMAPPED; in dw_mci_dma_cleanup()
477 struct mmc_data *data = host->data; in dw_mci_dmac_complete_dma()
479 dev_vdbg(host->dev, "DMA complete\n"); in dw_mci_dmac_complete_dma()
481 if ((host->use_dma == TRANS_MODE_EDMAC) && in dw_mci_dmac_complete_dma()
482 data && (data->flags & MMC_DATA_READ)) in dw_mci_dmac_complete_dma()
484 dma_sync_sg_for_cpu(mmc_dev(host->slot->mmc), in dw_mci_dmac_complete_dma()
485 data->sg, in dw_mci_dmac_complete_dma()
486 data->sg_len, in dw_mci_dmac_complete_dma()
489 host->dma_ops->cleanup(host); in dw_mci_dmac_complete_dma()
496 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); in dw_mci_dmac_complete_dma()
497 tasklet_schedule(&host->tasklet); in dw_mci_dmac_complete_dma()
505 if (host->dma_64bit_address == 1) { in dw_mci_idmac_init()
508 host->ring_size = in dw_mci_idmac_init()
512 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; in dw_mci_idmac_init()
514 p->des6 = (host->sg_dma + in dw_mci_idmac_init()
518 p->des7 = (u64)(host->sg_dma + in dw_mci_idmac_init()
522 p->des0 = 0; in dw_mci_idmac_init()
523 p->des1 = 0; in dw_mci_idmac_init()
524 p->des2 = 0; in dw_mci_idmac_init()
525 p->des3 = 0; in dw_mci_idmac_init()
528 /* Set the last descriptor as the end-of-ring descriptor */ in dw_mci_idmac_init()
529 p->des6 = host->sg_dma & 0xffffffff; in dw_mci_idmac_init()
530 p->des7 = (u64)host->sg_dma >> 32; in dw_mci_idmac_init()
531 p->des0 = IDMAC_DES0_ER; in dw_mci_idmac_init()
536 host->ring_size = in dw_mci_idmac_init()
540 for (i = 0, p = host->sg_cpu; in dw_mci_idmac_init()
541 i < host->ring_size - 1; in dw_mci_idmac_init()
543 p->des3 = cpu_to_le32(host->sg_dma + in dw_mci_idmac_init()
545 p->des0 = 0; in dw_mci_idmac_init()
546 p->des1 = 0; in dw_mci_idmac_init()
549 /* Set the last descriptor as the end-of-ring descriptor */ in dw_mci_idmac_init()
550 p->des3 = cpu_to_le32(host->sg_dma); in dw_mci_idmac_init()
551 p->des0 = cpu_to_le32(IDMAC_DES0_ER); in dw_mci_idmac_init()
556 if (host->dma_64bit_address == 1) { in dw_mci_idmac_init()
557 /* Mask out interrupts - get Tx & Rx complete only */ in dw_mci_idmac_init()
563 mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff); in dw_mci_idmac_init()
564 mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32); in dw_mci_idmac_init()
567 /* Mask out interrupts - get Tx & Rx complete only */ in dw_mci_idmac_init()
573 mci_writel(host, DBADDR, host->sg_dma); in dw_mci_idmac_init()
588 desc_first = desc_last = desc = host->sg_cpu; in dw_mci_prepare_desc64()
591 unsigned int length = sg_dma_len(&data->sg[i]); in dw_mci_prepare_desc64()
593 u64 mem_addr = sg_dma_address(&data->sg[i]); in dw_mci_prepare_desc64()
599 length -= desc_len; in dw_mci_prepare_desc64()
607 if (readl_poll_timeout_atomic(&desc->des0, val, in dw_mci_prepare_desc64()
616 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | in dw_mci_prepare_desc64()
623 desc->des4 = mem_addr & 0xffffffff; in dw_mci_prepare_desc64()
624 desc->des5 = mem_addr >> 32; in dw_mci_prepare_desc64()
635 desc_first->des0 |= IDMAC_DES0_FD; in dw_mci_prepare_desc64()
638 desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC); in dw_mci_prepare_desc64()
639 desc_last->des0 |= IDMAC_DES0_LD; in dw_mci_prepare_desc64()
644 dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n"); in dw_mci_prepare_desc64()
645 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ); in dw_mci_prepare_desc64()
647 return -EINVAL; in dw_mci_prepare_desc64()
660 desc_first = desc_last = desc = host->sg_cpu; in dw_mci_prepare_desc32()
663 unsigned int length = sg_dma_len(&data->sg[i]); in dw_mci_prepare_desc32()
665 u32 mem_addr = sg_dma_address(&data->sg[i]); in dw_mci_prepare_desc32()
671 length -= desc_len; in dw_mci_prepare_desc32()
679 if (readl_poll_timeout_atomic(&desc->des0, val, in dw_mci_prepare_desc32()
689 desc->des0 = cpu_to_le32(IDMAC_DES0_OWN | in dw_mci_prepare_desc32()
697 desc->des2 = cpu_to_le32(mem_addr); in dw_mci_prepare_desc32()
708 desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD); in dw_mci_prepare_desc32()
711 desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH | in dw_mci_prepare_desc32()
713 desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD); in dw_mci_prepare_desc32()
718 dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n"); in dw_mci_prepare_desc32()
719 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ); in dw_mci_prepare_desc32()
721 return -EINVAL; in dw_mci_prepare_desc32()
729 if (host->dma_64bit_address == 1) in dw_mci_idmac_start_dma()
730 ret = dw_mci_prepare_desc64(host, host->data, sg_len); in dw_mci_idmac_start_dma()
732 ret = dw_mci_prepare_desc32(host, host->data, sg_len); in dw_mci_idmac_start_dma()
774 dmaengine_terminate_async(host->dms->ch); in dw_mci_edmac_stop_dma()
782 struct scatterlist *sgl = host->data->sg; in dw_mci_edmac_start_dma()
784 u32 sg_elems = host->data->sg_len; in dw_mci_edmac_start_dma()
786 u32 fifo_offset = host->fifo_reg - host->regs; in dw_mci_edmac_start_dma()
791 cfg.dst_addr = host->phy_regs + fifo_offset; in dw_mci_edmac_start_dma()
801 if (host->data->flags & MMC_DATA_WRITE) in dw_mci_edmac_start_dma()
806 ret = dmaengine_slave_config(host->dms->ch, &cfg); in dw_mci_edmac_start_dma()
808 dev_err(host->dev, "Failed to config edmac.\n"); in dw_mci_edmac_start_dma()
809 return -EBUSY; in dw_mci_edmac_start_dma()
812 desc = dmaengine_prep_slave_sg(host->dms->ch, sgl, in dw_mci_edmac_start_dma()
816 dev_err(host->dev, "Can't prepare slave sg.\n"); in dw_mci_edmac_start_dma()
817 return -EBUSY; in dw_mci_edmac_start_dma()
821 desc->callback = dw_mci_dmac_complete_dma; in dw_mci_edmac_start_dma()
822 desc->callback_param = (void *)host; in dw_mci_edmac_start_dma()
826 if (host->data->flags & MMC_DATA_WRITE) in dw_mci_edmac_start_dma()
827 dma_sync_sg_for_device(mmc_dev(host->slot->mmc), sgl, in dw_mci_edmac_start_dma()
830 dma_async_issue_pending(host->dms->ch); in dw_mci_edmac_start_dma()
838 host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL); in dw_mci_edmac_init()
839 if (!host->dms) in dw_mci_edmac_init()
840 return -ENOMEM; in dw_mci_edmac_init()
842 host->dms->ch = dma_request_chan(host->dev, "rx-tx"); in dw_mci_edmac_init()
843 if (IS_ERR(host->dms->ch)) { in dw_mci_edmac_init()
844 int ret = PTR_ERR(host->dms->ch); in dw_mci_edmac_init()
846 dev_err(host->dev, "Failed to get external DMA channel.\n"); in dw_mci_edmac_init()
847 kfree(host->dms); in dw_mci_edmac_init()
848 host->dms = NULL; in dw_mci_edmac_init()
857 if (host->dms) { in dw_mci_edmac_exit()
858 if (host->dms->ch) { in dw_mci_edmac_exit()
859 dma_release_channel(host->dms->ch); in dw_mci_edmac_exit()
860 host->dms->ch = NULL; in dw_mci_edmac_exit()
862 kfree(host->dms); in dw_mci_edmac_exit()
863 host->dms = NULL; in dw_mci_edmac_exit()
883 if (data->host_cookie == COOKIE_PRE_MAPPED) in dw_mci_pre_dma_transfer()
884 return data->sg_len; in dw_mci_pre_dma_transfer()
888 * non-word-aligned buffers or lengths. Also, we don't bother in dw_mci_pre_dma_transfer()
891 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD) in dw_mci_pre_dma_transfer()
892 return -EINVAL; in dw_mci_pre_dma_transfer()
894 if (data->blksz & 3) in dw_mci_pre_dma_transfer()
895 return -EINVAL; in dw_mci_pre_dma_transfer()
897 for_each_sg(data->sg, sg, data->sg_len, i) { in dw_mci_pre_dma_transfer()
898 if (sg->offset & 3 || sg->length & 3) in dw_mci_pre_dma_transfer()
899 return -EINVAL; in dw_mci_pre_dma_transfer()
902 sg_len = dma_map_sg(host->dev, in dw_mci_pre_dma_transfer()
903 data->sg, in dw_mci_pre_dma_transfer()
904 data->sg_len, in dw_mci_pre_dma_transfer()
907 return -EINVAL; in dw_mci_pre_dma_transfer()
909 data->host_cookie = cookie; in dw_mci_pre_dma_transfer()
918 struct mmc_data *data = mrq->data; in dw_mci_pre_req()
920 if (!slot->host->use_dma || !data) in dw_mci_pre_req()
924 data->host_cookie = COOKIE_UNMAPPED; in dw_mci_pre_req()
926 if (dw_mci_pre_dma_transfer(slot->host, mrq->data, in dw_mci_pre_req()
928 data->host_cookie = COOKIE_UNMAPPED; in dw_mci_pre_req()
936 struct mmc_data *data = mrq->data; in dw_mci_post_req()
938 if (!slot->host->use_dma || !data) in dw_mci_post_req()
941 if (data->host_cookie != COOKIE_UNMAPPED) in dw_mci_post_req()
942 dma_unmap_sg(slot->host->dev, in dw_mci_post_req()
943 data->sg, in dw_mci_post_req()
944 data->sg_len, in dw_mci_post_req()
946 data->host_cookie = COOKIE_UNMAPPED; in dw_mci_post_req()
953 struct dw_mci *host = slot->host; in dw_mci_get_cd()
957 if (((mmc->caps & MMC_CAP_NEEDS_POLL) in dw_mci_get_cd()
961 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) { in dw_mci_get_cd()
962 if (mmc->caps & MMC_CAP_NEEDS_POLL) { in dw_mci_get_cd()
963 dev_info(&mmc->class_dev, in dw_mci_get_cd()
966 dev_info(&mmc->class_dev, in dw_mci_get_cd()
967 "card is non-removable.\n"); in dw_mci_get_cd()
969 set_bit(DW_MMC_CARD_PRESENT, &slot->flags); in dw_mci_get_cd()
976 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id)) in dw_mci_get_cd()
979 spin_lock_bh(&host->lock); in dw_mci_get_cd()
980 if (present && !test_and_set_bit(DW_MMC_CARD_PRESENT, &slot->flags)) in dw_mci_get_cd()
981 dev_dbg(&mmc->class_dev, "card is present\n"); in dw_mci_get_cd()
983 !test_and_clear_bit(DW_MMC_CARD_PRESENT, &slot->flags)) in dw_mci_get_cd()
984 dev_dbg(&mmc->class_dev, "card is not present\n"); in dw_mci_get_cd()
985 spin_unlock_bh(&host->lock); in dw_mci_get_cd()
992 unsigned int blksz = data->blksz; in dw_mci_adjust_fifoth()
994 u32 fifo_width = 1 << host->data_shift; in dw_mci_adjust_fifoth()
997 int idx = ARRAY_SIZE(mszs) - 1; in dw_mci_adjust_fifoth()
1000 if (!host->use_dma) in dw_mci_adjust_fifoth()
1003 tx_wmark = (host->fifo_depth) / 2; in dw_mci_adjust_fifoth()
1004 tx_wmark_invers = host->fifo_depth - tx_wmark; in dw_mci_adjust_fifoth()
1008 * if blksz is not a multiple of the FIFO width in dw_mci_adjust_fifoth()
1017 rx_wmark = mszs[idx] - 1; in dw_mci_adjust_fifoth()
1020 } while (--idx > 0); in dw_mci_adjust_fifoth()
1032 unsigned int blksz = data->blksz; in dw_mci_ctrl_thld()
1039 * in the FIFO region, so we really shouldn't access it). in dw_mci_ctrl_thld()
1041 if (host->verid < DW_MMC_240A || in dw_mci_ctrl_thld()
1042 (host->verid < DW_MMC_280A && data->flags & MMC_DATA_WRITE)) in dw_mci_ctrl_thld()
1049 if (data->flags & MMC_DATA_WRITE && in dw_mci_ctrl_thld()
1050 host->timing != MMC_TIMING_MMC_HS400) in dw_mci_ctrl_thld()
1053 if (data->flags & MMC_DATA_WRITE) in dw_mci_ctrl_thld()
1058 if (host->timing != MMC_TIMING_MMC_HS200 && in dw_mci_ctrl_thld()
1059 host->timing != MMC_TIMING_UHS_SDR104 && in dw_mci_ctrl_thld()
1060 host->timing != MMC_TIMING_MMC_HS400) in dw_mci_ctrl_thld()
1063 blksz_depth = blksz / (1 << host->data_shift); in dw_mci_ctrl_thld()
1064 fifo_depth = host->fifo_depth; in dw_mci_ctrl_thld()
1088 host->using_dma = 0; in dw_mci_submit_data_dma()
1091 if (!host->use_dma) in dw_mci_submit_data_dma()
1092 return -ENODEV; in dw_mci_submit_data_dma()
1096 host->dma_ops->stop(host); in dw_mci_submit_data_dma()
1100 host->using_dma = 1; in dw_mci_submit_data_dma()
1102 if (host->use_dma == TRANS_MODE_IDMAC) in dw_mci_submit_data_dma()
1103 dev_vdbg(host->dev, in dw_mci_submit_data_dma()
1105 (unsigned long)host->sg_cpu, in dw_mci_submit_data_dma()
1106 (unsigned long)host->sg_dma, in dw_mci_submit_data_dma()
1110 * Decide the MSIZE and RX/TX Watermark. in dw_mci_submit_data_dma()
1114 if (host->prev_blksz != data->blksz) in dw_mci_submit_data_dma()
1123 spin_lock_irqsave(&host->irq_lock, irqflags); in dw_mci_submit_data_dma()
1127 spin_unlock_irqrestore(&host->irq_lock, irqflags); in dw_mci_submit_data_dma()
1129 if (host->dma_ops->start(host, sg_len)) { in dw_mci_submit_data_dma()
1130 host->dma_ops->stop(host); in dw_mci_submit_data_dma()
1132 dev_dbg(host->dev, in dw_mci_submit_data_dma()
1135 return -ENODEV; in dw_mci_submit_data_dma()
1147 data->error = -EINPROGRESS; in dw_mci_submit_data()
1149 WARN_ON(host->data); in dw_mci_submit_data()
1150 host->sg = NULL; in dw_mci_submit_data()
1151 host->data = data; in dw_mci_submit_data()
1153 if (data->flags & MMC_DATA_READ) in dw_mci_submit_data()
1154 host->dir_status = DW_MCI_RECV_STATUS; in dw_mci_submit_data()
1156 host->dir_status = DW_MCI_SEND_STATUS; in dw_mci_submit_data()
1161 if (host->data->flags & MMC_DATA_READ) in dw_mci_submit_data()
1166 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); in dw_mci_submit_data()
1167 host->sg = data->sg; in dw_mci_submit_data()
1168 host->part_buf_start = 0; in dw_mci_submit_data()
1169 host->part_buf_count = 0; in dw_mci_submit_data()
1173 spin_lock_irqsave(&host->irq_lock, irqflags); in dw_mci_submit_data()
1177 spin_unlock_irqrestore(&host->irq_lock, irqflags); in dw_mci_submit_data()
1185 * is set, we set watermark same as data size. in dw_mci_submit_data()
1189 if (host->wm_aligned) in dw_mci_submit_data()
1192 mci_writel(host, FIFOTH, host->fifoth_val); in dw_mci_submit_data()
1193 host->prev_blksz = 0; in dw_mci_submit_data()
1200 host->prev_blksz = data->blksz; in dw_mci_submit_data()
1206 struct dw_mci *host = slot->host; in dw_mci_setup_bus()
1207 unsigned int clock = slot->clock; in dw_mci_setup_bus()
1213 if (host->state == STATE_WAITING_CMD11_DONE) in dw_mci_setup_bus()
1216 slot->mmc->actual_clock = 0; in dw_mci_setup_bus()
1221 } else if (clock != host->current_speed || force_clkinit) { in dw_mci_setup_bus()
1222 div = host->bus_hz / clock; in dw_mci_setup_bus()
1223 if (host->bus_hz % clock && host->bus_hz > clock) in dw_mci_setup_bus()
1226 * over-clocking the card. in dw_mci_setup_bus()
1230 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0; in dw_mci_setup_bus()
1232 if ((clock != slot->__clk_old && in dw_mci_setup_bus()
1233 !test_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags)) || in dw_mci_setup_bus()
1237 dev_info(&slot->mmc->class_dev, in dw_mci_setup_bus()
1239 slot->id, host->bus_hz, clock, in dw_mci_setup_bus()
1240 div ? ((host->bus_hz / div) >> 1) : in dw_mci_setup_bus()
1241 host->bus_hz, div); in dw_mci_setup_bus()
1247 if (slot->mmc->caps & MMC_CAP_NEEDS_POLL && in dw_mci_setup_bus()
1248 slot->mmc->f_min == clock) in dw_mci_setup_bus()
1249 set_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags); in dw_mci_setup_bus()
1266 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id; in dw_mci_setup_bus()
1267 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags)) in dw_mci_setup_bus()
1268 clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id; in dw_mci_setup_bus()
1275 slot->__clk_old = clock; in dw_mci_setup_bus()
1276 slot->mmc->actual_clock = div ? ((host->bus_hz / div) >> 1) : in dw_mci_setup_bus()
1277 host->bus_hz; in dw_mci_setup_bus()
1280 host->current_speed = clock; in dw_mci_setup_bus()
1283 mci_writel(host, CTYPE, (slot->ctype << slot->id)); in dw_mci_setup_bus()
1294 mrq = slot->mrq; in __dw_mci_start_request()
1296 host->mrq = mrq; in __dw_mci_start_request()
1298 host->pending_events = 0; in __dw_mci_start_request()
1299 host->completed_events = 0; in __dw_mci_start_request()
1300 host->cmd_status = 0; in __dw_mci_start_request()
1301 host->data_status = 0; in __dw_mci_start_request()
1302 host->dir_status = 0; in __dw_mci_start_request()
1304 data = cmd->data; in __dw_mci_start_request()
1307 mci_writel(host, BYTCNT, data->blksz*data->blocks); in __dw_mci_start_request()
1308 mci_writel(host, BLKSIZ, data->blksz); in __dw_mci_start_request()
1311 cmdflags = dw_mci_prepare_command(slot->mmc, cmd); in __dw_mci_start_request()
1314 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags)) in __dw_mci_start_request()
1324 if (cmd->opcode == SD_SWITCH_VOLTAGE) { in __dw_mci_start_request()
1337 spin_lock_irqsave(&host->irq_lock, irqflags); in __dw_mci_start_request()
1338 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) in __dw_mci_start_request()
1339 mod_timer(&host->cmd11_timer, in __dw_mci_start_request()
1341 spin_unlock_irqrestore(&host->irq_lock, irqflags); in __dw_mci_start_request()
1344 host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd); in __dw_mci_start_request()
1350 struct mmc_request *mrq = slot->mrq; in dw_mci_start_request()
1353 cmd = mrq->sbc ? mrq->sbc : mrq->cmd; in dw_mci_start_request()
1357 /* must be called with host->lock held */
1361 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n", in dw_mci_queue_request()
1362 host->state); in dw_mci_queue_request()
1364 slot->mrq = mrq; in dw_mci_queue_request()
1366 if (host->state == STATE_WAITING_CMD11_DONE) { in dw_mci_queue_request()
1367 dev_warn(&slot->mmc->class_dev, in dw_mci_queue_request()
1374 host->state = STATE_IDLE; in dw_mci_queue_request()
1377 if (host->state == STATE_IDLE) { in dw_mci_queue_request()
1378 host->state = STATE_SENDING_CMD; in dw_mci_queue_request()
1381 list_add_tail(&slot->queue_node, &host->queue); in dw_mci_queue_request()
1388 struct dw_mci *host = slot->host; in dw_mci_request()
1390 WARN_ON(slot->mrq); in dw_mci_request()
1399 mrq->cmd->error = -ENOMEDIUM; in dw_mci_request()
1404 spin_lock_bh(&host->lock); in dw_mci_request()
1408 spin_unlock_bh(&host->lock); in dw_mci_request()
1414 const struct dw_mci_drv_data *drv_data = slot->host->drv_data; in dw_mci_set_ios()
1418 switch (ios->bus_width) { in dw_mci_set_ios()
1420 slot->ctype = SDMMC_CTYPE_4BIT; in dw_mci_set_ios()
1423 slot->ctype = SDMMC_CTYPE_8BIT; in dw_mci_set_ios()
1427 slot->ctype = SDMMC_CTYPE_1BIT; in dw_mci_set_ios()
1430 regs = mci_readl(slot->host, UHS_REG); in dw_mci_set_ios()
1433 if (ios->timing == MMC_TIMING_MMC_DDR52 || in dw_mci_set_ios()
1434 ios->timing == MMC_TIMING_UHS_DDR50 || in dw_mci_set_ios()
1435 ios->timing == MMC_TIMING_MMC_HS400) in dw_mci_set_ios()
1436 regs |= ((0x1 << slot->id) << 16); in dw_mci_set_ios()
1438 regs &= ~((0x1 << slot->id) << 16); in dw_mci_set_ios()
1440 mci_writel(slot->host, UHS_REG, regs); in dw_mci_set_ios()
1441 slot->host->timing = ios->timing; in dw_mci_set_ios()
1444 * Use mirror of ios->clock to prevent race with mmc in dw_mci_set_ios()
1447 slot->clock = ios->clock; in dw_mci_set_ios()
1449 if (drv_data && drv_data->set_ios) in dw_mci_set_ios()
1450 drv_data->set_ios(slot->host, ios); in dw_mci_set_ios()
1452 switch (ios->power_mode) { in dw_mci_set_ios()
1454 if (!IS_ERR(mmc->supply.vmmc)) { in dw_mci_set_ios()
1455 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, in dw_mci_set_ios()
1456 ios->vdd); in dw_mci_set_ios()
1458 dev_err(slot->host->dev, in dw_mci_set_ios()
1464 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags); in dw_mci_set_ios()
1465 regs = mci_readl(slot->host, PWREN); in dw_mci_set_ios()
1466 regs |= (1 << slot->id); in dw_mci_set_ios()
1467 mci_writel(slot->host, PWREN, regs); in dw_mci_set_ios()
1470 if (!slot->host->vqmmc_enabled) { in dw_mci_set_ios()
1471 if (!IS_ERR(mmc->supply.vqmmc)) { in dw_mci_set_ios()
1472 ret = regulator_enable(mmc->supply.vqmmc); in dw_mci_set_ios()
1474 dev_err(slot->host->dev, in dw_mci_set_ios()
1477 slot->host->vqmmc_enabled = true; in dw_mci_set_ios()
1481 slot->host->vqmmc_enabled = true; in dw_mci_set_ios()
1485 dw_mci_ctrl_reset(slot->host, in dw_mci_set_ios()
1497 if (!IS_ERR(mmc->supply.vmmc)) in dw_mci_set_ios()
1498 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); in dw_mci_set_ios()
1500 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled) in dw_mci_set_ios()
1501 regulator_disable(mmc->supply.vqmmc); in dw_mci_set_ios()
1502 slot->host->vqmmc_enabled = false; in dw_mci_set_ios()
1504 regs = mci_readl(slot->host, PWREN); in dw_mci_set_ios()
1505 regs &= ~(1 << slot->id); in dw_mci_set_ios()
1506 mci_writel(slot->host, PWREN, regs); in dw_mci_set_ios()
1512 if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0) in dw_mci_set_ios()
1513 slot->host->state = STATE_IDLE; in dw_mci_set_ios()
1525 status = mci_readl(slot->host, STATUS); in dw_mci_card_busy()
1533 struct dw_mci *host = slot->host; in dw_mci_switch_voltage()
1534 const struct dw_mci_drv_data *drv_data = host->drv_data; in dw_mci_switch_voltage()
1536 u32 v18 = SDMMC_UHS_18V << slot->id; in dw_mci_switch_voltage()
1539 if (drv_data && drv_data->switch_voltage) in dw_mci_switch_voltage()
1540 return drv_data->switch_voltage(mmc, ios); in dw_mci_switch_voltage()
1548 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) in dw_mci_switch_voltage()
1553 if (!IS_ERR(mmc->supply.vqmmc)) { in dw_mci_switch_voltage()
1556 dev_dbg(&mmc->class_dev, in dw_mci_switch_voltage()
1557 "Regulator set error %d - %s V\n", in dw_mci_switch_voltage()
1578 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0; in dw_mci_get_ro()
1580 dev_dbg(&mmc->class_dev, "card is %s\n", in dw_mci_get_ro()
1581 read_only ? "read-only" : "read-write"); in dw_mci_get_ro()
1589 struct dw_mci *host = slot->host; in dw_mci_hw_reset()
1592 if (host->use_dma == TRANS_MODE_IDMAC) in dw_mci_hw_reset()
1606 reset &= ~(SDMMC_RST_HWACTIVE << slot->id); in dw_mci_hw_reset()
1609 reset |= SDMMC_RST_HWACTIVE << slot->id; in dw_mci_hw_reset()
1617 struct dw_mci *host = slot->host; in dw_mci_init_card()
1624 if (mmc->caps & MMC_CAP_SDIO_IRQ) { in dw_mci_init_card()
1625 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id; in dw_mci_init_card()
1631 if (card->type == MMC_TYPE_SDIO || in dw_mci_init_card()
1632 card->type == MMC_TYPE_SD_COMBO) { in dw_mci_init_card()
1633 set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags); in dw_mci_init_card()
1636 clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags); in dw_mci_init_card()
1650 struct dw_mci *host = slot->host; in __dw_mci_enable_sdio_irq()
1654 spin_lock_irqsave(&host->irq_lock, irqflags); in __dw_mci_enable_sdio_irq()
1659 int_mask |= SDMMC_INT_SDIO(slot->sdio_id); in __dw_mci_enable_sdio_irq()
1661 int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id); in __dw_mci_enable_sdio_irq()
1664 spin_unlock_irqrestore(&host->irq_lock, irqflags); in __dw_mci_enable_sdio_irq()
1670 struct dw_mci *host = slot->host; in dw_mci_enable_sdio_irq()
1676 pm_runtime_get_noresume(host->dev); in dw_mci_enable_sdio_irq()
1678 pm_runtime_put_noidle(host->dev); in dw_mci_enable_sdio_irq()
1691 struct dw_mci *host = slot->host; in dw_mci_execute_tuning()
1692 const struct dw_mci_drv_data *drv_data = host->drv_data; in dw_mci_execute_tuning()
1693 int err = -EINVAL; in dw_mci_execute_tuning()
1695 if (drv_data && drv_data->execute_tuning) in dw_mci_execute_tuning()
1696 err = drv_data->execute_tuning(slot, opcode); in dw_mci_execute_tuning()
1704 struct dw_mci *host = slot->host; in dw_mci_prepare_hs400_tuning()
1705 const struct dw_mci_drv_data *drv_data = host->drv_data; in dw_mci_prepare_hs400_tuning()
1707 if (drv_data && drv_data->prepare_hs400_tuning) in dw_mci_prepare_hs400_tuning()
1708 return drv_data->prepare_hs400_tuning(host, ios); in dw_mci_prepare_hs400_tuning()
1721 * the scatter-gather pointer to NULL. in dw_mci_reset()
1723 if (host->sg) { in dw_mci_reset()
1724 sg_miter_stop(&host->sg_miter); in dw_mci_reset()
1725 host->sg = NULL; in dw_mci_reset()
1728 if (host->use_dma) in dw_mci_reset()
1738 if (!host->use_dma) { in dw_mci_reset()
1744 if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS, in dw_mci_reset()
1748 dev_err(host->dev, in dw_mci_reset()
1754 /* when using DMA next we reset the fifo again */ in dw_mci_reset()
1760 dev_err(host->dev, in dw_mci_reset()
1761 "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n", in dw_mci_reset()
1767 if (host->use_dma == TRANS_MODE_IDMAC) in dw_mci_reset()
1775 mci_send_cmd(host->slot, SDMMC_CMD_UPD_CLK, 0); in dw_mci_reset()
1803 spin_lock_irqsave(&host->irq_lock, flags); in dw_mci_fault_timer()
1809 if (!host->data_status) { in dw_mci_fault_timer()
1810 host->data_status = SDMMC_INT_DCRC; in dw_mci_fault_timer()
1811 set_bit(EVENT_DATA_ERROR, &host->pending_events); in dw_mci_fault_timer()
1812 tasklet_schedule(&host->tasklet); in dw_mci_fault_timer()
1815 spin_unlock_irqrestore(&host->irq_lock, flags); in dw_mci_fault_timer()
1822 struct mmc_data *data = host->data; in dw_mci_start_fault_timer()
1824 if (!data || data->blocks <= 1) in dw_mci_start_fault_timer()
1827 if (!should_fail(&host->fail_data_crc, 1)) in dw_mci_start_fault_timer()
1833 hrtimer_start(&host->fault_timer, in dw_mci_start_fault_timer()
1840 hrtimer_cancel(&host->fault_timer); in dw_mci_stop_fault_timer()
1845 host->fail_data_crc = (struct fault_attr) FAULT_ATTR_INITIALIZER; in dw_mci_init_fault()
1847 hrtimer_init(&host->fault_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); in dw_mci_init_fault()
1848 host->fault_timer.function = dw_mci_fault_timer; in dw_mci_init_fault()
1865 __releases(&host->lock) in dw_mci_request_end()
1866 __acquires(&host->lock) in dw_mci_request_end()
1869 struct mmc_host *prev_mmc = host->slot->mmc; in dw_mci_request_end()
1871 WARN_ON(host->cmd || host->data); in dw_mci_request_end()
1873 host->slot->mrq = NULL; in dw_mci_request_end()
1874 host->mrq = NULL; in dw_mci_request_end()
1875 if (!list_empty(&host->queue)) { in dw_mci_request_end()
1876 slot = list_entry(host->queue.next, in dw_mci_request_end()
1878 list_del(&slot->queue_node); in dw_mci_request_end()
1879 dev_vdbg(host->dev, "list not empty: %s is next\n", in dw_mci_request_end()
1880 mmc_hostname(slot->mmc)); in dw_mci_request_end()
1881 host->state = STATE_SENDING_CMD; in dw_mci_request_end()
1884 dev_vdbg(host->dev, "list empty\n"); in dw_mci_request_end()
1886 if (host->state == STATE_SENDING_CMD11) in dw_mci_request_end()
1887 host->state = STATE_WAITING_CMD11_DONE; in dw_mci_request_end()
1889 host->state = STATE_IDLE; in dw_mci_request_end()
1892 spin_unlock(&host->lock); in dw_mci_request_end()
1894 spin_lock(&host->lock); in dw_mci_request_end()
1899 u32 status = host->cmd_status; in dw_mci_command_complete()
1901 host->cmd_status = 0; in dw_mci_command_complete()
1904 if (cmd->flags & MMC_RSP_PRESENT) { in dw_mci_command_complete()
1905 if (cmd->flags & MMC_RSP_136) { in dw_mci_command_complete()
1906 cmd->resp[3] = mci_readl(host, RESP0); in dw_mci_command_complete()
1907 cmd->resp[2] = mci_readl(host, RESP1); in dw_mci_command_complete()
1908 cmd->resp[1] = mci_readl(host, RESP2); in dw_mci_command_complete()
1909 cmd->resp[0] = mci_readl(host, RESP3); in dw_mci_command_complete()
1911 cmd->resp[0] = mci_readl(host, RESP0); in dw_mci_command_complete()
1912 cmd->resp[1] = 0; in dw_mci_command_complete()
1913 cmd->resp[2] = 0; in dw_mci_command_complete()
1914 cmd->resp[3] = 0; in dw_mci_command_complete()
1919 cmd->error = -ETIMEDOUT; in dw_mci_command_complete()
1920 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC)) in dw_mci_command_complete()
1921 cmd->error = -EILSEQ; in dw_mci_command_complete()
1923 cmd->error = -EIO; in dw_mci_command_complete()
1925 cmd->error = 0; in dw_mci_command_complete()
1927 return cmd->error; in dw_mci_command_complete()
1932 u32 status = host->data_status; in dw_mci_data_complete()
1936 data->error = -ETIMEDOUT; in dw_mci_data_complete()
1938 data->error = -EILSEQ; in dw_mci_data_complete()
1940 if (host->dir_status == in dw_mci_data_complete()
1947 data->bytes_xfered = 0; in dw_mci_data_complete()
1948 data->error = -ETIMEDOUT; in dw_mci_data_complete()
1949 } else if (host->dir_status == in dw_mci_data_complete()
1951 data->error = -EILSEQ; in dw_mci_data_complete()
1955 data->error = -EILSEQ; in dw_mci_data_complete()
1958 dev_dbg(host->dev, "data error, status 0x%08x\n", status); in dw_mci_data_complete()
1962 * in the FIFO in dw_mci_data_complete()
1966 data->bytes_xfered = data->blocks * data->blksz; in dw_mci_data_complete()
1967 data->error = 0; in dw_mci_data_complete()
1970 return data->error; in dw_mci_data_complete()
1986 host->bus_hz); in dw_mci_set_drto()
1991 spin_lock_irqsave(&host->irq_lock, irqflags); in dw_mci_set_drto()
1992 if (!test_bit(EVENT_DATA_COMPLETE, &host->pending_events)) in dw_mci_set_drto()
1993 mod_timer(&host->dto_timer, in dw_mci_set_drto()
1995 spin_unlock_irqrestore(&host->irq_lock, irqflags); in dw_mci_set_drto()
2000 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) in dw_mci_clear_pending_cmd_complete()
2010 WARN_ON(del_timer_sync(&host->cto_timer)); in dw_mci_clear_pending_cmd_complete()
2011 clear_bit(EVENT_CMD_COMPLETE, &host->pending_events); in dw_mci_clear_pending_cmd_complete()
2018 if (!test_bit(EVENT_DATA_COMPLETE, &host->pending_events)) in dw_mci_clear_pending_data_complete()
2022 WARN_ON(del_timer_sync(&host->dto_timer)); in dw_mci_clear_pending_data_complete()
2023 clear_bit(EVENT_DATA_COMPLETE, &host->pending_events); in dw_mci_clear_pending_data_complete()
2038 spin_lock(&host->lock); in dw_mci_tasklet_func()
2040 state = host->state; in dw_mci_tasklet_func()
2041 data = host->data; in dw_mci_tasklet_func()
2042 mrq = host->mrq; in dw_mci_tasklet_func()
2057 cmd = host->cmd; in dw_mci_tasklet_func()
2058 host->cmd = NULL; in dw_mci_tasklet_func()
2059 set_bit(EVENT_CMD_COMPLETE, &host->completed_events); in dw_mci_tasklet_func()
2061 if (cmd == mrq->sbc && !err) { in dw_mci_tasklet_func()
2062 __dw_mci_start_request(host, host->slot, in dw_mci_tasklet_func()
2063 mrq->cmd); in dw_mci_tasklet_func()
2067 if (cmd->data && err) { in dw_mci_tasklet_func()
2089 if (err != -ETIMEDOUT) { in dw_mci_tasklet_func()
2100 if (!cmd->data || err) { in dw_mci_tasklet_func()
2118 &host->pending_events)) { in dw_mci_tasklet_func()
2119 if (!(host->data_status & (SDMMC_INT_DRTO | in dw_mci_tasklet_func()
2128 &host->pending_events)) { in dw_mci_tasklet_func()
2130 * If all data-related interrupts don't come in dw_mci_tasklet_func()
2133 if (host->dir_status == DW_MCI_RECV_STATUS) in dw_mci_tasklet_func()
2138 set_bit(EVENT_XFER_COMPLETE, &host->completed_events); in dw_mci_tasklet_func()
2154 &host->pending_events)) { in dw_mci_tasklet_func()
2155 if (!(host->data_status & (SDMMC_INT_DRTO | in dw_mci_tasklet_func()
2173 if (host->dir_status == DW_MCI_RECV_STATUS) in dw_mci_tasklet_func()
2179 host->data = NULL; in dw_mci_tasklet_func()
2180 set_bit(EVENT_DATA_COMPLETE, &host->completed_events); in dw_mci_tasklet_func()
2184 if (!data->stop || mrq->sbc) { in dw_mci_tasklet_func()
2185 if (mrq->sbc && data->stop) in dw_mci_tasklet_func()
2186 data->stop->error = 0; in dw_mci_tasklet_func()
2191 /* stop command for open-ended transfer*/ in dw_mci_tasklet_func()
2192 if (data->stop) in dw_mci_tasklet_func()
2205 &host->pending_events)) { in dw_mci_tasklet_func()
2206 host->cmd = NULL; in dw_mci_tasklet_func()
2213 * If err has non-zero, in dw_mci_tasklet_func()
2214 * stop-abort command has been already issued. in dw_mci_tasklet_func()
2225 if (mrq->cmd->error && mrq->data) in dw_mci_tasklet_func()
2229 host->cmd = NULL; in dw_mci_tasklet_func()
2230 host->data = NULL; in dw_mci_tasklet_func()
2232 if (!mrq->sbc && mrq->stop) in dw_mci_tasklet_func()
2233 dw_mci_command_complete(host, mrq->stop); in dw_mci_tasklet_func()
2235 host->cmd_status = 0; in dw_mci_tasklet_func()
2242 &host->pending_events)) in dw_mci_tasklet_func()
2250 host->state = state; in dw_mci_tasklet_func()
2252 spin_unlock(&host->lock); in dw_mci_tasklet_func()
2259 memcpy((void *)&host->part_buf, buf, cnt); in dw_mci_set_part_bytes()
2260 host->part_buf_count = cnt; in dw_mci_set_part_bytes()
2266 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count); in dw_mci_push_part_bytes()
2267 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt); in dw_mci_push_part_bytes()
2268 host->part_buf_count += cnt; in dw_mci_push_part_bytes()
2275 cnt = min_t(int, cnt, host->part_buf_count); in dw_mci_pull_part_bytes()
2277 memcpy(buf, (void *)&host->part_buf + host->part_buf_start, in dw_mci_pull_part_bytes()
2279 host->part_buf_count -= cnt; in dw_mci_pull_part_bytes()
2280 host->part_buf_start += cnt; in dw_mci_pull_part_bytes()
2288 memcpy(buf, &host->part_buf, cnt); in dw_mci_pull_final_bytes()
2289 host->part_buf_start = cnt; in dw_mci_pull_final_bytes()
2290 host->part_buf_count = (1 << host->data_shift) - cnt; in dw_mci_pull_final_bytes()
2295 struct mmc_data *data = host->data; in dw_mci_push_data16()
2299 if (unlikely(host->part_buf_count)) { in dw_mci_push_data16()
2303 cnt -= len; in dw_mci_push_data16()
2304 if (host->part_buf_count == 2) { in dw_mci_push_data16()
2305 mci_fifo_writew(host->fifo_reg, host->part_buf16); in dw_mci_push_data16()
2306 host->part_buf_count = 0; in dw_mci_push_data16()
2313 int len = min(cnt & -2, (int)sizeof(aligned_buf)); in dw_mci_push_data16()
2316 /* memcpy from input buffer into aligned buffer */ in dw_mci_push_data16()
2319 cnt -= len; in dw_mci_push_data16()
2320 /* push data from aligned buffer into fifo */ in dw_mci_push_data16()
2322 mci_fifo_writew(host->fifo_reg, aligned_buf[i]); in dw_mci_push_data16()
2329 for (; cnt >= 2; cnt -= 2) in dw_mci_push_data16()
2330 mci_fifo_writew(host->fifo_reg, *pdata++); in dw_mci_push_data16()
2337 if ((data->bytes_xfered + init_cnt) == in dw_mci_push_data16()
2338 (data->blksz * data->blocks)) in dw_mci_push_data16()
2339 mci_fifo_writew(host->fifo_reg, host->part_buf16); in dw_mci_push_data16()
2348 /* pull data from fifo into aligned buffer */ in dw_mci_pull_data16()
2350 int len = min(cnt & -2, (int)sizeof(aligned_buf)); in dw_mci_pull_data16()
2355 aligned_buf[i] = mci_fifo_readw(host->fifo_reg); in dw_mci_pull_data16()
2356 /* memcpy from aligned buffer into output buffer */ in dw_mci_pull_data16()
2359 cnt -= len; in dw_mci_pull_data16()
2366 for (; cnt >= 2; cnt -= 2) in dw_mci_pull_data16()
2367 *pdata++ = mci_fifo_readw(host->fifo_reg); in dw_mci_pull_data16()
2371 host->part_buf16 = mci_fifo_readw(host->fifo_reg); in dw_mci_pull_data16()
2378 struct mmc_data *data = host->data; in dw_mci_push_data32()
2382 if (unlikely(host->part_buf_count)) { in dw_mci_push_data32()
2386 cnt -= len; in dw_mci_push_data32()
2387 if (host->part_buf_count == 4) { in dw_mci_push_data32()
2388 mci_fifo_writel(host->fifo_reg, host->part_buf32); in dw_mci_push_data32()
2389 host->part_buf_count = 0; in dw_mci_push_data32()
2396 int len = min(cnt & -4, (int)sizeof(aligned_buf)); in dw_mci_push_data32()
2399 /* memcpy from input buffer into aligned buffer */ in dw_mci_push_data32()
2402 cnt -= len; in dw_mci_push_data32()
2403 /* push data from aligned buffer into fifo */ in dw_mci_push_data32()
2405 mci_fifo_writel(host->fifo_reg, aligned_buf[i]); in dw_mci_push_data32()
2412 for (; cnt >= 4; cnt -= 4) in dw_mci_push_data32()
2413 mci_fifo_writel(host->fifo_reg, *pdata++); in dw_mci_push_data32()
2420 if ((data->bytes_xfered + init_cnt) == in dw_mci_push_data32()
2421 (data->blksz * data->blocks)) in dw_mci_push_data32()
2422 mci_fifo_writel(host->fifo_reg, host->part_buf32); in dw_mci_push_data32()
2431 /* pull data from fifo into aligned buffer */ in dw_mci_pull_data32()
2433 int len = min(cnt & -4, (int)sizeof(aligned_buf)); in dw_mci_pull_data32()
2438 aligned_buf[i] = mci_fifo_readl(host->fifo_reg); in dw_mci_pull_data32()
2439 /* memcpy from aligned buffer into output buffer */ in dw_mci_pull_data32()
2442 cnt -= len; in dw_mci_pull_data32()
2449 for (; cnt >= 4; cnt -= 4) in dw_mci_pull_data32()
2450 *pdata++ = mci_fifo_readl(host->fifo_reg); in dw_mci_pull_data32()
2454 host->part_buf32 = mci_fifo_readl(host->fifo_reg); in dw_mci_pull_data32()
2461 struct mmc_data *data = host->data; in dw_mci_push_data64()
2465 if (unlikely(host->part_buf_count)) { in dw_mci_push_data64()
2469 cnt -= len; in dw_mci_push_data64()
2471 if (host->part_buf_count == 8) { in dw_mci_push_data64()
2472 mci_fifo_writeq(host->fifo_reg, host->part_buf); in dw_mci_push_data64()
2473 host->part_buf_count = 0; in dw_mci_push_data64()
2480 int len = min(cnt & -8, (int)sizeof(aligned_buf)); in dw_mci_push_data64()
2483 /* memcpy from input buffer into aligned buffer */ in dw_mci_push_data64()
2486 cnt -= len; in dw_mci_push_data64()
2487 /* push data from aligned buffer into fifo */ in dw_mci_push_data64()
2489 mci_fifo_writeq(host->fifo_reg, aligned_buf[i]); in dw_mci_push_data64()
2496 for (; cnt >= 8; cnt -= 8) in dw_mci_push_data64()
2497 mci_fifo_writeq(host->fifo_reg, *pdata++); in dw_mci_push_data64()
2504 if ((data->bytes_xfered + init_cnt) == in dw_mci_push_data64()
2505 (data->blksz * data->blocks)) in dw_mci_push_data64()
2506 mci_fifo_writeq(host->fifo_reg, host->part_buf); in dw_mci_push_data64()
2515 /* pull data from fifo into aligned buffer */ in dw_mci_pull_data64()
2517 int len = min(cnt & -8, (int)sizeof(aligned_buf)); in dw_mci_pull_data64()
2522 aligned_buf[i] = mci_fifo_readq(host->fifo_reg); in dw_mci_pull_data64()
2524 /* memcpy from aligned buffer into output buffer */ in dw_mci_pull_data64()
2527 cnt -= len; in dw_mci_pull_data64()
2534 for (; cnt >= 8; cnt -= 8) in dw_mci_pull_data64()
2535 *pdata++ = mci_fifo_readq(host->fifo_reg); in dw_mci_pull_data64()
2539 host->part_buf = mci_fifo_readq(host->fifo_reg); in dw_mci_pull_data64()
2553 cnt -= len; in dw_mci_pull_data()
2556 host->pull_data(host, buf, cnt); in dw_mci_pull_data()
2561 struct sg_mapping_iter *sg_miter = &host->sg_miter; in dw_mci_read_data_pio()
2564 struct mmc_data *data = host->data; in dw_mci_read_data_pio()
2565 int shift = host->data_shift; in dw_mci_read_data_pio()
2574 host->sg = sg_miter->piter.sg; in dw_mci_read_data_pio()
2575 buf = sg_miter->addr; in dw_mci_read_data_pio()
2576 remain = sg_miter->length; in dw_mci_read_data_pio()
2581 << shift) + host->part_buf_count; in dw_mci_read_data_pio()
2586 data->bytes_xfered += len; in dw_mci_read_data_pio()
2588 remain -= len; in dw_mci_read_data_pio()
2591 sg_miter->consumed = offset; in dw_mci_read_data_pio()
2601 sg_miter->consumed = 0; in dw_mci_read_data_pio()
2608 host->sg = NULL; in dw_mci_read_data_pio()
2610 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); in dw_mci_read_data_pio()
2615 struct sg_mapping_iter *sg_miter = &host->sg_miter; in dw_mci_write_data_pio()
2618 struct mmc_data *data = host->data; in dw_mci_write_data_pio()
2619 int shift = host->data_shift; in dw_mci_write_data_pio()
2622 unsigned int fifo_depth = host->fifo_depth; in dw_mci_write_data_pio()
2629 host->sg = sg_miter->piter.sg; in dw_mci_write_data_pio()
2630 buf = sg_miter->addr; in dw_mci_write_data_pio()
2631 remain = sg_miter->length; in dw_mci_write_data_pio()
2635 fcnt = ((fifo_depth - in dw_mci_write_data_pio()
2637 << shift) - host->part_buf_count; in dw_mci_write_data_pio()
2641 host->push_data(host, (void *)(buf + offset), len); in dw_mci_write_data_pio()
2642 data->bytes_xfered += len; in dw_mci_write_data_pio()
2644 remain -= len; in dw_mci_write_data_pio()
2647 sg_miter->consumed = offset; in dw_mci_write_data_pio()
2655 sg_miter->consumed = 0; in dw_mci_write_data_pio()
2662 host->sg = NULL; in dw_mci_write_data_pio()
2664 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); in dw_mci_write_data_pio()
2669 del_timer(&host->cto_timer); in dw_mci_cmd_interrupt()
2671 if (!host->cmd_status) in dw_mci_cmd_interrupt()
2672 host->cmd_status = status; in dw_mci_cmd_interrupt()
2676 set_bit(EVENT_CMD_COMPLETE, &host->pending_events); in dw_mci_cmd_interrupt()
2677 tasklet_schedule(&host->tasklet); in dw_mci_cmd_interrupt()
2684 struct dw_mci_slot *slot = host->slot; in dw_mci_handle_cd()
2686 mmc_detect_change(slot->mmc, in dw_mci_handle_cd()
2687 msecs_to_jiffies(host->pdata->detect_delay_ms)); in dw_mci_handle_cd()
2694 struct dw_mci_slot *slot = host->slot; in dw_mci_interrupt()
2696 pending = mci_readl(host, MINTSTS); /* read-only mask reg */ in dw_mci_interrupt()
2700 if ((host->state == STATE_SENDING_CMD11) && in dw_mci_interrupt()
2709 spin_lock(&host->irq_lock); in dw_mci_interrupt()
2711 spin_unlock(&host->irq_lock); in dw_mci_interrupt()
2713 del_timer(&host->cmd11_timer); in dw_mci_interrupt()
2717 spin_lock(&host->irq_lock); in dw_mci_interrupt()
2719 del_timer(&host->cto_timer); in dw_mci_interrupt()
2721 host->cmd_status = pending; in dw_mci_interrupt()
2723 set_bit(EVENT_CMD_COMPLETE, &host->pending_events); in dw_mci_interrupt()
2725 spin_unlock(&host->irq_lock); in dw_mci_interrupt()
2729 spin_lock(&host->irq_lock); in dw_mci_interrupt()
2733 host->data_status = pending; in dw_mci_interrupt()
2735 set_bit(EVENT_DATA_ERROR, &host->pending_events); in dw_mci_interrupt()
2736 tasklet_schedule(&host->tasklet); in dw_mci_interrupt()
2738 spin_unlock(&host->irq_lock); in dw_mci_interrupt()
2742 spin_lock(&host->irq_lock); in dw_mci_interrupt()
2744 del_timer(&host->dto_timer); in dw_mci_interrupt()
2747 if (!host->data_status) in dw_mci_interrupt()
2748 host->data_status = pending; in dw_mci_interrupt()
2750 if (host->dir_status == DW_MCI_RECV_STATUS) { in dw_mci_interrupt()
2751 if (host->sg != NULL) in dw_mci_interrupt()
2754 set_bit(EVENT_DATA_COMPLETE, &host->pending_events); in dw_mci_interrupt()
2755 tasklet_schedule(&host->tasklet); in dw_mci_interrupt()
2757 spin_unlock(&host->irq_lock); in dw_mci_interrupt()
2762 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg) in dw_mci_interrupt()
2768 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg) in dw_mci_interrupt()
2773 spin_lock(&host->irq_lock); in dw_mci_interrupt()
2778 spin_unlock(&host->irq_lock); in dw_mci_interrupt()
2786 if (pending & SDMMC_INT_SDIO(slot->sdio_id)) { in dw_mci_interrupt()
2788 SDMMC_INT_SDIO(slot->sdio_id)); in dw_mci_interrupt()
2790 sdio_signal_irq(slot->mmc); in dw_mci_interrupt()
2795 if (host->use_dma != TRANS_MODE_IDMAC) in dw_mci_interrupt()
2799 if (host->dma_64bit_address == 1) { in dw_mci_interrupt()
2805 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events)) in dw_mci_interrupt()
2806 host->dma_ops->complete((void *)host); in dw_mci_interrupt()
2814 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events)) in dw_mci_interrupt()
2815 host->dma_ops->complete((void *)host); in dw_mci_interrupt()
2824 struct dw_mci *host = slot->host; in dw_mci_init_slot_caps()
2825 const struct dw_mci_drv_data *drv_data = host->drv_data; in dw_mci_init_slot_caps()
2826 struct mmc_host *mmc = slot->mmc; in dw_mci_init_slot_caps()
2829 if (host->pdata->caps) in dw_mci_init_slot_caps()
2830 mmc->caps = host->pdata->caps; in dw_mci_init_slot_caps()
2832 if (host->pdata->pm_caps) in dw_mci_init_slot_caps()
2833 mmc->pm_caps = host->pdata->pm_caps; in dw_mci_init_slot_caps()
2835 if (host->dev->of_node) { in dw_mci_init_slot_caps()
2836 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc"); in dw_mci_init_slot_caps()
2840 ctrl_id = to_platform_device(host->dev)->id; in dw_mci_init_slot_caps()
2843 if (drv_data && drv_data->caps) { in dw_mci_init_slot_caps()
2844 if (ctrl_id >= drv_data->num_caps) { in dw_mci_init_slot_caps()
2845 dev_err(host->dev, "invalid controller id %d\n", in dw_mci_init_slot_caps()
2847 return -EINVAL; in dw_mci_init_slot_caps()
2849 mmc->caps |= drv_data->caps[ctrl_id]; in dw_mci_init_slot_caps()
2852 if (host->pdata->caps2) in dw_mci_init_slot_caps()
2853 mmc->caps2 = host->pdata->caps2; in dw_mci_init_slot_caps()
2855 mmc->f_min = DW_MCI_FREQ_MIN; in dw_mci_init_slot_caps()
2856 if (!mmc->f_max) in dw_mci_init_slot_caps()
2857 mmc->f_max = DW_MCI_FREQ_MAX; in dw_mci_init_slot_caps()
2860 if (mmc->caps & MMC_CAP_SDIO_IRQ) in dw_mci_init_slot_caps()
2861 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; in dw_mci_init_slot_caps()
2872 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev); in dw_mci_init_slot()
2874 return -ENOMEM; in dw_mci_init_slot()
2877 slot->id = 0; in dw_mci_init_slot()
2878 slot->sdio_id = host->sdio_id0 + slot->id; in dw_mci_init_slot()
2879 slot->mmc = mmc; in dw_mci_init_slot()
2880 slot->host = host; in dw_mci_init_slot()
2881 host->slot = slot; in dw_mci_init_slot()
2883 mmc->ops = &dw_mci_ops; in dw_mci_init_slot()
2890 if (!mmc->ocr_avail) in dw_mci_init_slot()
2891 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; in dw_mci_init_slot()
2902 if (host->use_dma == TRANS_MODE_IDMAC) { in dw_mci_init_slot()
2903 mmc->max_segs = host->ring_size; in dw_mci_init_slot()
2904 mmc->max_blk_size = 65535; in dw_mci_init_slot()
2905 mmc->max_seg_size = 0x1000; in dw_mci_init_slot()
2906 mmc->max_req_size = mmc->max_seg_size * host->ring_size; in dw_mci_init_slot()
2907 mmc->max_blk_count = mmc->max_req_size / 512; in dw_mci_init_slot()
2908 } else if (host->use_dma == TRANS_MODE_EDMAC) { in dw_mci_init_slot()
2909 mmc->max_segs = 64; in dw_mci_init_slot()
2910 mmc->max_blk_size = 65535; in dw_mci_init_slot()
2911 mmc->max_blk_count = 65535; in dw_mci_init_slot()
2912 mmc->max_req_size = in dw_mci_init_slot()
2913 mmc->max_blk_size * mmc->max_blk_count; in dw_mci_init_slot()
2914 mmc->max_seg_size = mmc->max_req_size; in dw_mci_init_slot()
2917 mmc->max_segs = 64; in dw_mci_init_slot()
2918 mmc->max_blk_size = 65535; /* BLKSIZ is 16 bits */ in dw_mci_init_slot()
2919 mmc->max_blk_count = 512; in dw_mci_init_slot()
2920 mmc->max_req_size = mmc->max_blk_size * in dw_mci_init_slot()
2921 mmc->max_blk_count; in dw_mci_init_slot()
2922 mmc->max_seg_size = mmc->max_req_size; in dw_mci_init_slot()
2945 mmc_remove_host(slot->mmc); in dw_mci_cleanup_slot()
2946 slot->host->slot = NULL; in dw_mci_cleanup_slot()
2947 mmc_free_host(slot->mmc); in dw_mci_cleanup_slot()
2953 struct device *dev = host->dev; in dw_mci_init_dma()
2958 * 2b'00: No DMA Interface -> Actually means using Internal DMA block in dw_mci_init_dma()
2959 * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block in dw_mci_init_dma()
2960 * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block in dw_mci_init_dma()
2961 * 2b'11: Non DW DMA Interface -> pio only in dw_mci_init_dma()
2966 host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON)); in dw_mci_init_dma()
2967 if (host->use_dma == DMA_INTERFACE_IDMA) { in dw_mci_init_dma()
2968 host->use_dma = TRANS_MODE_IDMAC; in dw_mci_init_dma()
2969 } else if (host->use_dma == DMA_INTERFACE_DWDMA || in dw_mci_init_dma()
2970 host->use_dma == DMA_INTERFACE_GDMA) { in dw_mci_init_dma()
2971 host->use_dma = TRANS_MODE_EDMAC; in dw_mci_init_dma()
2977 if (host->use_dma == TRANS_MODE_IDMAC) { in dw_mci_init_dma()
2985 /* host supports IDMAC in 64-bit address mode */ in dw_mci_init_dma()
2986 host->dma_64bit_address = 1; in dw_mci_init_dma()
2987 dev_info(host->dev, in dw_mci_init_dma()
2988 "IDMAC supports 64-bit address mode.\n"); in dw_mci_init_dma()
2989 if (!dma_set_mask(host->dev, DMA_BIT_MASK(64))) in dw_mci_init_dma()
2990 dma_set_coherent_mask(host->dev, in dw_mci_init_dma()
2993 /* host supports IDMAC in 32-bit address mode */ in dw_mci_init_dma()
2994 host->dma_64bit_address = 0; in dw_mci_init_dma()
2995 dev_info(host->dev, in dw_mci_init_dma()
2996 "IDMAC supports 32-bit address mode.\n"); in dw_mci_init_dma()
3000 host->sg_cpu = dmam_alloc_coherent(host->dev, in dw_mci_init_dma()
3002 &host->sg_dma, GFP_KERNEL); in dw_mci_init_dma()
3003 if (!host->sg_cpu) { in dw_mci_init_dma()
3004 dev_err(host->dev, in dw_mci_init_dma()
3010 host->dma_ops = &dw_mci_idmac_ops; in dw_mci_init_dma()
3011 dev_info(host->dev, "Using internal DMA controller.\n"); in dw_mci_init_dma()
3014 if ((device_property_read_string_array(dev, "dma-names", in dw_mci_init_dma()
3019 host->dma_ops = &dw_mci_edmac_ops; in dw_mci_init_dma()
3020 dev_info(host->dev, "Using external DMA controller.\n"); in dw_mci_init_dma()
3023 if (host->dma_ops->init && host->dma_ops->start && in dw_mci_init_dma()
3024 host->dma_ops->stop && host->dma_ops->cleanup) { in dw_mci_init_dma()
3025 if (host->dma_ops->init(host)) { in dw_mci_init_dma()
3026 dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n", in dw_mci_init_dma()
3031 dev_err(host->dev, "DMA initialization not found.\n"); in dw_mci_init_dma()
3038 dev_info(host->dev, "Using PIO mode.\n"); in dw_mci_init_dma()
3039 host->use_dma = TRANS_MODE_PIO; in dw_mci_init_dma()
3046 if (host->state != STATE_SENDING_CMD11) { in dw_mci_cmd11_timer()
3047 dev_warn(host->dev, "Unexpected CMD11 timeout\n"); in dw_mci_cmd11_timer()
3051 host->cmd_status = SDMMC_INT_RTO; in dw_mci_cmd11_timer()
3052 set_bit(EVENT_CMD_COMPLETE, &host->pending_events); in dw_mci_cmd11_timer()
3053 tasklet_schedule(&host->tasklet); in dw_mci_cmd11_timer()
3062 spin_lock_irqsave(&host->irq_lock, irqflags); in dw_mci_cto_timer()
3070 * pending command in the controller--we just assume it will never come. in dw_mci_cto_timer()
3072 pending = mci_readl(host, MINTSTS); /* read-only mask reg */ in dw_mci_cto_timer()
3075 dev_warn(host->dev, "Unexpected interrupt latency\n"); in dw_mci_cto_timer()
3078 if (test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) { in dw_mci_cto_timer()
3080 dev_warn(host->dev, "CTO timeout when already completed\n"); in dw_mci_cto_timer()
3088 switch (host->state) { in dw_mci_cto_timer()
3097 host->cmd_status = SDMMC_INT_RTO; in dw_mci_cto_timer()
3098 set_bit(EVENT_CMD_COMPLETE, &host->pending_events); in dw_mci_cto_timer()
3099 tasklet_schedule(&host->tasklet); in dw_mci_cto_timer()
3102 dev_warn(host->dev, "Unexpected command timeout, state %d\n", in dw_mci_cto_timer()
3103 host->state); in dw_mci_cto_timer()
3108 spin_unlock_irqrestore(&host->irq_lock, irqflags); in dw_mci_cto_timer()
3117 spin_lock_irqsave(&host->irq_lock, irqflags); in dw_mci_dto_timer()
3123 pending = mci_readl(host, MINTSTS); /* read-only mask reg */ in dw_mci_dto_timer()
3126 dev_warn(host->dev, "Unexpected data interrupt latency\n"); in dw_mci_dto_timer()
3129 if (test_bit(EVENT_DATA_COMPLETE, &host->pending_events)) { in dw_mci_dto_timer()
3131 dev_warn(host->dev, "DTO timeout when already completed\n"); in dw_mci_dto_timer()
3139 switch (host->state) { in dw_mci_dto_timer()
3147 host->data_status = SDMMC_INT_DRTO; in dw_mci_dto_timer()
3148 set_bit(EVENT_DATA_ERROR, &host->pending_events); in dw_mci_dto_timer()
3149 set_bit(EVENT_DATA_COMPLETE, &host->pending_events); in dw_mci_dto_timer()
3150 tasklet_schedule(&host->tasklet); in dw_mci_dto_timer()
3153 dev_warn(host->dev, "Unexpected data timeout, state %d\n", in dw_mci_dto_timer()
3154 host->state); in dw_mci_dto_timer()
3159 spin_unlock_irqrestore(&host->irq_lock, irqflags); in dw_mci_dto_timer()
3166 struct device *dev = host->dev; in dw_mci_parse_dt()
3167 const struct dw_mci_drv_data *drv_data = host->drv_data; in dw_mci_parse_dt()
3173 return ERR_PTR(-ENOMEM); in dw_mci_parse_dt()
3176 pdata->rstc = devm_reset_control_get_optional_exclusive(dev, "reset"); in dw_mci_parse_dt()
3177 if (IS_ERR(pdata->rstc)) in dw_mci_parse_dt()
3178 return ERR_CAST(pdata->rstc); in dw_mci_parse_dt()
3180 if (device_property_read_u32(dev, "fifo-depth", &pdata->fifo_depth)) in dw_mci_parse_dt()
3182 "fifo-depth property not found, using value of FIFOTH register as default\n"); in dw_mci_parse_dt()
3184 device_property_read_u32(dev, "card-detect-delay", in dw_mci_parse_dt()
3185 &pdata->detect_delay_ms); in dw_mci_parse_dt()
3187 device_property_read_u32(dev, "data-addr", &host->data_addr_override); in dw_mci_parse_dt()
3189 if (device_property_present(dev, "fifo-watermark-aligned")) in dw_mci_parse_dt()
3190 host->wm_aligned = true; in dw_mci_parse_dt()
3192 if (!device_property_read_u32(dev, "clock-frequency", &clock_frequency)) in dw_mci_parse_dt()
3193 pdata->bus_hz = clock_frequency; in dw_mci_parse_dt()
3195 if (drv_data && drv_data->parse_dt) { in dw_mci_parse_dt()
3196 ret = drv_data->parse_dt(host); in dw_mci_parse_dt()
3207 return ERR_PTR(-EINVAL); in dw_mci_parse_dt()
3217 * No need for CD if all slots have a non-error GPIO in dw_mci_enable_cd()
3220 if (host->slot->mmc->caps & MMC_CAP_NEEDS_POLL) in dw_mci_enable_cd()
3223 if (mmc_gpio_get_cd(host->slot->mmc) < 0) { in dw_mci_enable_cd()
3224 spin_lock_irqsave(&host->irq_lock, irqflags); in dw_mci_enable_cd()
3228 spin_unlock_irqrestore(&host->irq_lock, irqflags); in dw_mci_enable_cd()
3234 const struct dw_mci_drv_data *drv_data = host->drv_data; in dw_mci_probe()
3238 if (!host->pdata) { in dw_mci_probe()
3239 host->pdata = dw_mci_parse_dt(host); in dw_mci_probe()
3240 if (IS_ERR(host->pdata)) in dw_mci_probe()
3241 return dev_err_probe(host->dev, PTR_ERR(host->pdata), in dw_mci_probe()
3245 host->biu_clk = devm_clk_get(host->dev, "biu"); in dw_mci_probe()
3246 if (IS_ERR(host->biu_clk)) { in dw_mci_probe()
3247 dev_dbg(host->dev, "biu clock not available\n"); in dw_mci_probe()
3249 ret = clk_prepare_enable(host->biu_clk); in dw_mci_probe()
3251 dev_err(host->dev, "failed to enable biu clock\n"); in dw_mci_probe()
3256 host->ciu_clk = devm_clk_get(host->dev, "ciu"); in dw_mci_probe()
3257 if (IS_ERR(host->ciu_clk)) { in dw_mci_probe()
3258 dev_dbg(host->dev, "ciu clock not available\n"); in dw_mci_probe()
3259 host->bus_hz = host->pdata->bus_hz; in dw_mci_probe()
3261 ret = clk_prepare_enable(host->ciu_clk); in dw_mci_probe()
3263 dev_err(host->dev, "failed to enable ciu clock\n"); in dw_mci_probe()
3267 if (host->pdata->bus_hz) { in dw_mci_probe()
3268 ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz); in dw_mci_probe()
3270 dev_warn(host->dev, in dw_mci_probe()
3272 host->pdata->bus_hz); in dw_mci_probe()
3274 host->bus_hz = clk_get_rate(host->ciu_clk); in dw_mci_probe()
3277 if (!host->bus_hz) { in dw_mci_probe()
3278 dev_err(host->dev, in dw_mci_probe()
3280 ret = -ENODEV; in dw_mci_probe()
3284 if (host->pdata->rstc) { in dw_mci_probe()
3285 reset_control_assert(host->pdata->rstc); in dw_mci_probe()
3287 reset_control_deassert(host->pdata->rstc); in dw_mci_probe()
3290 if (drv_data && drv_data->init) { in dw_mci_probe()
3291 ret = drv_data->init(host); in dw_mci_probe()
3293 dev_err(host->dev, in dw_mci_probe()
3299 timer_setup(&host->cmd11_timer, dw_mci_cmd11_timer, 0); in dw_mci_probe()
3300 timer_setup(&host->cto_timer, dw_mci_cto_timer, 0); in dw_mci_probe()
3301 timer_setup(&host->dto_timer, dw_mci_dto_timer, 0); in dw_mci_probe()
3303 spin_lock_init(&host->lock); in dw_mci_probe()
3304 spin_lock_init(&host->irq_lock); in dw_mci_probe()
3305 INIT_LIST_HEAD(&host->queue); in dw_mci_probe()
3310 * Get the host data width - this assumes that HCON has been set with in dw_mci_probe()
3315 host->push_data = dw_mci_push_data16; in dw_mci_probe()
3316 host->pull_data = dw_mci_pull_data16; in dw_mci_probe()
3318 host->data_shift = 1; in dw_mci_probe()
3320 host->push_data = dw_mci_push_data64; in dw_mci_probe()
3321 host->pull_data = dw_mci_pull_data64; in dw_mci_probe()
3323 host->data_shift = 3; in dw_mci_probe()
3328 "Defaulting to 32-bit access.\n"); in dw_mci_probe()
3329 host->push_data = dw_mci_push_data32; in dw_mci_probe()
3330 host->pull_data = dw_mci_pull_data32; in dw_mci_probe()
3332 host->data_shift = 2; in dw_mci_probe()
3337 ret = -ENODEV; in dw_mci_probe()
3341 host->dma_ops = host->pdata->dma_ops; in dw_mci_probe()
3352 * FIFO threshold settings RxMark = fifo_size / 2 - 1, in dw_mci_probe()
3355 if (!host->pdata->fifo_depth) { in dw_mci_probe()
3357 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may in dw_mci_probe()
3365 fifo_size = host->pdata->fifo_depth; in dw_mci_probe()
3367 host->fifo_depth = fifo_size; in dw_mci_probe()
3368 host->fifoth_val = in dw_mci_probe()
3369 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2); in dw_mci_probe()
3370 mci_writel(host, FIFOTH, host->fifoth_val); in dw_mci_probe()
3378 * Need to check the version-id and set data-offset for DATA register. in dw_mci_probe()
3380 host->verid = SDMMC_GET_VERID(mci_readl(host, VERID)); in dw_mci_probe()
3381 dev_info(host->dev, "Version ID is %04x\n", host->verid); in dw_mci_probe()
3383 if (host->data_addr_override) in dw_mci_probe()
3384 host->fifo_reg = host->regs + host->data_addr_override; in dw_mci_probe()
3385 else if (host->verid < DW_MMC_240A) in dw_mci_probe()
3386 host->fifo_reg = host->regs + DATA_OFFSET; in dw_mci_probe()
3388 host->fifo_reg = host->regs + DATA_240A_OFFSET; in dw_mci_probe()
3390 tasklet_setup(&host->tasklet, dw_mci_tasklet_func); in dw_mci_probe()
3391 ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt, in dw_mci_probe()
3392 host->irq_flags, "dw-mci", host); in dw_mci_probe()
3406 dev_info(host->dev, in dw_mci_probe()
3407 "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n", in dw_mci_probe()
3408 host->irq, width, fifo_size); in dw_mci_probe()
3413 dev_dbg(host->dev, "slot %d init failed\n", i); in dw_mci_probe()
3423 if (host->use_dma && host->dma_ops->exit) in dw_mci_probe()
3424 host->dma_ops->exit(host); in dw_mci_probe()
3426 reset_control_assert(host->pdata->rstc); in dw_mci_probe()
3429 clk_disable_unprepare(host->ciu_clk); in dw_mci_probe()
3432 clk_disable_unprepare(host->biu_clk); in dw_mci_probe()
3440 dev_dbg(host->dev, "remove slot\n"); in dw_mci_remove()
3441 if (host->slot) in dw_mci_remove()
3442 dw_mci_cleanup_slot(host->slot); in dw_mci_remove()
3451 if (host->use_dma && host->dma_ops->exit) in dw_mci_remove()
3452 host->dma_ops->exit(host); in dw_mci_remove()
3454 reset_control_assert(host->pdata->rstc); in dw_mci_remove()
3456 clk_disable_unprepare(host->ciu_clk); in dw_mci_remove()
3457 clk_disable_unprepare(host->biu_clk); in dw_mci_remove()
3468 if (host->use_dma && host->dma_ops->exit) in dw_mci_runtime_suspend()
3469 host->dma_ops->exit(host); in dw_mci_runtime_suspend()
3471 clk_disable_unprepare(host->ciu_clk); in dw_mci_runtime_suspend()
3473 if (host->slot && in dw_mci_runtime_suspend()
3474 (mmc_can_gpio_cd(host->slot->mmc) || in dw_mci_runtime_suspend()
3475 !mmc_card_is_removable(host->slot->mmc))) in dw_mci_runtime_suspend()
3476 clk_disable_unprepare(host->biu_clk); in dw_mci_runtime_suspend()
3487 if (host->slot && in dw_mci_runtime_resume()
3488 (mmc_can_gpio_cd(host->slot->mmc) || in dw_mci_runtime_resume()
3489 !mmc_card_is_removable(host->slot->mmc))) { in dw_mci_runtime_resume()
3490 ret = clk_prepare_enable(host->biu_clk); in dw_mci_runtime_resume()
3495 ret = clk_prepare_enable(host->ciu_clk); in dw_mci_runtime_resume()
3500 clk_disable_unprepare(host->ciu_clk); in dw_mci_runtime_resume()
3501 ret = -ENODEV; in dw_mci_runtime_resume()
3505 if (host->use_dma && host->dma_ops->init) in dw_mci_runtime_resume()
3506 host->dma_ops->init(host); in dw_mci_runtime_resume()
3512 mci_writel(host, FIFOTH, host->fifoth_val); in dw_mci_runtime_resume()
3513 host->prev_blksz = 0; in dw_mci_runtime_resume()
3525 if (host->slot->mmc->pm_flags & MMC_PM_KEEP_POWER) in dw_mci_runtime_resume()
3526 dw_mci_set_ios(host->slot->mmc, &host->slot->mmc->ios); in dw_mci_runtime_resume()
3529 dw_mci_setup_bus(host->slot, true); in dw_mci_runtime_resume()
3531 /* Re-enable SDIO interrupts. */ in dw_mci_runtime_resume()
3532 if (sdio_irq_claimed(host->slot->mmc)) in dw_mci_runtime_resume()
3533 __dw_mci_enable_sdio_irq(host->slot, 1); in dw_mci_runtime_resume()
3541 if (host->slot && in dw_mci_runtime_resume()
3542 (mmc_can_gpio_cd(host->slot->mmc) || in dw_mci_runtime_resume()
3543 !mmc_card_is_removable(host->slot->mmc))) in dw_mci_runtime_resume()
3544 clk_disable_unprepare(host->biu_clk); in dw_mci_runtime_resume()