1 // SPDX-License-Identifier: GPL-2.0
17 #include "dw_mmc-pltfm.h"
34 	struct hi3798cv200_priv *priv = host->priv;  in dw_mci_hi3798cv200_set_ios()
38 	if (ios->timing == MMC_TIMING_MMC_DDR52 ||  in dw_mci_hi3798cv200_set_ios()
39 	    ios->timing == MMC_TIMING_UHS_DDR50)  in dw_mci_hi3798cv200_set_ios()
46 	if (ios->timing == MMC_TIMING_MMC_DDR52)  in dw_mci_hi3798cv200_set_ios()
53 	if (ios->timing == MMC_TIMING_MMC_HS400)  in dw_mci_hi3798cv200_set_ios()
59 	if (ios->timing == MMC_TIMING_MMC_HS ||  in dw_mci_hi3798cv200_set_ios()
60 	    ios->timing == MMC_TIMING_LEGACY)  in dw_mci_hi3798cv200_set_ios()
61 		clk_set_phase(priv->drive_clk, 180);  in dw_mci_hi3798cv200_set_ios()
62 	else if (ios->timing == MMC_TIMING_MMC_HS200)  in dw_mci_hi3798cv200_set_ios()
63 		clk_set_phase(priv->drive_clk, 135);  in dw_mci_hi3798cv200_set_ios()
70 	struct dw_mci *host = slot->host;  in dw_mci_hi3798cv200_execute_tuning()
71 	struct hi3798cv200_priv *priv = host->priv;  in dw_mci_hi3798cv200_execute_tuning()
72 	int raise_point = -1, fall_point = -1;  in dw_mci_hi3798cv200_execute_tuning()
73 	int err, prev_err = -1;  in dw_mci_hi3798cv200_execute_tuning()
78 		clk_set_phase(priv->sample_clk, degrees[i]);  in dw_mci_hi3798cv200_execute_tuning()
81 		err = mmc_send_tuning(slot->mmc, opcode, NULL);  in dw_mci_hi3798cv200_execute_tuning()
87 				fall_point = i - 1;  in dw_mci_hi3798cv200_execute_tuning()
92 		if (raise_point != -1 && fall_point != -1)  in dw_mci_hi3798cv200_execute_tuning()
101 		if (raise_point == -1)  in dw_mci_hi3798cv200_execute_tuning()
103 		if (fall_point == -1)  in dw_mci_hi3798cv200_execute_tuning()
104 			fall_point = ARRAY_SIZE(degrees) - 1;  in dw_mci_hi3798cv200_execute_tuning()
107 			    (ARRAY_SIZE(degrees) - 1))  in dw_mci_hi3798cv200_execute_tuning()
110 				i = (raise_point + ARRAY_SIZE(degrees) - 1) / 2;  in dw_mci_hi3798cv200_execute_tuning()
115 		clk_set_phase(priv->sample_clk, degrees[i]);  in dw_mci_hi3798cv200_execute_tuning()
116 		dev_dbg(host->dev, "Tuning clk_sample[%d, %d], set[%d]\n",  in dw_mci_hi3798cv200_execute_tuning()
119 		dev_err(host->dev, "No valid clk_sample shift! use default\n");  in dw_mci_hi3798cv200_execute_tuning()
120 		err = -EINVAL;  in dw_mci_hi3798cv200_execute_tuning()
132 	priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);  in dw_mci_hi3798cv200_init()
134 		return -ENOMEM;  in dw_mci_hi3798cv200_init()
136 	priv->sample_clk = devm_clk_get(host->dev, "ciu-sample");  in dw_mci_hi3798cv200_init()
137 	if (IS_ERR(priv->sample_clk)) {  in dw_mci_hi3798cv200_init()
138 		dev_err(host->dev, "failed to get ciu-sample clock\n");  in dw_mci_hi3798cv200_init()
139 		return PTR_ERR(priv->sample_clk);  in dw_mci_hi3798cv200_init()
142 	priv->drive_clk = devm_clk_get(host->dev, "ciu-drive");  in dw_mci_hi3798cv200_init()
143 	if (IS_ERR(priv->drive_clk)) {  in dw_mci_hi3798cv200_init()
144 		dev_err(host->dev, "failed to get ciu-drive clock\n");  in dw_mci_hi3798cv200_init()
145 		return PTR_ERR(priv->drive_clk);  in dw_mci_hi3798cv200_init()
148 	ret = clk_prepare_enable(priv->sample_clk);  in dw_mci_hi3798cv200_init()
150 		dev_err(host->dev, "failed to enable ciu-sample clock\n");  in dw_mci_hi3798cv200_init()
154 	ret = clk_prepare_enable(priv->drive_clk);  in dw_mci_hi3798cv200_init()
156 		dev_err(host->dev, "failed to enable ciu-drive clock\n");  in dw_mci_hi3798cv200_init()
160 	host->priv = priv;  in dw_mci_hi3798cv200_init()
164 	clk_disable_unprepare(priv->sample_clk);  in dw_mci_hi3798cv200_init()
184 	struct hi3798cv200_priv *priv = host->priv;  in dw_mci_hi3798cv200_remove()
186 	clk_disable_unprepare(priv->drive_clk);  in dw_mci_hi3798cv200_remove()
187 	clk_disable_unprepare(priv->sample_clk);  in dw_mci_hi3798cv200_remove()
193 	{ .compatible = "hisilicon,hi3798cv200-dw-mshc", },
209 MODULE_DESCRIPTION("HiSilicon Hi3798CV200 Specific DW-MSHC Driver Extension");