Lines Matching +full:read +full:- +full:only

1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3  * Copyright (c) 2003-2019, Intel Corporation. All rights reserved.
53 #define MEI_DEV_ID_LPT_W      0x8D3A  /* Lynx Point - Wellsburg */
129 /* H_CB_WW - Host Circular Buffer (CB) Write Window register */
131 /* H_CSR - Host Control Status register */
133 /* ME_CB_RW - ME Circular Buffer Read Window register (read only) */
135 /* ME_CSR_HA - ME Control Status Host Access register (read only) */
137 /* H_HGC_CSR - PGI register */
139 /* H_D0I3C - D0I3 Control  */
143 /* Host Circular Buffer Depth - maximum number of 32-bit entries in CB */
147 /* Host Circular Buffer Read Pointer */
169 /* ME CB (Circular Buffer) Depth HRA (Host Read Access) - host read only
172 /* ME CB Write Pointer HRA - host read only access to ME_CBWP */
174 /* ME CB Read Pointer HRA - host read only access to ME_CBRP */
176 /* ME Power Gate Isolation Capability HRA  - host ready only access */
178 /* ME Reset HRA - host read only access to ME_RST */
180 /* ME Ready HRA - host read only access to ME_RDY */
182 /* ME Interrupt Generate HRA - host read only access to ME_IG */
184 /* ME Interrupt Status HRA - host read only access to ME_IS */
186 /* ME Interrupt Enable HRA - host read only access to ME_IE */