311 void rtsx_pci_add_cmd(struct rtsx_pcr *pcr,  in rtsx_pci_add_cmd()  function
332 EXPORT_SYMBOL_GPL(rtsx_pci_add_cmd);
559 			rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);  in rtsx_pci_read_ppbuf()
573 			rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);  in rtsx_pci_read_ppbuf()
602 			rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,  in rtsx_pci_write_ppbuf()
616 			rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,  in rtsx_pci_write_ppbuf()
635 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,  in rtsx_pci_set_pull_ctl()
791 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,  in rtsx_pci_switch_clock()
793 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV,  in rtsx_pci_switch_clock()
795 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);  in rtsx_pci_switch_clock()
796 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2,  in rtsx_pci_switch_clock()
798 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n);  in rtsx_pci_switch_clock()
799 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);  in rtsx_pci_switch_clock()
801 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,  in rtsx_pci_switch_clock()
803 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,  in rtsx_pci_switch_clock()
1328 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, 0x07, 0x07);  in rtsx_pci_init_hw()
1330 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, HOST_SLEEP_STATE, 0x03, 0x00);  in rtsx_pci_init_hw()
1332 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, 0x1E, 0);  in rtsx_pci_init_hw()
1334 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x0A, 0);  in rtsx_pci_init_hw()
1336 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DRIVE_SEL,  in rtsx_pci_init_hw()
1339 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1,  in rtsx_pci_init_hw()
1342 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF,  in rtsx_pci_init_hw()
1345 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF,  in rtsx_pci_init_hw()
1348 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, 0x12);  in rtsx_pci_init_hw()
1351 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x16, 0x10);  in rtsx_pci_init_hw()
1353 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,  in rtsx_pci_init_hw()
1358 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PERST_GLITCH_WIDTH, 0xFF, 0x80);  in rtsx_pci_init_hw()
1363 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RCCTL, 0x01, 0x00);  in rtsx_pci_init_hw()
1369 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, NFTS_TX_CTRL, 0x02, 0);  in rtsx_pci_init_hw()