Lines Matching +full:0 +full:xff0000
44 { PCI_DEVICE(0x10EC, 0x5209), PCI_CLASS_OTHERS << 16, 0xFF0000 },
45 { PCI_DEVICE(0x10EC, 0x5229), PCI_CLASS_OTHERS << 16, 0xFF0000 },
46 { PCI_DEVICE(0x10EC, 0x5289), PCI_CLASS_OTHERS << 16, 0xFF0000 },
47 { PCI_DEVICE(0x10EC, 0x5227), PCI_CLASS_OTHERS << 16, 0xFF0000 },
48 { PCI_DEVICE(0x10EC, 0x522A), PCI_CLASS_OTHERS << 16, 0xFF0000 },
49 { PCI_DEVICE(0x10EC, 0x5249), PCI_CLASS_OTHERS << 16, 0xFF0000 },
50 { PCI_DEVICE(0x10EC, 0x5287), PCI_CLASS_OTHERS << 16, 0xFF0000 },
51 { PCI_DEVICE(0x10EC, 0x5286), PCI_CLASS_OTHERS << 16, 0xFF0000 },
52 { PCI_DEVICE(0x10EC, 0x524A), PCI_CLASS_OTHERS << 16, 0xFF0000 },
53 { PCI_DEVICE(0x10EC, 0x525A), PCI_CLASS_OTHERS << 16, 0xFF0000 },
54 { PCI_DEVICE(0x10EC, 0x5260), PCI_CLASS_OTHERS << 16, 0xFF0000 },
55 { PCI_DEVICE(0x10EC, 0x5261), PCI_CLASS_OTHERS << 16, 0xFF0000 },
56 { PCI_DEVICE(0x10EC, 0x5228), PCI_CLASS_OTHERS << 16, 0xFF0000 },
57 { 0, }
65 MASK_8_BIT_DEF, (u8) (latency & 0xFF)); in rtsx_comm_set_ltr_latency()
67 MASK_8_BIT_DEF, (u8)((latency >> 8) & 0xFF)); in rtsx_comm_set_ltr_latency()
69 MASK_8_BIT_DEF, (u8)((latency >> 16) & 0xFF)); in rtsx_comm_set_ltr_latency()
71 MASK_8_BIT_DEF, (u8)((latency >> 24) & 0xFF)); in rtsx_comm_set_ltr_latency()
75 return 0; in rtsx_comm_set_ltr_latency()
91 enable ? pcr->aspm_en : 0); in rtsx_comm_set_aspm()
93 if (pcr->aspm_en & 0x02) in rtsx_comm_set_aspm()
95 FORCE_ASPM_CTL1, enable ? 0 : FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1); in rtsx_comm_set_aspm()
101 if (!enable && (pcr->aspm_en & 0x02)) in rtsx_comm_set_aspm()
117 rtsx_pci_write_register(pcr, L1SUB_CONFIG3, 0xFF, val); in rtsx_set_l1off_sub()
119 return 0; in rtsx_set_l1off_sub()
177 val |= (u32)(addr & 0x3FFF) << 16; in rtsx_pci_write_register()
183 for (i = 0; i < MAX_RW_REG_CNT; i++) { in rtsx_pci_write_register()
185 if ((val & HAIMR_TRANS_END) == 0) { in rtsx_pci_write_register()
188 return 0; in rtsx_pci_write_register()
201 val |= (u32)(addr & 0x3FFF) << 16; in rtsx_pci_read_register()
204 for (i = 0; i < MAX_RW_REG_CNT; i++) { in rtsx_pci_read_register()
206 if ((val & HAIMR_TRANS_END) == 0) in rtsx_pci_read_register()
214 *data = (u8)(val & 0xFF); in rtsx_pci_read_register()
216 return 0; in rtsx_pci_read_register()
222 int err, i, finished = 0; in __rtsx_pci_write_phy_register()
225 rtsx_pci_write_register(pcr, PHYDATA0, 0xFF, (u8)val); in __rtsx_pci_write_phy_register()
226 rtsx_pci_write_register(pcr, PHYDATA1, 0xFF, (u8)(val >> 8)); in __rtsx_pci_write_phy_register()
227 rtsx_pci_write_register(pcr, PHYADDR, 0xFF, addr); in __rtsx_pci_write_phy_register()
228 rtsx_pci_write_register(pcr, PHYRWCTL, 0xFF, 0x81); in __rtsx_pci_write_phy_register()
230 for (i = 0; i < 100000; i++) { in __rtsx_pci_write_phy_register()
232 if (err < 0) in __rtsx_pci_write_phy_register()
235 if (!(tmp & 0x80)) { in __rtsx_pci_write_phy_register()
244 return 0; in __rtsx_pci_write_phy_register()
258 int err, i, finished = 0; in __rtsx_pci_read_phy_register()
262 rtsx_pci_write_register(pcr, PHYADDR, 0xFF, addr); in __rtsx_pci_read_phy_register()
263 rtsx_pci_write_register(pcr, PHYRWCTL, 0xFF, 0x80); in __rtsx_pci_read_phy_register()
265 for (i = 0; i < 100000; i++) { in __rtsx_pci_read_phy_register()
267 if (err < 0) in __rtsx_pci_read_phy_register()
270 if (!(tmp & 0x80)) { in __rtsx_pci_read_phy_register()
286 return 0; in __rtsx_pci_read_phy_register()
306 rtsx_pci_write_register(pcr, DMACTL, 0x80, 0x80); in rtsx_pci_stop_cmd()
307 rtsx_pci_write_register(pcr, RBCTL, 0x80, 0x80); in rtsx_pci_stop_cmd()
315 u32 val = 0; in rtsx_pci_add_cmd()
318 val |= (u32)(cmd_type & 0x03) << 30; in rtsx_pci_add_cmd()
319 val |= (u32)(reg_addr & 0x3FFF) << 16; in rtsx_pci_add_cmd()
340 val |= (u32)(pcr->ci * 4) & 0x00FFFFFF; in rtsx_pci_send_cmd_no_wait()
342 val |= 0x40000000; in rtsx_pci_send_cmd_no_wait()
353 int err = 0; in rtsx_pci_send_cmd()
364 val |= (u32)(pcr->ci * 4) & 0x00FFFFFF; in rtsx_pci_send_cmd()
366 val |= 0x40000000; in rtsx_pci_send_cmd()
374 if (timeleft <= 0) { in rtsx_pci_send_cmd()
384 err = 0; in rtsx_pci_send_cmd()
394 if ((err < 0) && (err != -ENODEV)) in rtsx_pci_send_cmd()
411 pcr_dbg(pcr, "DMA addr: 0x%x, Len: 0x%x\n", (unsigned int)addr, len); in rtsx_pci_add_sg_tbl()
417 if (len > 0xFFFF) in rtsx_pci_add_sg_tbl()
418 val = ((u64)addr << 32) | (((u64)len & 0xFFFF) << 16) in rtsx_pci_add_sg_tbl()
432 int err = 0, count; in rtsx_pci_transfer_data()
456 if ((sglist == NULL) || (num_sg <= 0)) in rtsx_pci_dma_map_sg()
481 int i, err = 0; in rtsx_pci_dma_transfer()
491 val = ((u32)(dir & 0x01) << 29) | TRIG_DMA | ADMA_MODE; in rtsx_pci_dma_transfer()
492 pcr->sgi = 0; in rtsx_pci_dma_transfer()
511 if (timeleft <= 0) { in rtsx_pci_dma_transfer()
533 if ((err < 0) && (err != -ENODEV)) in rtsx_pci_dma_transfer()
555 for (i = 0; i < buf_len / 256; i++) { in rtsx_pci_read_ppbuf()
558 for (j = 0; j < 256; j++) in rtsx_pci_read_ppbuf()
559 rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0); in rtsx_pci_read_ppbuf()
562 if (err < 0) in rtsx_pci_read_ppbuf()
572 for (j = 0; j < buf_len % 256; j++) in rtsx_pci_read_ppbuf()
573 rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0); in rtsx_pci_read_ppbuf()
576 if (err < 0) in rtsx_pci_read_ppbuf()
582 return 0; in rtsx_pci_read_ppbuf()
598 for (i = 0; i < buf_len / 256; i++) { in rtsx_pci_write_ppbuf()
601 for (j = 0; j < 256; j++) { in rtsx_pci_write_ppbuf()
603 reg++, 0xFF, *ptr); in rtsx_pci_write_ppbuf()
608 if (err < 0) in rtsx_pci_write_ppbuf()
615 for (j = 0; j < buf_len % 256; j++) { in rtsx_pci_write_ppbuf()
617 reg++, 0xFF, *ptr); in rtsx_pci_write_ppbuf()
622 if (err < 0) in rtsx_pci_write_ppbuf()
626 return 0; in rtsx_pci_write_ppbuf()
634 while (*tbl & 0xFFFF0000) { in rtsx_pci_set_pull_ctl()
636 (u16)(*tbl >> 16), 0xFF, (u8)(*tbl)); in rtsx_pci_set_pull_ctl()
686 pcr_dbg(pcr, "RTSX_BIER: 0x%08x\n", pcr->bier); in rtsx_pci_enable_bus_int()
735 if (err < 0) in rtsx_pci_switch_clock()
755 return 0; in rtsx_pci_switch_clock()
794 0xFF, (div << 4) | mcu_cnt); in rtsx_pci_switch_clock()
795 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0); in rtsx_pci_switch_clock()
798 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n); in rtsx_pci_switch_clock()
802 PHASE_NOT_RESET, 0); in rtsx_pci_switch_clock()
808 if (err < 0) in rtsx_pci_switch_clock()
813 err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0); in rtsx_pci_switch_clock()
814 if (err < 0) in rtsx_pci_switch_clock()
818 return 0; in rtsx_pci_switch_clock()
827 return 0; in rtsx_pci_card_power_on()
836 return 0; in rtsx_pci_card_power_off()
855 return 0; in rtsx_pci_card_exclusive_check()
864 return 0; in rtsx_pci_switch_output_voltage()
904 unsigned int card_detect = 0, card_inserted, card_removed; in rtsx_pci_card_detect()
916 pcr_dbg(pcr, "irq_status: 0x%08x\n", irq_status); in rtsx_pci_card_detect()
921 pcr->card_inserted = 0; in rtsx_pci_card_detect()
922 pcr->card_removed = 0; in rtsx_pci_card_detect()
927 pcr_dbg(pcr, "card_inserted: 0x%x, card_removed: 0x%x\n", in rtsx_pci_card_detect()
959 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0); in rtsx_pci_process_ocp()
961 pcr->ocp_stat = 0; in rtsx_pci_process_ocp()
971 return 0; in rtsx_pci_process_ocp_interrupt()
987 if ((int_reg & pcr->bier) == 0) { in rtsx_pci_isr()
991 if (int_reg == 0xFFFFFFFF) { in rtsx_pci_isr()
996 int_reg &= (pcr->bier | 0x7FFFFF); in rtsx_pci_isr()
1009 RTS5261_EXPRESS_LINK_FAIL_MASK, 0); in rtsx_pci_isr()
1013 pcr->dma_error_count = 0; in rtsx_pci_isr()
1051 pcr->msi_en ? 0 : IRQF_SHARED, in rtsx_pci_acquire_irq()
1062 return 0; in rtsx_pci_acquire_irq()
1087 rtsx_set_l1off_sub_cfg_d0(pcr, 0); in rtsx_comm_pm_power_saving()
1133 /* Set relink_time to 0 */ in rtsx_base_force_power_down()
1134 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, MASK_8_BIT_DEF, 0); in rtsx_base_force_power_down()
1135 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, MASK_8_BIT_DEF, 0); in rtsx_base_force_power_down()
1137 RELINK_TIME_MASK, 0); in rtsx_base_force_power_down()
1150 rtsx_pci_writel(pcr, RTSX_BIER, 0); in rtsx_pci_power_off()
1151 pcr->bier = 0; in rtsx_pci_power_off()
1153 rtsx_pci_write_register(pcr, PETXCFG, 0x08, 0x08); in rtsx_pci_power_off()
1154 rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, pm_state); in rtsx_pci_power_off()
1169 rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN, 0); in rtsx_pci_enable_ocp()
1170 rtsx_pci_write_register(pcr, REG_OCPCTL, 0xFF, val); in rtsx_pci_enable_ocp()
1182 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0); in rtsx_pci_disable_ocp()
1198 rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN, 0); in rtsx_pci_init_ocp()
1228 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0); in rtsx_pci_clear_ocpstat()
1237 rtsx_pci_read_phy_register(pcr, 0x01, &val); in rtsx_pci_enable_oobs_polling()
1239 rtsx_pci_write_phy_register(pcr, 0x01, val); in rtsx_pci_enable_oobs_polling()
1241 rtsx_pci_write_register(pcr, REG_CFG_OOBS_OFF_TIMER, 0xFF, 0x32); in rtsx_pci_enable_oobs_polling()
1242 rtsx_pci_write_register(pcr, REG_CFG_OOBS_ON_TIMER, 0xFF, 0x05); in rtsx_pci_enable_oobs_polling()
1243 rtsx_pci_write_register(pcr, REG_CFG_VCM_ON_TIMER, 0xFF, 0x83); in rtsx_pci_enable_oobs_polling()
1244 rtsx_pci_write_register(pcr, REG_CFG_OOBS_POLLING, 0xFF, 0xDE); in rtsx_pci_enable_oobs_polling()
1253 rtsx_pci_read_phy_register(pcr, 0x01, &val); in rtsx_pci_disable_oobs_polling()
1255 rtsx_pci_write_phy_register(pcr, 0x01, val); in rtsx_pci_disable_oobs_polling()
1257 rtsx_pci_write_register(pcr, REG_CFG_VCM_ON_TIMER, 0xFF, 0x03); in rtsx_pci_disable_oobs_polling()
1258 rtsx_pci_write_register(pcr, REG_CFG_OOBS_POLLING, 0xFF, 0x00); in rtsx_pci_disable_oobs_polling()
1265 MS_CLK_EN | SD40_CLK_EN, 0); in rtsx_sd_power_off_card3v3()
1266 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0); in rtsx_sd_power_off_card3v3()
1273 return 0; in rtsx_sd_power_off_card3v3()
1279 MS_CLK_EN | SD40_CLK_EN, 0); in rtsx_ms_power_off_card3v3()
1283 rtsx_pci_write_register(pcr, CARD_OE, MS_OUTPUT_EN, 0); in rtsx_ms_power_off_card3v3()
1286 return 0; in rtsx_ms_power_off_card3v3()
1306 RTS5261_MCU_CLOCK_GATING, 0); in rtsx_pci_init_hw()
1308 SSC_POWER_DOWN, 0); in rtsx_pci_init_hw()
1310 err = rtsx_pci_write_register(pcr, FPDCTL, SSC_POWER_DOWN, 0); in rtsx_pci_init_hw()
1312 if (err < 0) in rtsx_pci_init_hw()
1321 if (err < 0) in rtsx_pci_init_hw()
1328 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, 0x07, 0x07); in rtsx_pci_init_hw()
1330 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, HOST_SLEEP_STATE, 0x03, 0x00); in rtsx_pci_init_hw()
1332 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, 0x1E, 0); in rtsx_pci_init_hw()
1334 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x0A, 0); in rtsx_pci_init_hw()
1337 0xFF, pcr->card_drive_sel); in rtsx_pci_init_hw()
1340 0xFF, SSC_8X_EN | SSC_SEL_4M); in rtsx_pci_init_hw()
1342 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, in rtsx_pci_init_hw()
1345 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, in rtsx_pci_init_hw()
1348 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, 0x12); in rtsx_pci_init_hw()
1351 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x16, 0x10); in rtsx_pci_init_hw()
1358 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PERST_GLITCH_WIDTH, 0xFF, 0x80); in rtsx_pci_init_hw()
1360 * bit[0] F_HIGH: for RC oscillator, Rst_value is 1'b1 in rtsx_pci_init_hw()
1361 * 1: 2M 0: 400k in rtsx_pci_init_hw()
1363 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RCCTL, 0x01, 0x00); in rtsx_pci_init_hw()
1366 * 1: Enable ELBI interrupt[31:22] & [7:0] flag read clear in rtsx_pci_init_hw()
1367 * 0: ELBI interrupt flag[31:22] & [7:0] only can be write clear in rtsx_pci_init_hw()
1369 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, NFTS_TX_CTRL, 0x02, 0); in rtsx_pci_init_hw()
1372 if (err < 0) in rtsx_pci_init_hw()
1393 0, PCI_EXP_LNKCTL_CLKREQ_EN); in rtsx_pci_init_hw()
1395 pci_write_config_byte(pdev, 0x70F, 0x5B); in rtsx_pci_init_hw()
1399 if (err < 0) in rtsx_pci_init_hw()
1404 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0x30, 0x30); in rtsx_pci_init_hw()
1414 return 0; in rtsx_pci_init_hw()
1428 case 0x5209: in rtsx_pci_init_chip()
1432 case 0x5229: in rtsx_pci_init_chip()
1436 case 0x5289: in rtsx_pci_init_chip()
1440 case 0x5227: in rtsx_pci_init_chip()
1444 case 0x522A: in rtsx_pci_init_chip()
1448 case 0x5249: in rtsx_pci_init_chip()
1452 case 0x524A: in rtsx_pci_init_chip()
1456 case 0x525A: in rtsx_pci_init_chip()
1460 case 0x5287: in rtsx_pci_init_chip()
1464 case 0x5286: in rtsx_pci_init_chip()
1468 case 0x5260: in rtsx_pci_init_chip()
1472 case 0x5261: in rtsx_pci_init_chip()
1476 case 0x5228: in rtsx_pci_init_chip()
1481 pcr_dbg(pcr, "PID: 0x%04x, IC version: 0x%02x\n", in rtsx_pci_init_chip()
1507 pcr_dbg(pcr, "pcr->aspm_en = 0x%x\n", pcr->aspm_en); in rtsx_pci_init_chip()
1508 pcr_dbg(pcr, "pcr->sd30_drive_sel_1v8 = 0x%x\n", in rtsx_pci_init_chip()
1510 pcr_dbg(pcr, "pcr->sd30_drive_sel_3v3 = 0x%x\n", in rtsx_pci_init_chip()
1512 pcr_dbg(pcr, "pcr->card_drive_sel = 0x%x\n", in rtsx_pci_init_chip()
1514 pcr_dbg(pcr, "pcr->flags = 0x%x\n", pcr->flags); in rtsx_pci_init_chip()
1518 if (err < 0) { in rtsx_pci_init_chip()
1523 return 0; in rtsx_pci_init_chip()
1532 int ret, i, bar = 0; in rtsx_pci_probe()
1540 if (ret < 0) in rtsx_pci_probe()
1566 ret = idr_alloc(&rtsx_pci_idr, pcr, 0, 0, GFP_NOWAIT); in rtsx_pci_probe()
1567 if (ret >= 0) in rtsx_pci_probe()
1571 if (ret < 0) in rtsx_pci_probe()
1577 if (CHK_PCI_PID(pcr, 0x525A)) in rtsx_pci_probe()
1598 pcr->card_inserted = 0; in rtsx_pci_probe()
1599 pcr->card_removed = 0; in rtsx_pci_probe()
1611 if (ret < 0) in rtsx_pci_probe()
1618 if (ret < 0) in rtsx_pci_probe()
1621 for (i = 0; i < ARRAY_SIZE(rtsx_pcr_cells); i++) { in rtsx_pci_probe()
1635 ARRAY_SIZE(rtsx_pcr_cells), NULL, 0, NULL); in rtsx_pci_probe()
1636 if (ret < 0) in rtsx_pci_probe()
1641 return 0; in rtsx_pci_probe()
1678 rtsx_pci_writel(pcr, RTSX_BIER, 0); in rtsx_pci_remove()
1679 pcr->bier = 0; in rtsx_pci_remove()
1738 return 0; in rtsx_pci_suspend()
1746 int ret = 0; in rtsx_pci_resume()
1755 ret = rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, 0x00); in rtsx_pci_resume()
1812 return 0; in rtsx_pci_runtime_suspend()
1827 rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, 0x00); in rtsx_pci_runtime_resume()
1844 return 0; in rtsx_pci_runtime_resume()