29 		{0x96, 0x96, 0x96},  in rts5261_fill_driving()
30 		{0x96, 0x96, 0x96},  in rts5261_fill_driving()
31 		{0x7F, 0x7F, 0x7F},  in rts5261_fill_driving()
32 		{0x13, 0x13, 0x13},  in rts5261_fill_driving()
35 		{0xB3, 0xB3, 0xB3},  in rts5261_fill_driving()
36 		{0x3A, 0x3A, 0x3A},  in rts5261_fill_driving()
37 		{0xE6, 0xE6, 0xE6},  in rts5261_fill_driving()
38 		{0x99, 0x99, 0x99},  in rts5261_fill_driving()
51 			 0xFF, driving[drive_sel][0]);  in rts5261_fill_driving()
54 			 0xFF, driving[drive_sel][1]);  in rts5261_fill_driving()
57 			 0xFF, driving[drive_sel][2]);  in rts5261_fill_driving()
65 	/* 0x814~0x817 */  in rtsx5261_fetch_vendor_settings()
67 	pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);  in rtsx5261_fetch_vendor_settings()
85 	/* 0x724~0x727 */  in rtsx5261_fetch_vendor_settings()
87 	pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);  in rtsx5261_fetch_vendor_settings()
96 	/* Set relink_time to 0 */  in rts5261_force_power_down()
97 	rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, MASK_8_BIT_DEF, 0);  in rts5261_force_power_down()
98 	rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, MASK_8_BIT_DEF, 0);  in rts5261_force_power_down()
100 				RELINK_TIME_MASK, 0);  in rts5261_force_power_down()
125 		0x02, 0x02);  in rts5261_turn_on_led()
131 		0x02, 0x00);  in rts5261_turn_off_led()
135  *     SD_DAT[3:0] ==> pull up
142 	RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
143 	RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
144 	0,
148  *     SD_DAT[3:0] ==> pull down
155 	RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
156 	RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
157 	0,
165 	rtsx_pci_write_register(pcr, CARD_CLK_SOURCE, 0xFF,  in rts5261_sd_set_sample_push_timing_sd30()
167 	rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);  in rts5261_sd_set_sample_push_timing_sd30()
169 	return 0;  in rts5261_sd_set_sample_push_timing_sd30()
195 	rtsx_pci_write_register(pcr, SD_CFG1, 0xFF,  in rts5261_card_power_on()
199 			0xFF, SD20_RX_POS_EDGE);  in rts5261_card_power_on()
200 	rtsx_pci_write_register(pcr, SD_PUSH_POINT_CTL, 0xFF, 0);  in rts5261_card_power_on()
205 	rtsx_pci_write_register(pcr, SD_CFG3, SD30_CLK_END_EN, 0);  in rts5261_card_power_on()
208 			SD30_CLK_STOP_CFG0, 0);  in rts5261_card_power_on()
214 	return 0;  in rts5261_card_power_on()
220 	u16 val = 0;  in rts5261_switch_output_voltage()
230 		if (err < 0)  in rts5261_switch_output_voltage()
236 				SD_IO_USING_1V8, 0);  in rts5261_switch_output_voltage()
242 		if (err < 0)  in rts5261_switch_output_voltage()
257 	return 0;  in rts5261_switch_output_voltage()
279 	u8 val = 0;  in rts5261_enable_ocp()
285 	rtsx_pci_write_register(pcr, REG_OCPCTL, 0xFF, val);  in rts5261_enable_ocp()
291 	u8 mask = 0;  in rts5261_disable_ocp()
294 	rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);  in rts5261_disable_ocp()
296 			RTS5261_LDO1_OCP_EN | RTS5261_LDO1_OCP_LMT_EN, 0);  in rts5261_disable_ocp()
302 	int err = 0;  in rts5261_card_power_off()
306 				RTS5261_LDO_POWERON_MASK, 0);  in rts5261_card_power_off()
309 		CFG_SD_POW_AUTO_PD, 0);  in rts5261_card_power_off()
341 			RTS5261_LDO1_OCP_EN | RTS5261_LDO1_OCP_LMT_EN, 0);  in rts5261_init_ocp()
347 	u8 mask = 0;  in rts5261_clear_ocpstat()
348 	u8 val = 0;  in rts5261_clear_ocpstat()
356 	rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);  in rts5261_clear_ocpstat()
370 		rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0);  in rts5261_process_ocp()
371 		pcr->ocp_stat = 0;  in rts5261_process_ocp()
388 		RTS5261_EFUSE_ADDR_MASK, 0x00);  in rts5261_init_from_hw()
394 	for (i = 0; i < MAX_RW_REG_CNT; i++) {  in rts5261_init_from_hw()
396 		if ((tmp & 0x80) == 0)  in rts5261_init_from_hw()
400 	efuse_valid = ((tmp & 0x0C) >> 2);  in rts5261_init_from_hw()
401 	pcr_dbg(pcr, "Load efuse valid: 0x%x\n", efuse_valid);  in rts5261_init_from_hw()
403 	if (efuse_valid == 0) {  in rts5261_init_from_hw()
405 		if (retval != 0)  in rts5261_init_from_hw()
406 			pcr_dbg(pcr, "read 0x814 DW fail\n");  in rts5261_init_from_hw()
407 		pcr_dbg(pcr, "DW from 0x814: 0x%x\n", lval);  in rts5261_init_from_hw()
408 		/* 0x816 */  in rts5261_init_from_hw()
409 		valid = (u8)((lval >> 16) & 0x03);  in rts5261_init_from_hw()
410 		pcr_dbg(pcr, "0x816: %d\n", valid);  in rts5261_init_from_hw()
413 		REG_EFUSE_POR, 0);  in rts5261_init_from_hw()
417 	lval = lval & 0x00FFFFFF;  in rts5261_init_from_hw()
419 	if (retval != 0)  in rts5261_init_from_hw()
458 	rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0xFF, 0);  in rts5261_init_from_cfg()
495 	rtsx_pci_write_register(pcr, L1SUB_CONFIG3, 0xFF, 0);  in rts5261_extra_init_hw()
499 		rtsx_pci_writel(pcr, RTSX_DUM_REG, val | 0x1);  in rts5261_extra_init_hw()
502 			RTS5261_AUX_CLK_16M_EN, 0);  in rts5261_extra_init_hw()
506 			RTS5261_FORCE_PRSNT_LOW, 0);  in rts5261_extra_init_hw()
517 	rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x0F, 0x02);  in rts5261_extra_init_hw()
523 		rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x30);  in rts5261_extra_init_hw()
525 		rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x00);  in rts5261_extra_init_hw()
538 	rtsx_pci_write_register(pcr, PWD_SUSPEND_EN, 0xFF, 0xFB);  in rts5261_extra_init_hw()
539 	rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x10, 0x00);  in rts5261_extra_init_hw()
545 		RTS5261_INFORM_RTD3_COLD, 0);  in rts5261_extra_init_hw()
547 	return 0;  in rts5261_extra_init_hw()
558 	val |= (pcr->aspm_en & 0x02);  in rts5261_enable_aspm()
574 					   PCI_EXP_LNKCTL_ASPMC, 0);  in rts5261_disable_aspm()
576 	rtsx_pci_write_register(pcr, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);  in rts5261_disable_aspm()
593 	u8 val = 0;  in rts5261_set_l1off_cfg_sub_d0()
664 	if (err < 0)  in rts5261_pci_switch_clock()
677 		return 0;  in rts5261_pci_switch_clock()
728 		ssc_depth = 0;  in rts5261_pci_switch_clock()
736 			0xFF, (div << 4) | mcu_cnt);  in rts5261_pci_switch_clock()
737 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);  in rts5261_pci_switch_clock()
740 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n);  in rts5261_pci_switch_clock()
744 				PHASE_NOT_RESET, 0);  in rts5261_pci_switch_clock()
746 				PHASE_NOT_RESET, 0);  in rts5261_pci_switch_clock()
754 	if (err < 0)  in rts5261_pci_switch_clock()
759 	err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);  in rts5261_pci_switch_clock()
760 	if (err < 0)  in rts5261_pci_switch_clock()
764 	return 0;  in rts5261_pci_switch_clock()
781 	pcr->flags = 0;  in rts5261_init_params()
783 	pcr->sd30_drive_sel_1v8 = 0x00;  in rts5261_init_params()
784 	pcr->sd30_drive_sel_3v3 = 0x00;  in rts5261_init_params()
805 	option->ltr_l1off_sspwrgate = 0x7F;  in rts5261_init_params()
806 	option->ltr_l1off_snooze_sspwrgate = 0x78;  in rts5261_init_params()