40 	DEFINE_RES_MEM(0x800, 0x200),
44 #define SCR_REVID	0x08		/* b Revision ID	*/
45 #define SCR_IMR		0x42		/* b Interrupt Mask	*/
46 #define SCR_DEV_CTL	0xe0		/* b Device control	*/
47 #define SCR_ISR		0xe1		/* b Interrupt Status	*/
48 #define SCR_GPO_OC	0xf0		/* b GPO output control	*/
49 #define SCR_GPO_OS	0xf1		/* b GPO output enable	*/
50 #define SCR_GPI_S	0xf2		/* w GPI status		*/
51 #define SCR_APDC	0xf8		/* b Active pullup down ctrl */
53 #define SCR_DEV_CTL_USB		BIT(0)	/* USB enable		*/
91 	tmio_core_mmc_enable(t7l66xb->scr + 0x200, 0,  in t7l66xb_mmc_enable()
92 		t7l66xb_mmc_resources[0].start & 0xfffe);  in t7l66xb_mmc_enable()
94 	return 0;  in t7l66xb_mmc_enable()
113 	return 0;  in t7l66xb_mmc_disable()
120 	tmio_core_mmc_pwr(t7l66xb->scr + 0x200, 0, state);  in t7l66xb_mmc_pwr()
127 	tmio_core_mmc_clk_div(t7l66xb->scr + 0x200, 0, state);  in t7l66xb_mmc_clk_div()
140 		.start	= 0xc00,
141 		.end	= 0xc07,
145 		.start	= 0x0100,
146 		.end	= 0x01ff,
186 		for (i = 0; i < T7L66XB_NR_IRQS; i++)  in t7l66xb_irq()
270 	return 0;  in t7l66xb_suspend()
286 	tmio_core_mmc_enable(t7l66xb->scr + 0x200, 0,  in t7l66xb_resume()
287 		t7l66xb_mmc_resources[0].start & 0xfffe);  in t7l66xb_resume()
289 	return 0;  in t7l66xb_resume()
308 	iomem = platform_get_resource(dev, IORESOURCE_MEM, 0);  in t7l66xb_probe()
320 	ret = platform_get_irq(dev, 0);  in t7l66xb_probe()
321 	if (ret >= 0)  in t7l66xb_probe()
343 	rscr->end = iomem->start + 0xff;  in t7l66xb_probe()
364 	tmio_iowrite8(0xbf, t7l66xb->scr + SCR_IMR);  in t7l66xb_probe()
366 	printk(KERN_INFO "%s rev %d @ 0x%08lx, irq %d\n",  in t7l66xb_probe()
380 		return 0;  in t7l66xb_probe()