Lines Matching +full:16 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <dt-bindings/memory/tegra30-mc.h>
48 .fifo_size = 16 * 2,
56 .bit = 1,
65 .fifo_size = 16 * 128,
73 .bit = 2,
82 .fifo_size = 16 * 128,
90 .bit = 3,
94 .shift = 16,
99 .fifo_size = 16 * 64,
107 .bit = 4,
111 .shift = 16,
116 .fifo_size = 16 * 64,
124 .bit = 5,
133 .fifo_size = 16 * 128,
141 .bit = 6,
150 .fifo_size = 16 * 128,
158 .bit = 7,
162 .shift = 16,
167 .fifo_size = 16 * 64,
175 .bit = 8,
179 .shift = 16,
184 .fifo_size = 16 * 64,
192 .bit = 9,
201 .fifo_size = 16 * 8,
209 .bit = 10,
218 .fifo_size = 16 * 64,
226 .bit = 11,
230 .shift = 16,
235 .fifo_size = 16 * 64,
243 .bit = 12,
252 .fifo_size = 16 * 8,
260 .bit = 13,
269 .fifo_size = 16 * 8,
277 .bit = 14,
286 .fifo_size = 16 * 32,
294 .bit = 15,
303 .fifo_size = 16 * 2,
311 .bit = 16,
320 .fifo_size = 16 * 2,
328 .bit = 17,
337 .fifo_size = 16 * 2,
345 .bit = 18,
354 .fifo_size = 16 * 48,
362 .bit = 19,
371 .fifo_size = 16 * 48,
379 .bit = 20,
388 .fifo_size = 16 * 48,
396 .bit = 21,
405 .fifo_size = 16 * 16,
413 .bit = 22,
422 .fifo_size = 16 * 16,
430 .bit = 23,
434 .shift = 16,
439 .fifo_size = 16 * 8,
447 .bit = 24,
451 .shift = 16,
456 .fifo_size = 16 * 64,
464 .bit = 25,
468 .shift = 16,
473 .fifo_size = 16 * 64,
481 .bit = 26,
485 .shift = 16,
490 .fifo_size = 16 * 2,
498 .bit = 27,
507 .fifo_size = 16 * 64,
515 .bit = 28,
519 .shift = 16,
524 .fifo_size = 16 * 8,
532 .bit = 29,
541 .fifo_size = 16 * 2,
549 .bit = 30,
553 .shift = 16,
558 .fifo_size = 16 * 8,
566 .bit = 31,
575 .fifo_size = 16 * 32,
583 .bit = 0,
592 .fifo_size = 16 * 64,
600 .bit = 1,
609 .fifo_size = 16 * 64,
617 .bit = 2,
626 .fifo_size = 16 * 8,
634 .bit = 3,
638 .shift = 16,
643 .fifo_size = 16 * 4,
651 .bit = 4,
660 .fifo_size = 16 * 16,
668 .bit = 5,
672 .shift = 16,
677 .fifo_size = 16 * 16,
690 .fifo_size = 16 * 14,
703 .fifo_size = 16 * 14,
711 .bit = 8,
715 .shift = 16,
720 .fifo_size = 16 * 64,
728 .bit = 9,
737 .fifo_size = 16 * 64,
745 .bit = 10,
749 .shift = 16,
754 .fifo_size = 16 * 64,
762 .bit = 11,
771 .fifo_size = 16 * 8,
779 .bit = 12,
783 .shift = 16,
788 .fifo_size = 16 * 64,
796 .bit = 13,
805 .fifo_size = 16 * 64,
813 .bit = 14,
817 .shift = 16,
822 .fifo_size = 16 * 64,
830 .bit = 15,
839 .fifo_size = 16 * 64,
847 .bit = 16,
851 .shift = 16,
856 .fifo_size = 16 * 128,
864 .bit = 17,
868 .shift = 16,
873 .fifo_size = 16 * 32,
881 .bit = 18,
885 .shift = 16,
890 .fifo_size = 16 * 2,
898 .bit = 19,
902 .shift = 16,
907 .fifo_size = 16 * 48,
915 .bit = 20,
919 .shift = 16,
924 .fifo_size = 16 * 48,
932 .bit = 21,
936 .shift = 16,
941 .fifo_size = 16 * 16,
949 .bit = 22,
958 .fifo_size = 16 * 32,
966 .bit = 23,
975 .fifo_size = 16 * 64,
983 .shift = 16,
988 .fifo_size = 16 * 24,
996 .shift = 16,
1001 .fifo_size = 16 * 24,
1009 .bit = 26,
1013 .shift = 16,
1018 .fifo_size = 16 * 8,
1026 .bit = 27,
1035 .fifo_size = 16 * 2,
1043 .bit = 28,
1047 .shift = 16,
1052 .fifo_size = 16 * 4,
1060 .bit = 29,
1064 .shift = 16,
1069 .fifo_size = 16 * 32,
1077 .bit = 30,
1086 .fifo_size = 16 * 4,
1094 .bit = 31,
1098 .shift = 16,
1103 .fifo_size = 16 * 16,
1111 .bit = 0,
1120 .fifo_size = 16 * 2,
1128 .bit = 1,
1132 .shift = 16,
1137 .fifo_size = 16 * 16,
1185 .num_tlb_lines = 16,
1195 .bit = _bit, \
1215 TEGRA30_MC_RESET(VDE, 0x200, 0x204, 16),
1224 unsigned int fifo_size = client->fifo_size; in tegra30_mc_tune_client_latency()
1244 switch (client->swgroup) { in tegra30_mc_tune_client_latency()
1271 arb_nsec -= arb_tolerance_compensation_nsec; in tegra30_mc_tune_client_latency()
1279 * client may wait in the EMEM arbiter before it becomes a high-priority in tegra30_mc_tune_client_latency()
1282 la_ticks = arb_nsec / mc->tick; in tegra30_mc_tune_client_latency()
1283 la_ticks = min(la_ticks, client->regs.la.mask); in tegra30_mc_tune_client_latency()
1285 value = mc_readl(mc, client->regs.la.reg); in tegra30_mc_tune_client_latency()
1286 value &= ~(client->regs.la.mask << client->regs.la.shift); in tegra30_mc_tune_client_latency()
1287 value |= la_ticks << client->regs.la.shift; in tegra30_mc_tune_client_latency()
1288 mc_writel(mc, value, client->regs.la.reg); in tegra30_mc_tune_client_latency()
1293 struct tegra_mc *mc = icc_provider_to_tegra_mc(src->provider); in tegra30_mc_icc_set()
1294 const struct tegra_mc_client *client = &mc->soc->clients[src->id]; in tegra30_mc_icc_set()
1295 u64 peak_bandwidth = icc_units_to_bps(src->peak_bw); in tegra30_mc_icc_set()
1298 * Skip pre-initialization that is done by icc_node_add(), which sets in tegra30_mc_icc_set()
1320 * ISO clients need to reserve extra bandwidth up-front because in tegra30_mc_icc_aggreate()
1339 unsigned int i, idx = spec->args[0]; in tegra30_mc_of_icc_xlate_extended()
1343 list_for_each_entry(node, &mc->provider.nodes, node_list) { in tegra30_mc_of_icc_xlate_extended()
1344 if (node->id != idx) in tegra30_mc_of_icc_xlate_extended()
1349 return ERR_PTR(-ENOMEM); in tegra30_mc_of_icc_xlate_extended()
1351 client = &mc->soc->clients[idx]; in tegra30_mc_of_icc_xlate_extended()
1352 ndata->node = node; in tegra30_mc_of_icc_xlate_extended()
1354 switch (client->swgroup) { in tegra30_mc_of_icc_xlate_extended()
1360 ndata->tag = TEGRA_MC_ICC_TAG_ISO; in tegra30_mc_of_icc_xlate_extended()
1364 ndata->tag = TEGRA_MC_ICC_TAG_DEFAULT; in tegra30_mc_of_icc_xlate_extended()
1371 for (i = 0; i < mc->soc->num_clients; i++) { in tegra30_mc_of_icc_xlate_extended()
1372 if (mc->soc->clients[i].id == idx) in tegra30_mc_of_icc_xlate_extended()
1373 return ERR_PTR(-EPROBE_DEFER); in tegra30_mc_of_icc_xlate_extended()
1376 dev_err(mc->dev, "invalid ICC client ID %u\n", idx); in tegra30_mc_of_icc_xlate_extended()
1378 return ERR_PTR(-EINVAL); in tegra30_mc_of_icc_xlate_extended()
1391 .atom_size = 16,