Lines Matching +full:emc +full:- +full:timings +full:-
1 // SPDX-License-Identifier: GPL-2.0+
5 * Based on downstream driver from NVIDIA and tegra124-emc.c
6 * Copyright (C) 2011-2014 NVIDIA Corporation
9 * Copyright (C) 2019 GRATE-DRIVER project
17 #include <linux/interconnect-provider.h>
353 struct emc_timing *timings; member
374 * There are multiple sources in the EMC driver which could request
379 /* protect shared rate-change code path */
383 static int emc_seq_update_timing(struct tegra_emc *emc) in emc_seq_update_timing() argument
388 writel_relaxed(EMC_TIMING_UPDATE, emc->regs + EMC_TIMING_CONTROL); in emc_seq_update_timing()
390 err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_STATUS, val, in emc_seq_update_timing()
394 dev_err(emc->dev, "failed to update timing: %d\n", err); in emc_seq_update_timing()
403 struct tegra_emc *emc = data; in tegra_emc_isr() local
407 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; in tegra_emc_isr()
413 dev_err_ratelimited(emc->dev, in tegra_emc_isr()
417 writel_relaxed(status, emc->regs + EMC_INTSTATUS); in tegra_emc_isr()
422 static struct emc_timing *emc_find_timing(struct tegra_emc *emc, in emc_find_timing() argument
428 for (i = 0; i < emc->num_timings; i++) { in emc_find_timing()
429 if (emc->timings[i].rate >= rate) { in emc_find_timing()
430 timing = &emc->timings[i]; in emc_find_timing()
436 dev_err(emc->dev, "no timing for rate %lu\n", rate); in emc_find_timing()
443 static bool emc_dqs_preset(struct tegra_emc *emc, struct emc_timing *timing, in emc_dqs_preset() argument
449 if (timing->data[71] & EMC_XM2DQSPADCTRL2_VREF_ENABLE) { in emc_dqs_preset()
450 val = readl_relaxed(emc->regs + EMC_XM2DQSPADCTRL2); in emc_dqs_preset()
454 writel_relaxed(val, emc->regs + EMC_XM2DQSPADCTRL2); in emc_dqs_preset()
460 if (timing->data[78] & EMC_XM2DQSPADCTRL3_VREF_ENABLE) { in emc_dqs_preset()
461 val = readl_relaxed(emc->regs + EMC_XM2DQSPADCTRL3); in emc_dqs_preset()
465 writel_relaxed(val, emc->regs + EMC_XM2DQSPADCTRL3); in emc_dqs_preset()
471 if (timing->data[77] & EMC_XM2QUSEPADCTRL_IVREF_ENABLE) { in emc_dqs_preset()
472 val = readl_relaxed(emc->regs + EMC_XM2QUSEPADCTRL); in emc_dqs_preset()
476 writel_relaxed(val, emc->regs + EMC_XM2QUSEPADCTRL); in emc_dqs_preset()
486 static int emc_prepare_mc_clk_cfg(struct tegra_emc *emc, unsigned long rate) in emc_prepare_mc_clk_cfg() argument
488 struct tegra_mc *mc = emc->mc; in emc_prepare_mc_clk_cfg()
493 for (i = 0; i < mc->num_timings; i++) { in emc_prepare_mc_clk_cfg()
494 if (mc->timings[i].rate != rate) in emc_prepare_mc_clk_cfg()
497 if (mc->timings[i].emem_data[misc0_index] & BIT(27)) in emc_prepare_mc_clk_cfg()
502 return tegra20_clk_prepare_emc_mc_same_freq(emc->clk, same); in emc_prepare_mc_clk_cfg()
505 return -EINVAL; in emc_prepare_mc_clk_cfg()
508 static int emc_prepare_timing_change(struct tegra_emc *emc, unsigned long rate) in emc_prepare_timing_change() argument
510 struct emc_timing *timing = emc_find_timing(emc, rate); in emc_prepare_timing_change()
523 if (!timing || emc->bad_state) in emc_prepare_timing_change()
524 return -EINVAL; in emc_prepare_timing_change()
526 dev_dbg(emc->dev, "%s: using timing rate %lu for requested rate %lu\n", in emc_prepare_timing_change()
527 __func__, timing->rate, rate); in emc_prepare_timing_change()
529 emc->bad_state = true; in emc_prepare_timing_change()
531 err = emc_prepare_mc_clk_cfg(emc, rate); in emc_prepare_timing_change()
533 dev_err(emc->dev, "mc clock preparation failed: %d\n", err); in emc_prepare_timing_change()
537 emc->vref_cal_toggle = false; in emc_prepare_timing_change()
538 emc->mc_override = mc_readl(emc->mc, MC_EMEM_ARB_OVERRIDE); in emc_prepare_timing_change()
539 emc->emc_cfg = readl_relaxed(emc->regs + EMC_CFG); in emc_prepare_timing_change()
540 emc_dbg = readl_relaxed(emc->regs + EMC_DBG); in emc_prepare_timing_change()
542 if (emc->dll_on == !!(timing->emc_mode_1 & 0x1)) in emc_prepare_timing_change()
544 else if (timing->emc_mode_1 & 0x1) in emc_prepare_timing_change()
549 emc->dll_on = !!(timing->emc_mode_1 & 0x1); in emc_prepare_timing_change()
551 if (timing->data[80] && !readl_relaxed(emc->regs + EMC_ZCAL_INTERVAL)) in emc_prepare_timing_change()
552 emc->zcal_long = true; in emc_prepare_timing_change()
554 emc->zcal_long = false; in emc_prepare_timing_change()
556 fbio_cfg5 = readl_relaxed(emc->regs + EMC_FBIO_CFG5); in emc_prepare_timing_change()
559 dram_num = tegra_mc_get_emem_device_count(emc->mc); in emc_prepare_timing_change()
561 /* disable dynamic self-refresh */ in emc_prepare_timing_change()
562 if (emc->emc_cfg & EMC_CFG_DYN_SREF_ENABLE) { in emc_prepare_timing_change()
563 emc->emc_cfg &= ~EMC_CFG_DYN_SREF_ENABLE; in emc_prepare_timing_change()
564 writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG); in emc_prepare_timing_change()
570 val = mc_readl(emc->mc, MC_EMEM_ARB_OUTSTANDING_REQ); in emc_prepare_timing_change()
576 mc_writel(emc->mc, val, MC_EMEM_ARB_OUTSTANDING_REQ); in emc_prepare_timing_change()
577 mc_writel(emc->mc, MC_TIMING_UPDATE, MC_TIMING_CONTROL); in emc_prepare_timing_change()
580 if (emc->mc_override & MC_EMEM_ARB_OVERRIDE_EACK_MASK) in emc_prepare_timing_change()
581 mc_writel(emc->mc, in emc_prepare_timing_change()
582 emc->mc_override & ~MC_EMEM_ARB_OVERRIDE_EACK_MASK, in emc_prepare_timing_change()
586 if (emc_dqs_preset(emc, timing, &schmitt_to_vref)) { in emc_prepare_timing_change()
592 err = emc_seq_update_timing(emc); in emc_prepare_timing_change()
599 /* disable auto-calibration if VREF mode is switching */ in emc_prepare_timing_change()
600 if (timing->emc_auto_cal_interval) { in emc_prepare_timing_change()
601 val = readl_relaxed(emc->regs + EMC_XM2COMPPADCTRL); in emc_prepare_timing_change()
602 val ^= timing->data[74]; in emc_prepare_timing_change()
605 writel_relaxed(0, emc->regs + EMC_AUTO_CAL_INTERVAL); in emc_prepare_timing_change()
608 emc->regs + EMC_AUTO_CAL_STATUS, val, in emc_prepare_timing_change()
611 dev_err(emc->dev, in emc_prepare_timing_change()
612 "auto-cal finish timeout: %d\n", err); in emc_prepare_timing_change()
616 emc->vref_cal_toggle = true; in emc_prepare_timing_change()
621 for (i = 0; i < ARRAY_SIZE(timing->data); i++) { in emc_prepare_timing_change()
624 writel_relaxed(timing->data[i], in emc_prepare_timing_change()
625 emc->regs + emc_timing_registers[i]); in emc_prepare_timing_change()
628 err = tegra_mc_write_emem_configuration(emc->mc, timing->rate); in emc_prepare_timing_change()
636 if (emc->zcal_long) in emc_prepare_timing_change()
637 cnt -= dram_num * 256; in emc_prepare_timing_change()
639 val = timing->data[82] & EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK; in emc_prepare_timing_change()
643 val = timing->data[82] & ~EMC_MRS_WAIT_CNT_LONG_WAIT_MASK; in emc_prepare_timing_change()
647 writel_relaxed(val, emc->regs + EMC_MRS_WAIT_CNT); in emc_prepare_timing_change()
651 val = readl_relaxed(emc->regs + EMC_SEL_DPD_CTRL); in emc_prepare_timing_change()
659 new_mode = timing->data[39] & EMC_CFG5_QUSE_MODE_MASK; in emc_prepare_timing_change()
670 writel_relaxed(0x1, emc->regs + EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE); in emc_prepare_timing_change()
675 emc->regs + EMC_DBG); in emc_prepare_timing_change()
676 writel_relaxed(emc->emc_cfg | EMC_CFG_PERIODIC_QRST, in emc_prepare_timing_change()
677 emc->regs + EMC_CFG); in emc_prepare_timing_change()
678 writel_relaxed(emc_dbg, emc->regs + EMC_DBG); in emc_prepare_timing_change()
681 /* disable auto-refresh to save time after clock change */ in emc_prepare_timing_change()
683 emc->regs + EMC_REFCTRL); in emc_prepare_timing_change()
685 /* turn off DLL and enter self-refresh on DDR3 */ in emc_prepare_timing_change()
688 writel_relaxed(timing->emc_mode_1, in emc_prepare_timing_change()
689 emc->regs + EMC_EMRS); in emc_prepare_timing_change()
693 emc->regs + EMC_SELF_REF); in emc_prepare_timing_change()
697 writel_relaxed(0x1, emc->regs + EMC_STALL_THEN_EXE_AFTER_CLKCHANGE); in emc_prepare_timing_change()
699 /* enable write-active MUX, update unshadowed pad control */ in emc_prepare_timing_change()
700 writel_relaxed(emc_dbg | EMC_DBG_WRITE_MUX_ACTIVE, emc->regs + EMC_DBG); in emc_prepare_timing_change()
701 writel_relaxed(timing->data[73], emc->regs + EMC_XM2CLKPADCTRL); in emc_prepare_timing_change()
703 /* restore periodic QRST and disable write-active MUX */ in emc_prepare_timing_change()
704 val = !!(emc->emc_cfg & EMC_CFG_PERIODIC_QRST); in emc_prepare_timing_change()
705 if (qrst_used || timing->emc_cfg_periodic_qrst != val) { in emc_prepare_timing_change()
706 if (timing->emc_cfg_periodic_qrst) in emc_prepare_timing_change()
707 emc->emc_cfg |= EMC_CFG_PERIODIC_QRST; in emc_prepare_timing_change()
709 emc->emc_cfg &= ~EMC_CFG_PERIODIC_QRST; in emc_prepare_timing_change()
711 writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG); in emc_prepare_timing_change()
713 writel_relaxed(emc_dbg, emc->regs + EMC_DBG); in emc_prepare_timing_change()
715 /* exit self-refresh on DDR3 */ in emc_prepare_timing_change()
718 emc->regs + EMC_SELF_REF); in emc_prepare_timing_change()
720 /* set DRAM-mode registers */ in emc_prepare_timing_change()
722 if (timing->emc_mode_1 != emc->emc_mode_1) in emc_prepare_timing_change()
723 writel_relaxed(timing->emc_mode_1, in emc_prepare_timing_change()
724 emc->regs + EMC_EMRS); in emc_prepare_timing_change()
726 if (timing->emc_mode_2 != emc->emc_mode_2) in emc_prepare_timing_change()
727 writel_relaxed(timing->emc_mode_2, in emc_prepare_timing_change()
728 emc->regs + EMC_EMRS); in emc_prepare_timing_change()
730 if (timing->emc_mode_reset != emc->emc_mode_reset || in emc_prepare_timing_change()
732 val = timing->emc_mode_reset; in emc_prepare_timing_change()
739 writel_relaxed(val, emc->regs + EMC_MRS); in emc_prepare_timing_change()
742 if (timing->emc_mode_2 != emc->emc_mode_2) in emc_prepare_timing_change()
743 writel_relaxed(timing->emc_mode_2, in emc_prepare_timing_change()
744 emc->regs + EMC_MRW); in emc_prepare_timing_change()
746 if (timing->emc_mode_1 != emc->emc_mode_1) in emc_prepare_timing_change()
747 writel_relaxed(timing->emc_mode_1, in emc_prepare_timing_change()
748 emc->regs + EMC_MRW); in emc_prepare_timing_change()
751 emc->emc_mode_1 = timing->emc_mode_1; in emc_prepare_timing_change()
752 emc->emc_mode_2 = timing->emc_mode_2; in emc_prepare_timing_change()
753 emc->emc_mode_reset = timing->emc_mode_reset; in emc_prepare_timing_change()
756 if (emc->zcal_long) { in emc_prepare_timing_change()
758 emc->regs + EMC_ZQ_CAL); in emc_prepare_timing_change()
762 emc->regs + EMC_ZQ_CAL); in emc_prepare_timing_change()
766 writel_relaxed(0x1, emc->regs + EMC_UNSTALL_RW_AFTER_CLKCHANGE); in emc_prepare_timing_change()
769 * Read and discard an arbitrary MC register (Note: EMC registers in emc_prepare_timing_change()
772 mc_readl(emc->mc, MC_EMEM_ARB_OVERRIDE); in emc_prepare_timing_change()
777 static int emc_complete_timing_change(struct tegra_emc *emc, in emc_complete_timing_change() argument
780 struct emc_timing *timing = emc_find_timing(emc, rate); in emc_complete_timing_change()
785 err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_INTSTATUS, v, in emc_complete_timing_change()
789 dev_err(emc->dev, "emc-car handshake timeout: %d\n", err); in emc_complete_timing_change()
793 /* re-enable auto-refresh */ in emc_complete_timing_change()
794 dram_num = tegra_mc_get_emem_device_count(emc->mc); in emc_complete_timing_change()
796 emc->regs + EMC_REFCTRL); in emc_complete_timing_change()
798 /* restore auto-calibration */ in emc_complete_timing_change()
799 if (emc->vref_cal_toggle) in emc_complete_timing_change()
800 writel_relaxed(timing->emc_auto_cal_interval, in emc_complete_timing_change()
801 emc->regs + EMC_AUTO_CAL_INTERVAL); in emc_complete_timing_change()
803 /* restore dynamic self-refresh */ in emc_complete_timing_change()
804 if (timing->emc_cfg_dyn_self_ref) { in emc_complete_timing_change()
805 emc->emc_cfg |= EMC_CFG_DYN_SREF_ENABLE; in emc_complete_timing_change()
806 writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG); in emc_complete_timing_change()
810 if (emc->zcal_long) in emc_complete_timing_change()
811 writel_relaxed(timing->emc_zcal_cnt_long, in emc_complete_timing_change()
812 emc->regs + EMC_ZCAL_WAIT_CNT); in emc_complete_timing_change()
818 err = emc_seq_update_timing(emc); in emc_complete_timing_change()
820 emc->bad_state = false; in emc_complete_timing_change()
823 mc_writel(emc->mc, emc->mc_override, MC_EMEM_ARB_OVERRIDE); in emc_complete_timing_change()
828 static int emc_unprepare_timing_change(struct tegra_emc *emc, in emc_unprepare_timing_change() argument
831 if (!emc->bad_state) { in emc_unprepare_timing_change()
833 dev_err(emc->dev, "timing configuration can't be reverted\n"); in emc_unprepare_timing_change()
834 emc->bad_state = true; in emc_unprepare_timing_change()
843 struct tegra_emc *emc = container_of(nb, struct tegra_emc, clk_nb); in emc_clk_change_notify() local
853 disable_irq(emc->irq); in emc_clk_change_notify()
854 err = emc_prepare_timing_change(emc, cnd->new_rate); in emc_clk_change_notify()
855 enable_irq(emc->irq); in emc_clk_change_notify()
859 err = emc_unprepare_timing_change(emc, cnd->old_rate); in emc_clk_change_notify()
863 err = emc_complete_timing_change(emc, cnd->new_rate); in emc_clk_change_notify()
873 static int load_one_timing_from_dt(struct tegra_emc *emc, in load_one_timing_from_dt() argument
880 err = of_property_read_u32(node, "clock-frequency", &value); in load_one_timing_from_dt()
882 dev_err(emc->dev, "timing %pOF: failed to read rate: %d\n", in load_one_timing_from_dt()
887 timing->rate = value; in load_one_timing_from_dt()
889 err = of_property_read_u32_array(node, "nvidia,emc-configuration", in load_one_timing_from_dt()
890 timing->data, in load_one_timing_from_dt()
893 dev_err(emc->dev, in load_one_timing_from_dt()
894 "timing %pOF: failed to read emc timing data: %d\n", in load_one_timing_from_dt()
900 timing->prop = of_property_read_bool(node, dtprop); in load_one_timing_from_dt()
903 err = of_property_read_u32(node, dtprop, &timing->prop); \ in load_one_timing_from_dt()
905 dev_err(emc->dev, \ in load_one_timing_from_dt()
911 EMC_READ_U32(emc_auto_cal_interval, "nvidia,emc-auto-cal-interval") in load_one_timing_from_dt()
912 EMC_READ_U32(emc_mode_1, "nvidia,emc-mode-1") in load_one_timing_from_dt()
913 EMC_READ_U32(emc_mode_2, "nvidia,emc-mode-2") in load_one_timing_from_dt()
914 EMC_READ_U32(emc_mode_reset, "nvidia,emc-mode-reset") in load_one_timing_from_dt()
915 EMC_READ_U32(emc_zcal_cnt_long, "nvidia,emc-zcal-cnt-long") in load_one_timing_from_dt()
916 EMC_READ_BOOL(emc_cfg_dyn_self_ref, "nvidia,emc-cfg-dyn-self-ref") in load_one_timing_from_dt()
917 EMC_READ_BOOL(emc_cfg_periodic_qrst, "nvidia,emc-cfg-periodic-qrst") in load_one_timing_from_dt()
922 dev_dbg(emc->dev, "%s: %pOF: rate %lu\n", __func__, node, timing->rate); in load_one_timing_from_dt()
932 if (a->rate < b->rate) in cmp_timings()
933 return -1; in cmp_timings()
935 if (a->rate > b->rate) in cmp_timings()
941 static int emc_check_mc_timings(struct tegra_emc *emc) in emc_check_mc_timings() argument
943 struct tegra_mc *mc = emc->mc; in emc_check_mc_timings()
946 if (emc->num_timings != mc->num_timings) { in emc_check_mc_timings()
947 dev_err(emc->dev, "emc/mc timings number mismatch: %u %u\n", in emc_check_mc_timings()
948 emc->num_timings, mc->num_timings); in emc_check_mc_timings()
949 return -EINVAL; in emc_check_mc_timings()
952 for (i = 0; i < mc->num_timings; i++) { in emc_check_mc_timings()
953 if (emc->timings[i].rate != mc->timings[i].rate) { in emc_check_mc_timings()
954 dev_err(emc->dev, in emc_check_mc_timings()
955 "emc/mc timing rate mismatch: %lu %lu\n", in emc_check_mc_timings()
956 emc->timings[i].rate, mc->timings[i].rate); in emc_check_mc_timings()
957 return -EINVAL; in emc_check_mc_timings()
964 static int emc_load_timings_from_dt(struct tegra_emc *emc, in emc_load_timings_from_dt() argument
974 dev_err(emc->dev, "no memory timings in: %pOF\n", node); in emc_load_timings_from_dt()
975 return -EINVAL; in emc_load_timings_from_dt()
978 emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing), in emc_load_timings_from_dt()
980 if (!emc->timings) in emc_load_timings_from_dt()
981 return -ENOMEM; in emc_load_timings_from_dt()
983 emc->num_timings = child_count; in emc_load_timings_from_dt()
984 timing = emc->timings; in emc_load_timings_from_dt()
987 err = load_one_timing_from_dt(emc, timing++, child); in emc_load_timings_from_dt()
994 sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings, in emc_load_timings_from_dt()
997 err = emc_check_mc_timings(emc); in emc_load_timings_from_dt()
1001 dev_info_once(emc->dev, in emc_load_timings_from_dt()
1002 "got %u timings for RAM code %u (min %luMHz max %luMHz)\n", in emc_load_timings_from_dt()
1003 emc->num_timings, in emc_load_timings_from_dt()
1005 emc->timings[0].rate / 1000000, in emc_load_timings_from_dt()
1006 emc->timings[emc->num_timings - 1].rate / 1000000); in emc_load_timings_from_dt()
1017 if (of_get_child_count(dev->of_node) == 0) { in emc_find_node_by_ram_code()
1018 dev_info_once(dev, "device-tree doesn't have memory timings\n"); in emc_find_node_by_ram_code()
1024 for_each_child_of_node(dev->of_node, np) { in emc_find_node_by_ram_code()
1025 err = of_property_read_u32(np, "nvidia,ram-code", &value); in emc_find_node_by_ram_code()
1032 dev_err(dev, "no memory timings for RAM code %u found in device-tree\n", in emc_find_node_by_ram_code()
1038 static int emc_setup_hw(struct tegra_emc *emc) in emc_setup_hw() argument
1044 fbio_cfg5 = readl_relaxed(emc->regs + EMC_FBIO_CFG5); in emc_setup_hw()
1047 emc_cfg = readl_relaxed(emc->regs + EMC_CFG_2); in emc_setup_hw()
1049 /* enable EMC and CAR to handshake on PLL divider/source changes */ in emc_setup_hw()
1065 writel_relaxed(emc_cfg, emc->regs + EMC_CFG_2); in emc_setup_hw()
1068 writel_relaxed(intmask, emc->regs + EMC_INTMASK); in emc_setup_hw()
1069 writel_relaxed(0xffffffff, emc->regs + EMC_INTSTATUS); in emc_setup_hw()
1072 emc_dbg = readl_relaxed(emc->regs + EMC_DBG); in emc_setup_hw()
1077 writel_relaxed(emc_dbg, emc->regs + EMC_DBG); in emc_setup_hw()
1088 struct tegra_emc *emc = arg; in emc_round_rate() local
1091 if (!emc->num_timings) in emc_round_rate()
1092 return clk_get_rate(emc->clk); in emc_round_rate()
1094 min_rate = min(min_rate, emc->timings[emc->num_timings - 1].rate); in emc_round_rate()
1096 for (i = 0; i < emc->num_timings; i++) { in emc_round_rate()
1097 if (emc->timings[i].rate < rate && i != emc->num_timings - 1) in emc_round_rate()
1100 if (emc->timings[i].rate > max_rate) { in emc_round_rate()
1101 i = max(i, 1u) - 1; in emc_round_rate()
1103 if (emc->timings[i].rate < min_rate) in emc_round_rate()
1107 if (emc->timings[i].rate < min_rate) in emc_round_rate()
1110 timing = &emc->timings[i]; in emc_round_rate()
1115 dev_err(emc->dev, "no timing for rate %lu min %lu max %lu\n", in emc_round_rate()
1117 return -EINVAL; in emc_round_rate()
1120 return timing->rate; in emc_round_rate()
1123 static void tegra_emc_rate_requests_init(struct tegra_emc *emc) in tegra_emc_rate_requests_init() argument
1128 emc->requested_rate[i].min_rate = 0; in tegra_emc_rate_requests_init()
1129 emc->requested_rate[i].max_rate = ULONG_MAX; in tegra_emc_rate_requests_init()
1133 static int emc_request_rate(struct tegra_emc *emc, in emc_request_rate() argument
1138 struct emc_rate_request *req = emc->requested_rate; in emc_request_rate()
1149 min_rate = max(req->min_rate, min_rate); in emc_request_rate()
1150 max_rate = min(req->max_rate, max_rate); in emc_request_rate()
1155 dev_err_ratelimited(emc->dev, "%s: type %u: out of range: %lu %lu\n", in emc_request_rate()
1157 return -ERANGE; in emc_request_rate()
1161 * EMC rate-changes should go via OPP API because it manages voltage in emc_request_rate()
1164 err = dev_pm_opp_set_rate(emc->dev, min_rate); in emc_request_rate()
1168 emc->requested_rate[type].min_rate = new_min_rate; in emc_request_rate()
1169 emc->requested_rate[type].max_rate = new_max_rate; in emc_request_rate()
1174 static int emc_set_min_rate(struct tegra_emc *emc, unsigned long rate, in emc_set_min_rate() argument
1177 struct emc_rate_request *req = &emc->requested_rate[type]; in emc_set_min_rate()
1180 mutex_lock(&emc->rate_lock); in emc_set_min_rate()
1181 ret = emc_request_rate(emc, rate, req->max_rate, type); in emc_set_min_rate()
1182 mutex_unlock(&emc->rate_lock); in emc_set_min_rate()
1187 static int emc_set_max_rate(struct tegra_emc *emc, unsigned long rate, in emc_set_max_rate() argument
1190 struct emc_rate_request *req = &emc->requested_rate[type]; in emc_set_max_rate()
1193 mutex_lock(&emc->rate_lock); in emc_set_max_rate()
1194 ret = emc_request_rate(emc, req->min_rate, rate, type); in emc_set_max_rate()
1195 mutex_unlock(&emc->rate_lock); in emc_set_max_rate()
1204 * to control the EMC frequency. The top-level directory can be found here:
1206 * /sys/kernel/debug/emc
1210 * - available_rates: This file contains a list of valid, space-separated
1211 * EMC frequencies.
1213 * - min_rate: Writing a value to this file sets the given frequency as the
1215 * configured EMC frequency, this will cause the frequency to be
1218 * - max_rate: Similarily to the min_rate file, writing a value to this file
1220 * the value is lower than the currently configured EMC frequency, this
1225 static bool tegra_emc_validate_rate(struct tegra_emc *emc, unsigned long rate) in tegra_emc_validate_rate() argument
1229 for (i = 0; i < emc->num_timings; i++) in tegra_emc_validate_rate()
1230 if (rate == emc->timings[i].rate) in tegra_emc_validate_rate()
1238 struct tegra_emc *emc = s->private; in tegra_emc_debug_available_rates_show() local
1242 for (i = 0; i < emc->num_timings; i++) { in tegra_emc_debug_available_rates_show()
1243 seq_printf(s, "%s%lu", prefix, emc->timings[i].rate); in tegra_emc_debug_available_rates_show()
1256 inode->i_private); in tegra_emc_debug_available_rates_open()
1268 struct tegra_emc *emc = data; in tegra_emc_debug_min_rate_get() local
1270 *rate = emc->debugfs.min_rate; in tegra_emc_debug_min_rate_get()
1277 struct tegra_emc *emc = data; in tegra_emc_debug_min_rate_set() local
1280 if (!tegra_emc_validate_rate(emc, rate)) in tegra_emc_debug_min_rate_set()
1281 return -EINVAL; in tegra_emc_debug_min_rate_set()
1283 err = emc_set_min_rate(emc, rate, EMC_RATE_DEBUG); in tegra_emc_debug_min_rate_set()
1287 emc->debugfs.min_rate = rate; in tegra_emc_debug_min_rate_set()
1298 struct tegra_emc *emc = data; in tegra_emc_debug_max_rate_get() local
1300 *rate = emc->debugfs.max_rate; in tegra_emc_debug_max_rate_get()
1307 struct tegra_emc *emc = data; in tegra_emc_debug_max_rate_set() local
1310 if (!tegra_emc_validate_rate(emc, rate)) in tegra_emc_debug_max_rate_set()
1311 return -EINVAL; in tegra_emc_debug_max_rate_set()
1313 err = emc_set_max_rate(emc, rate, EMC_RATE_DEBUG); in tegra_emc_debug_max_rate_set()
1317 emc->debugfs.max_rate = rate; in tegra_emc_debug_max_rate_set()
1326 static void tegra_emc_debugfs_init(struct tegra_emc *emc) in tegra_emc_debugfs_init() argument
1328 struct device *dev = emc->dev; in tegra_emc_debugfs_init()
1332 emc->debugfs.min_rate = ULONG_MAX; in tegra_emc_debugfs_init()
1333 emc->debugfs.max_rate = 0; in tegra_emc_debugfs_init()
1335 for (i = 0; i < emc->num_timings; i++) { in tegra_emc_debugfs_init()
1336 if (emc->timings[i].rate < emc->debugfs.min_rate) in tegra_emc_debugfs_init()
1337 emc->debugfs.min_rate = emc->timings[i].rate; in tegra_emc_debugfs_init()
1339 if (emc->timings[i].rate > emc->debugfs.max_rate) in tegra_emc_debugfs_init()
1340 emc->debugfs.max_rate = emc->timings[i].rate; in tegra_emc_debugfs_init()
1343 if (!emc->num_timings) { in tegra_emc_debugfs_init()
1344 emc->debugfs.min_rate = clk_get_rate(emc->clk); in tegra_emc_debugfs_init()
1345 emc->debugfs.max_rate = emc->debugfs.min_rate; in tegra_emc_debugfs_init()
1348 err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate, in tegra_emc_debugfs_init()
1349 emc->debugfs.max_rate); in tegra_emc_debugfs_init()
1351 dev_err(dev, "failed to set rate range [%lu-%lu] for %pC\n", in tegra_emc_debugfs_init()
1352 emc->debugfs.min_rate, emc->debugfs.max_rate, in tegra_emc_debugfs_init()
1353 emc->clk); in tegra_emc_debugfs_init()
1356 emc->debugfs.root = debugfs_create_dir("emc", NULL); in tegra_emc_debugfs_init()
1358 debugfs_create_file("available_rates", 0444, emc->debugfs.root, in tegra_emc_debugfs_init()
1359 emc, &tegra_emc_debug_available_rates_fops); in tegra_emc_debugfs_init()
1360 debugfs_create_file("min_rate", 0644, emc->debugfs.root, in tegra_emc_debugfs_init()
1361 emc, &tegra_emc_debug_min_rate_fops); in tegra_emc_debugfs_init()
1362 debugfs_create_file("max_rate", 0644, emc->debugfs.root, in tegra_emc_debugfs_init()
1363 emc, &tegra_emc_debug_max_rate_fops); in tegra_emc_debugfs_init()
1380 list_for_each_entry(node, &provider->nodes, node_list) { in emc_of_icc_xlate_extended()
1381 if (node->id != TEGRA_ICC_EMEM) in emc_of_icc_xlate_extended()
1386 return ERR_PTR(-ENOMEM); in emc_of_icc_xlate_extended()
1392 ndata->tag = TEGRA_MC_ICC_TAG_ISO; in emc_of_icc_xlate_extended()
1393 ndata->node = node; in emc_of_icc_xlate_extended()
1398 return ERR_PTR(-EPROBE_DEFER); in emc_of_icc_xlate_extended()
1403 struct tegra_emc *emc = to_tegra_emc_provider(dst->provider); in emc_icc_set() local
1404 unsigned long long peak_bw = icc_units_to_bps(dst->peak_bw); in emc_icc_set()
1405 unsigned long long avg_bw = icc_units_to_bps(dst->avg_bw); in emc_icc_set()
1412 * Tegra30 EMC runs on a clock rate of SDRAM bus. This means that in emc_icc_set()
1413 * EMC clock rate is twice smaller than the peak data rate because in emc_icc_set()
1414 * data is sampled on both EMC clock edges. in emc_icc_set()
1419 err = emc_set_min_rate(emc, rate, EMC_RATE_ICC); in emc_icc_set()
1426 static int tegra_emc_interconnect_init(struct tegra_emc *emc) in tegra_emc_interconnect_init() argument
1428 const struct tegra_mc_soc *soc = emc->mc->soc; in tegra_emc_interconnect_init()
1432 emc->provider.dev = emc->dev; in tegra_emc_interconnect_init()
1433 emc->provider.set = emc_icc_set; in tegra_emc_interconnect_init()
1434 emc->provider.data = &emc->provider; in tegra_emc_interconnect_init()
1435 emc->provider.aggregate = soc->icc_ops->aggregate; in tegra_emc_interconnect_init()
1436 emc->provider.xlate_extended = emc_of_icc_xlate_extended; in tegra_emc_interconnect_init()
1438 err = icc_provider_add(&emc->provider); in tegra_emc_interconnect_init()
1449 node->name = "External Memory Controller"; in tegra_emc_interconnect_init()
1450 icc_node_add(node, &emc->provider); in tegra_emc_interconnect_init()
1464 node->name = "External Memory (DRAM)"; in tegra_emc_interconnect_init()
1465 icc_node_add(node, &emc->provider); in tegra_emc_interconnect_init()
1470 icc_nodes_remove(&emc->provider); in tegra_emc_interconnect_init()
1472 icc_provider_del(&emc->provider); in tegra_emc_interconnect_init()
1474 dev_err(emc->dev, "failed to initialize ICC: %d\n", err); in tegra_emc_interconnect_init()
1486 struct tegra_emc *emc = data; in devm_tegra_emc_unreg_clk_notifier() local
1488 clk_notifier_unregister(emc->clk, &emc->clk_nb); in devm_tegra_emc_unreg_clk_notifier()
1491 static int tegra_emc_init_clk(struct tegra_emc *emc) in tegra_emc_init_clk() argument
1495 tegra20_clk_set_emc_round_callback(emc_round_rate, emc); in tegra_emc_init_clk()
1497 err = devm_add_action_or_reset(emc->dev, devm_tegra_emc_unset_callback, in tegra_emc_init_clk()
1502 emc->clk = devm_clk_get(emc->dev, NULL); in tegra_emc_init_clk()
1503 if (IS_ERR(emc->clk)) { in tegra_emc_init_clk()
1504 dev_err(emc->dev, "failed to get EMC clock: %pe\n", emc->clk); in tegra_emc_init_clk()
1505 return PTR_ERR(emc->clk); in tegra_emc_init_clk()
1508 err = clk_notifier_register(emc->clk, &emc->clk_nb); in tegra_emc_init_clk()
1510 dev_err(emc->dev, "failed to register clk notifier: %d\n", err); in tegra_emc_init_clk()
1514 err = devm_add_action_or_reset(emc->dev, in tegra_emc_init_clk()
1515 devm_tegra_emc_unreg_clk_notifier, emc); in tegra_emc_init_clk()
1526 struct tegra_emc *emc; in tegra_emc_probe() local
1529 emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL); in tegra_emc_probe()
1530 if (!emc) in tegra_emc_probe()
1531 return -ENOMEM; in tegra_emc_probe()
1533 emc->mc = devm_tegra_memory_controller_get(&pdev->dev); in tegra_emc_probe()
1534 if (IS_ERR(emc->mc)) in tegra_emc_probe()
1535 return PTR_ERR(emc->mc); in tegra_emc_probe()
1537 mutex_init(&emc->rate_lock); in tegra_emc_probe()
1538 emc->clk_nb.notifier_call = emc_clk_change_notify; in tegra_emc_probe()
1539 emc->dev = &pdev->dev; in tegra_emc_probe()
1541 np = emc_find_node_by_ram_code(&pdev->dev); in tegra_emc_probe()
1543 err = emc_load_timings_from_dt(emc, np); in tegra_emc_probe()
1549 emc->regs = devm_platform_ioremap_resource(pdev, 0); in tegra_emc_probe()
1550 if (IS_ERR(emc->regs)) in tegra_emc_probe()
1551 return PTR_ERR(emc->regs); in tegra_emc_probe()
1553 err = emc_setup_hw(emc); in tegra_emc_probe()
1561 emc->irq = err; in tegra_emc_probe()
1563 err = devm_request_irq(&pdev->dev, emc->irq, tegra_emc_isr, 0, in tegra_emc_probe()
1564 dev_name(&pdev->dev), emc); in tegra_emc_probe()
1566 dev_err(&pdev->dev, "failed to request irq: %d\n", err); in tegra_emc_probe()
1570 err = tegra_emc_init_clk(emc); in tegra_emc_probe()
1576 err = devm_tegra_core_dev_init_opp_table(&pdev->dev, &opp_params); in tegra_emc_probe()
1580 platform_set_drvdata(pdev, emc); in tegra_emc_probe()
1581 tegra_emc_rate_requests_init(emc); in tegra_emc_probe()
1582 tegra_emc_debugfs_init(emc); in tegra_emc_probe()
1583 tegra_emc_interconnect_init(emc); in tegra_emc_probe()
1597 struct tegra_emc *emc = dev_get_drvdata(dev); in tegra_emc_suspend() local
1601 err = clk_rate_exclusive_get(emc->clk); in tegra_emc_suspend()
1603 dev_err(emc->dev, "failed to acquire clk: %d\n", err); in tegra_emc_suspend()
1608 if (WARN(emc->bad_state, "hardware in a bad state\n")) in tegra_emc_suspend()
1609 return -EINVAL; in tegra_emc_suspend()
1611 emc->bad_state = true; in tegra_emc_suspend()
1618 struct tegra_emc *emc = dev_get_drvdata(dev); in tegra_emc_resume() local
1620 emc_setup_hw(emc); in tegra_emc_resume()
1621 emc->bad_state = false; in tegra_emc_resume()
1623 clk_rate_exclusive_put(emc->clk); in tegra_emc_resume()
1634 { .compatible = "nvidia,tegra30-emc", },
1642 .name = "tegra30-emc",
1652 MODULE_DESCRIPTION("NVIDIA Tegra30 EMC driver");