17 #define MC_STAT_CONTROL				0x90
18 #define MC_STAT_EMC_CLOCK_LIMIT			0xa0
19 #define MC_STAT_EMC_CLOCKS			0xa4
20 #define MC_STAT_EMC_CONTROL_0			0xa8
21 #define MC_STAT_EMC_CONTROL_1			0xac
22 #define MC_STAT_EMC_COUNT_0			0xb8
23 #define MC_STAT_EMC_COUNT_1			0xbc
31 #define MC_STAT_CONTROL_PRI_EVENT_HP		0
35 #define MC_STAT_CONTROL_FILTER_PRI_DISABLE	0
39 #define MC_STAT_CONTROL_EVENT_QUALIFIED		0
49 #define EMC_GATHER_RST				(0 << 8)
92 		.id = 0x00,
95 		.id = 0x01,
98 		.id = 0x02,
101 		.id = 0x03,
104 		.id = 0x04,
107 		.id = 0x05,
110 		.id = 0x06,
113 		.id = 0x07,
116 		.id = 0x08,
119 		.id = 0x09,
122 		.id = 0x0a,
125 		.id = 0x0b,
128 		.id = 0x0c,
131 		.id = 0x0d,
134 		.id = 0x0e,
137 		.id = 0x0f,
140 		.id = 0x10,
143 		.id = 0x11,
146 		.id = 0x12,
149 		.id = 0x13,
152 		.id = 0x14,
155 		.id = 0x15,
158 		.id = 0x16,
161 		.id = 0x17,
164 		.id = 0x18,
167 		.id = 0x19,
170 		.id = 0x1a,
173 		.id = 0x1b,
176 		.id = 0x1c,
179 		.id = 0x1d,
182 		.id = 0x1e,
185 		.id = 0x1f,
188 		.id = 0x20,
191 		.id = 0x21,
194 		.id = 0x22,
197 		.id = 0x23,
200 		.id = 0x24,
203 		.id = 0x25,
206 		.id = 0x26,
209 		.id = 0x27,
212 		.id = 0x28,
215 		.id = 0x29,
218 		.id = 0x2a,
221 		.id = 0x2b,
224 		.id = 0x2c,
227 		.id = 0x2d,
230 		.id = 0x2e,
233 		.id = 0x2f,
236 		.id = 0x30,
239 		.id = 0x31,
242 		.id = 0x32,
245 		.id = 0x33,
261 	TEGRA20_MC_RESET(AVPC,   0x100, 0x140, 0x104,  0),
262 	TEGRA20_MC_RESET(DC,     0x100, 0x144, 0x104,  1),
263 	TEGRA20_MC_RESET(DCB,    0x100, 0x148, 0x104,  2),
264 	TEGRA20_MC_RESET(EPP,    0x100, 0x14c, 0x104,  3),
265 	TEGRA20_MC_RESET(2D,     0x100, 0x150, 0x104,  4),
266 	TEGRA20_MC_RESET(HC,     0x100, 0x154, 0x104,  5),
267 	TEGRA20_MC_RESET(ISP,    0x100, 0x158, 0x104,  6),
268 	TEGRA20_MC_RESET(MPCORE, 0x100, 0x15c, 0x104,  7),
269 	TEGRA20_MC_RESET(MPEA,   0x100, 0x160, 0x104,  8),
270 	TEGRA20_MC_RESET(MPEB,   0x100, 0x164, 0x104,  9),
271 	TEGRA20_MC_RESET(MPEC,   0x100, 0x168, 0x104, 10),
272 	TEGRA20_MC_RESET(3D,     0x100, 0x16c, 0x104, 11),
273 	TEGRA20_MC_RESET(PPCS,   0x100, 0x170, 0x104, 12),
274 	TEGRA20_MC_RESET(VDE,    0x100, 0x174, 0x104, 13),
275 	TEGRA20_MC_RESET(VI,     0x100, 0x178, 0x104, 14),
291 	return 0;  in tegra20_mc_hotreset_assert()
307 	return 0;  in tegra20_mc_hotreset_deassert()
323 	return 0;  in tegra20_mc_block_dma()
329 	return mc_readl(mc, rst->status) == 0;  in tegra20_mc_dma_idling()
335 	return (mc_readl(mc, rst->reset) & BIT(rst->bit)) == 0;  in tegra20_mc_reset_status()
351 	return 0;  in tegra20_mc_unblock_dma()
370 	return 0;  in tegra20_mc_icc_set()
388 	return 0;  in tegra20_mc_icc_aggreate()
395 	unsigned int i, idx = spec->args[0];  in tegra20_mc_of_icc_xlate_extended()
419 	for (i = 0; i < mc->soc->num_clients; i++) {  in tegra20_mc_of_icc_xlate_extended()
460 	mc_writel(mc, 0x00000000, MC_STAT_CONTROL);  in tegra20_mc_stat_gather()
463 	mc_writel(mc, 0xffffffff, MC_STAT_EMC_CLOCK_LIMIT);  in tegra20_mc_stat_gather()
489 	stat.gather0.client = client0 ? client0->id : 0;  in tegra20_mc_stat_events()
495 	stat.gather1.client = client1 ? client1->id : 0;  in tegra20_mc_stat_events()
517 	for (i = 0; i < mc->soc->num_clients; i += 2) {  in tegra20_mc_collect_stats()
528 				       &stats[i + 0].events,  in tegra20_mc_collect_stats()
533 	for (i = 0; i < mc->soc->num_clients; i++) {  in tegra20_mc_collect_stats()
630 	for (i = 0; i < mc->soc->num_clients; i++) {  in tegra20_mc_stats_show()
679 	return 0;  in tegra20_mc_stats_show()
687 	return 0;  in tegra20_mc_probe()
696 		if (err < 0)  in tegra20_mc_suspend()
700 	return 0;  in tegra20_mc_suspend()
709 		if (err < 0)  in tegra20_mc_resume()
713 	return 0;  in tegra20_mc_resume()
754 			if (value & BIT(0))  in tegra20_mc_handle_irq()
800 	.client_id_mask = 0x3f,