Lines Matching +full:low +full:- +full:power +full:- +full:disable
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
9 #define ITE_DRIVER_NAME "ite-cir"
34 /* hw-specific operation function pointers; most of these must be
47 /* disable rx completely */
56 /* disable tx FIFO space available interrupt */
65 /* disable hardware completely */
66 void (*disable) (struct ite_dev *dev); member
89 /* rx low carrier frequency, in Hz, 0 means no demodulation */
98 /* duty cycle, 0-100 */
114 /* low-speed carrier frequency limits (Hz) */
118 /* high-speed carrier frequency limits (Hz) */
130 * n in RDCR produces a tolerance of +/- n * 6.25% around the center
133 * From two limit frequencies, L (low) and H (high), we can get both the
135 * frequency A = (H - L) / (H + L). We can use this in order to honor the
136 * s_rx_carrier_range() call in ir-core. We'll suppose that any request
170 * Environment Control - Low Pin Count Input / Output
171 * (EC - LPC I/O)
183 #define IT87_BDLR 0x05 /* baud rate divisor low byte register */
190 #define IT87_TLDLIE 0x01 /* transmitter low data interrupt enable */
202 #define IT87_HCFS 0x40 /* high-speed carrier frequency select */
212 * 0x00 -> 1, 0x10 -> 7, 0x20 -> 17,
213 * 0x30 -> 25 */
228 #define IT87_RXFTO 0x80 /* receiver FIFO time-out */
234 #define IT87_II_TXLDL 0x02 /* transmitter low data level */
265 #define IT85_C0BDLR 0x08 /* baud rate divisor low byte register */
271 #define IT85_C0WPS 0x0f /* wakeup power control/status register */
280 * 0x00 -> 1, 0x04 -> 7, 0x08 -> 17,
281 * 0x0c -> 25 */
286 #define IT85_TLDLIE 0x01 /* TX low data level interrupt enable */
292 #define IT85_TLDLI 0x01 /* transmitter low data level interrupt */
329 #define IT85_RXFTO 0x80 /* receiver FIFO time-out */
335 #define IT85_CIRPOSIE 0x01 /* power on/off status interrupt enable */
336 #define IT85_CIRPOIS 0x02 /* power on/off interrupt status */
337 #define IT85_CIRPOII 0x04 /* power on/off interrupt identification */
349 * suggest that it maps the 16 registers of IT8512 onto two 8-register banks,
350 * selectable by a single bank-select bit that's mapped onto both banks. The
353 * reserved high-order bit are placed at the same offset in both banks in
363 /* mapped onto the low bank */
374 #define IT8708_C0BDLR 0x01 /* baud rate divisor low byte register */
384 #define IT8708_C0WPS 0x07 /* wakeup power control/status register */
408 * a specific firmware running on the IT8512's embedded micro-controller.
409 * In addition of the embedded micro-controller, the IT8512 chip contains a
412 * micro-controller. The CIR module is only accessible by the
413 * micro-controller.
415 * The battery-backed SRAM module is accessible by the host CPU and the
416 * micro-controller. So one of the MC's firmware role is to act as a bridge
420 * communication protocol is not, so it was reverse-engineered.