261 	writel_relaxed(bits & ~clr_bits, vfe->base + reg);  in vfe_reg_clr()
268 	writel_relaxed(bits | set_bits, vfe->base + reg);  in vfe_reg_set()
284 	writel_relaxed(BIT(31), vfe->base + VFE_0_IRQ_MASK_0);  in vfe_global_reset()
288 	writel_relaxed(reset_bits, vfe->base + VFE_0_GLOBAL_RESET_CMD);  in vfe_global_reset()
293 	writel_relaxed(VFE_0_BUS_BDG_CMD_HALT_REQ,  in vfe_halt_request()
299 	writel_relaxed(0x0, vfe->base + VFE_0_BUS_BDG_CMD);  in vfe_halt_clear()
386 		writel_relaxed(reg, vfe->base +  in vfe_wm_line_based()
395 		writel_relaxed(reg, vfe->base +  in vfe_wm_line_based()
398 		writel_relaxed(0, vfe->base +  in vfe_wm_line_based()
400 		writel_relaxed(0, vfe->base +  in vfe_wm_line_based()
417 	writel_relaxed(reg,  in vfe_wm_set_framedrop_period()
424 	writel_relaxed(pattern, vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_FRAMEDROP_PATTERN(wm));  in vfe_wm_set_framedrop_pattern()
434 	writel_relaxed(reg, vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG(wm));  in vfe_wm_set_ub_cfg()
442 	writel_relaxed(VFE_0_BUS_CMD_Mx_RLD_CMD(wm), vfe->base + VFE_0_BUS_CMD);  in vfe_bus_reload_wm()
450 	writel_relaxed(addr,  in vfe_wm_set_ping_addr()
456 	writel_relaxed(addr,  in vfe_wm_set_pong_addr()
472 		writel_relaxed(0x101, vfe->base + VFE_0_BUS_CFG);  in vfe_bus_enable_wr_if()
474 		writel_relaxed(0, vfe->base + VFE_0_BUS_CFG);  in vfe_bus_enable_wr_if()
514 	writel_relaxed(VFE_0_BUS_IMAGE_MASTER_n_WR_IRQ_SUBSAMPLE_PATTERN_DEF,  in vfe_wm_set_subsample()
642 	writel_relaxed(val, vfe->base + VFE_0_REALIGN_BUF_CFG);  in vfe_set_realign_cfg()
661 	writel_relaxed(vfe->reg_update, vfe->base + VFE_0_REG_UPDATE);  in vfe_reg_update()
734 	writel_relaxed(VFE_0_DEMUX_CFG_PERIOD, vfe->base + VFE_0_DEMUX_CFG);  in vfe_set_demux_cfg()
737 	writel_relaxed(val, vfe->base + VFE_0_DEMUX_GAIN_0);  in vfe_set_demux_cfg()
740 	writel_relaxed(val, vfe->base + VFE_0_DEMUX_GAIN_1);  in vfe_set_demux_cfg()
762 	writel_relaxed(even_cfg, vfe->base + VFE_0_DEMUX_EVEN_CFG);  in vfe_set_demux_cfg()
763 	writel_relaxed(odd_cfg, vfe->base + VFE_0_DEMUX_ODD_CFG);  in vfe_set_demux_cfg()
774 	writel_relaxed(0x3, vfe->base + VFE_0_SCALE_ENC_Y_CFG);  in vfe_set_scale_cfg()
779 	writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_H_IMAGE_SIZE);  in vfe_set_scale_cfg()
784 	writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_H_PHASE);  in vfe_set_scale_cfg()
789 	writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_V_IMAGE_SIZE);  in vfe_set_scale_cfg()
794 	writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_V_PHASE);  in vfe_set_scale_cfg()
796 	writel_relaxed(0x3, vfe->base + VFE_0_SCALE_ENC_CBCR_CFG);  in vfe_set_scale_cfg()
801 	writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_H_IMAGE_SIZE);  in vfe_set_scale_cfg()
806 	writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_H_PHASE);  in vfe_set_scale_cfg()
813 	writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_V_IMAGE_SIZE);  in vfe_set_scale_cfg()
818 	writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_V_PHASE);  in vfe_set_scale_cfg()
830 	writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_Y_WIDTH);  in vfe_set_crop_cfg()
835 	writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_Y_HEIGHT);  in vfe_set_crop_cfg()
840 	writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_CBCR_WIDTH);  in vfe_set_crop_cfg()
849 	writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_CBCR_HEIGHT);  in vfe_set_crop_cfg()
858 	writel_relaxed(val, vfe->base + VFE_0_CLAMP_ENC_MAX_CFG);  in vfe_set_clamp_cfg()
864 	writel_relaxed(val, vfe->base + VFE_0_CLAMP_ENC_MIN_CFG);  in vfe_set_clamp_cfg()
893 	writel_relaxed(val, vfe->base + VFE_0_CORE_CFG);  in vfe_set_camif_cfg()
897 	writel_relaxed(val, vfe->base + VFE_0_CAMIF_FRAME_CFG);  in vfe_set_camif_cfg()
900 	writel_relaxed(val, vfe->base + VFE_0_CAMIF_WINDOW_WIDTH_CFG);  in vfe_set_camif_cfg()
903 	writel_relaxed(val, vfe->base + VFE_0_CAMIF_WINDOW_HEIGHT_CFG);  in vfe_set_camif_cfg()
906 	writel_relaxed(val, vfe->base + VFE_0_CAMIF_SUBSAMPLE_CFG);  in vfe_set_camif_cfg()
909 	writel_relaxed(val, vfe->base + VFE_0_CAMIF_IRQ_FRAMEDROP_PATTERN);  in vfe_set_camif_cfg()
912 	writel_relaxed(val, vfe->base + VFE_0_CAMIF_IRQ_SUBSAMPLE_PATTERN);  in vfe_set_camif_cfg()
918 	writel_relaxed(val, vfe->base + VFE_0_CAMIF_CFG);  in vfe_set_camif_cfg()
926 	writel_relaxed(cmd, vfe->base + VFE_0_CAMIF_CMD);  in vfe_set_camif_cmd()
936 	writel_relaxed(cmd, vfe->base + VFE_0_CAMIF_CMD);  in vfe_set_camif_cmd()
1033 		writel_relaxed(2 << VFE_0_BUS_IMAGE_MASTER_n_SHIFT(wm),  in vfe_wm_enable()
1036 		writel_relaxed(1 << VFE_0_BUS_IMAGE_MASTER_n_SHIFT(wm),  in vfe_wm_enable()
1050 	writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_0);  in vfe_set_qos()
1051 	writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_1);  in vfe_set_qos()
1052 	writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_2);  in vfe_set_qos()
1053 	writel_relaxed(val3, vfe->base + VFE_0_BUS_BDG_QOS_CFG_3);  in vfe_set_qos()
1054 	writel_relaxed(val4, vfe->base + VFE_0_BUS_BDG_QOS_CFG_4);  in vfe_set_qos()
1055 	writel_relaxed(val4, vfe->base + VFE_0_BUS_BDG_QOS_CFG_5);  in vfe_set_qos()
1056 	writel_relaxed(val4, vfe->base + VFE_0_BUS_BDG_QOS_CFG_6);  in vfe_set_qos()
1057 	writel_relaxed(val7, vfe->base + VFE_0_BUS_BDG_QOS_CFG_7);  in vfe_set_qos()
1065 	writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_0);  in vfe_set_ds()
1066 	writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_1);  in vfe_set_ds()
1067 	writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_2);  in vfe_set_ds()
1068 	writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_3);  in vfe_set_ds()
1069 	writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_4);  in vfe_set_ds()
1070 	writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_5);  in vfe_set_ds()
1071 	writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_6);  in vfe_set_ds()
1072 	writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_7);  in vfe_set_ds()
1073 	writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_8);  in vfe_set_ds()
1074 	writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_9);  in vfe_set_ds()
1075 	writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_10);  in vfe_set_ds()
1076 	writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_11);  in vfe_set_ds()
1077 	writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_12);  in vfe_set_ds()
1078 	writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_13);  in vfe_set_ds()
1079 	writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_14);  in vfe_set_ds()
1080 	writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_15);  in vfe_set_ds()
1081 	writel_relaxed(val16, vfe->base + VFE_0_BUS_BDG_DS_CFG_16);  in vfe_set_ds()
1089 	writel_relaxed(*value0, vfe->base + VFE_0_IRQ_CLEAR_0);  in vfe_isr_read()
1090 	writel_relaxed(*value1, vfe->base + VFE_0_IRQ_CLEAR_1);  in vfe_isr_read()
1094 	writel_relaxed(VFE_0_IRQ_CMD_GLOBAL_CLEAR, vfe->base + VFE_0_IRQ_CMD);  in vfe_isr_read()