Lines Matching +full:output +full:- +full:enable
1 // SPDX-License-Identifier: GPL-2.0
3 * camss-vfe-4-7.c
5 * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module v4.7
7 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
8 * Copyright (C) 2015-2018 Linaro Ltd.
17 #include "camss-vfe.h"
18 #include "camss-vfe-gen1.h"
259 u32 hw_version = readl_relaxed(vfe->base + VFE_0_HW_VERSION); in vfe_hw_version_read()
276 u32 bits = readl_relaxed(vfe->base + reg); in vfe_reg_clr()
278 writel_relaxed(bits & ~clr_bits, vfe->base + reg); in vfe_reg_clr()
283 u32 bits = readl_relaxed(vfe->base + reg); in vfe_reg_set()
285 writel_relaxed(bits | set_bits, vfe->base + reg); in vfe_reg_set()
301 writel_relaxed(BIT(31), vfe->base + VFE_0_IRQ_MASK_0); in vfe_global_reset()
305 writel_relaxed(reset_bits, vfe->base + VFE_0_GLOBAL_RESET_CMD); in vfe_global_reset()
311 vfe->base + VFE_0_BUS_BDG_CMD); in vfe_halt_request()
316 writel_relaxed(0x0, vfe->base + VFE_0_BUS_BDG_CMD); in vfe_halt_clear()
319 static void vfe_wm_enable(struct vfe_device *vfe, u8 wm, u8 enable) in vfe_wm_enable() argument
321 if (enable) in vfe_wm_enable()
329 static void vfe_wm_frame_based(struct vfe_device *vfe, u8 wm, u8 enable) in vfe_wm_frame_based() argument
331 if (enable) in vfe_wm_frame_based()
339 #define CALC_WORD(width, M, N) (((width) * (M) + (N) - 1) / (N))
371 switch (pix->pixelformat) { in vfe_get_wm_sizes()
374 *width = pix->width; in vfe_get_wm_sizes()
375 *height = pix->height; in vfe_get_wm_sizes()
376 *bytesperline = pix->plane_fmt[0].bytesperline; in vfe_get_wm_sizes()
382 *width = pix->width; in vfe_get_wm_sizes()
383 *height = pix->height; in vfe_get_wm_sizes()
384 *bytesperline = pix->plane_fmt[0].bytesperline; in vfe_get_wm_sizes()
390 *width = pix->width; in vfe_get_wm_sizes()
391 *height = pix->height; in vfe_get_wm_sizes()
392 *bytesperline = pix->plane_fmt[plane].bytesperline; in vfe_get_wm_sizes()
400 u8 plane, u32 enable) in vfe_wm_line_based() argument
404 if (enable) { in vfe_wm_line_based()
409 wpl = vfe_word_per_line_by_pixel(pix->pixelformat, width); in vfe_wm_line_based()
411 reg = height - 1; in vfe_wm_line_based()
412 reg |= ((wpl + 3) / 4 - 1) << 16; in vfe_wm_line_based()
414 writel_relaxed(reg, vfe->base + in vfe_wm_line_based()
420 reg |= (height - 1) << 2; in vfe_wm_line_based()
423 writel_relaxed(reg, vfe->base + in vfe_wm_line_based()
426 writel_relaxed(0, vfe->base + in vfe_wm_line_based()
428 writel_relaxed(0, vfe->base + in vfe_wm_line_based()
437 reg = readl_relaxed(vfe->base + in vfe_wm_set_framedrop_period()
446 vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(wm)); in vfe_wm_set_framedrop_period()
453 vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_FRAMEDROP_PATTERN(wm)); in vfe_wm_set_framedrop_pattern()
463 writel_relaxed(reg, vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG(wm)); in vfe_wm_set_ub_cfg()
471 writel_relaxed(VFE_0_BUS_CMD_Mx_RLD_CMD(wm), vfe->base + VFE_0_BUS_CMD); in vfe_bus_reload_wm()
480 vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_PING_ADDR(wm)); in vfe_wm_set_ping_addr()
486 vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_PONG_ADDR(wm)); in vfe_wm_set_pong_addr()
493 reg = readl_relaxed(vfe->base + VFE_0_BUS_PING_PONG_STATUS); in vfe_wm_get_ping_pong_status()
498 static void vfe_bus_enable_wr_if(struct vfe_device *vfe, u8 enable) in vfe_bus_enable_wr_if() argument
500 if (enable) in vfe_bus_enable_wr_if()
501 writel_relaxed(0x101, vfe->base + VFE_0_BUS_CFG); in vfe_bus_enable_wr_if()
503 writel_relaxed(0, vfe->base + VFE_0_BUS_CFG); in vfe_bus_enable_wr_if()
544 vfe->base + in vfe_wm_set_subsample()
578 static void vfe_set_xbar_cfg(struct vfe_device *vfe, struct vfe_output *output, in vfe_set_xbar_cfg() argument
579 u8 enable) in vfe_set_xbar_cfg() argument
581 struct vfe_line *line = container_of(output, struct vfe_line, output); in vfe_set_xbar_cfg()
582 u32 p = line->video_out.active_fmt.fmt.pix_mp.pixelformat; in vfe_set_xbar_cfg()
593 if (output->wm_idx[0] % 2 == 1) in vfe_set_xbar_cfg()
596 if (enable) in vfe_set_xbar_cfg()
598 VFE_0_BUS_XBAR_CFG_x(output->wm_idx[0]), in vfe_set_xbar_cfg()
602 VFE_0_BUS_XBAR_CFG_x(output->wm_idx[0]), in vfe_set_xbar_cfg()
609 if (output->wm_idx[1] % 2 == 1) in vfe_set_xbar_cfg()
612 if (enable) in vfe_set_xbar_cfg()
614 VFE_0_BUS_XBAR_CFG_x(output->wm_idx[1]), in vfe_set_xbar_cfg()
618 VFE_0_BUS_XBAR_CFG_x(output->wm_idx[1]), in vfe_set_xbar_cfg()
631 if (output->wm_idx[0] % 2 == 1) in vfe_set_xbar_cfg()
634 if (enable) in vfe_set_xbar_cfg()
636 VFE_0_BUS_XBAR_CFG_x(output->wm_idx[0]), in vfe_set_xbar_cfg()
640 VFE_0_BUS_XBAR_CFG_x(output->wm_idx[0]), in vfe_set_xbar_cfg()
649 u8 enable) in vfe_set_realign_cfg() argument
651 u32 p = line->video_out.active_fmt.fmt.pix_mp.pixelformat; in vfe_set_realign_cfg()
658 if (enable) { in vfe_set_realign_cfg()
672 writel_relaxed(val, vfe->base + VFE_0_REALIGN_BUF_CFG); in vfe_set_realign_cfg()
686 vfe->reg_update |= VFE_0_REG_UPDATE_line_n(line_id); in vfe_reg_update()
690 writel_relaxed(vfe->reg_update, vfe->base + VFE_0_REG_UPDATE); in vfe_reg_update()
699 vfe->reg_update &= ~VFE_0_REG_UPDATE_line_n(line_id); in vfe_reg_update_clear()
703 enum vfe_line_id line_id, u8 enable) in vfe_enable_irq_wm_line() argument
710 if (enable) { in vfe_enable_irq_wm_line()
720 enum vfe_line_id line_id, u8 enable) in vfe_enable_irq_pix_line() argument
722 struct vfe_output *output = &vfe->line[line_id].output; in vfe_enable_irq_pix_line() local
733 for (i = 0; i < output->wm_num; i++) { in vfe_enable_irq_pix_line()
735 output->wm_idx[i]); in vfe_enable_irq_pix_line()
736 comp_mask |= (1 << output->wm_idx[i]) << comp * 8; in vfe_enable_irq_pix_line()
739 if (enable) { in vfe_enable_irq_pix_line()
764 writel_relaxed(VFE_0_DEMUX_CFG_PERIOD, vfe->base + VFE_0_DEMUX_CFG); in vfe_set_demux_cfg()
767 writel_relaxed(val, vfe->base + VFE_0_DEMUX_GAIN_0); in vfe_set_demux_cfg()
770 writel_relaxed(val, vfe->base + VFE_0_DEMUX_GAIN_1); in vfe_set_demux_cfg()
772 switch (line->fmt[MSM_VFE_PAD_SINK].code) { in vfe_set_demux_cfg()
792 writel_relaxed(even_cfg, vfe->base + VFE_0_DEMUX_EVEN_CFG); in vfe_set_demux_cfg()
793 writel_relaxed(odd_cfg, vfe->base + VFE_0_DEMUX_ODD_CFG); in vfe_set_demux_cfg()
798 u32 p = line->video_out.active_fmt.fmt.pix_mp.pixelformat; in vfe_set_scale_cfg()
800 u16 input, output; in vfe_set_scale_cfg() local
804 writel_relaxed(0x3, vfe->base + VFE_0_SCALE_ENC_Y_CFG); in vfe_set_scale_cfg()
806 input = line->fmt[MSM_VFE_PAD_SINK].width - 1; in vfe_set_scale_cfg()
807 output = line->compose.width - 1; in vfe_set_scale_cfg()
808 reg = (output << 16) | input; in vfe_set_scale_cfg()
809 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_H_IMAGE_SIZE); in vfe_set_scale_cfg()
811 interp_reso = vfe_calc_interp_reso(input, output); in vfe_set_scale_cfg()
812 phase_mult = input * (1 << (14 + interp_reso)) / output; in vfe_set_scale_cfg()
814 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_H_PHASE); in vfe_set_scale_cfg()
816 input = line->fmt[MSM_VFE_PAD_SINK].height - 1; in vfe_set_scale_cfg()
817 output = line->compose.height - 1; in vfe_set_scale_cfg()
818 reg = (output << 16) | input; in vfe_set_scale_cfg()
819 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_V_IMAGE_SIZE); in vfe_set_scale_cfg()
821 interp_reso = vfe_calc_interp_reso(input, output); in vfe_set_scale_cfg()
822 phase_mult = input * (1 << (14 + interp_reso)) / output; in vfe_set_scale_cfg()
824 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_V_PHASE); in vfe_set_scale_cfg()
826 writel_relaxed(0x3, vfe->base + VFE_0_SCALE_ENC_CBCR_CFG); in vfe_set_scale_cfg()
828 input = line->fmt[MSM_VFE_PAD_SINK].width - 1; in vfe_set_scale_cfg()
829 output = line->compose.width / 2 - 1; in vfe_set_scale_cfg()
830 reg = (output << 16) | input; in vfe_set_scale_cfg()
831 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_H_IMAGE_SIZE); in vfe_set_scale_cfg()
833 interp_reso = vfe_calc_interp_reso(input, output); in vfe_set_scale_cfg()
834 phase_mult = input * (1 << (14 + interp_reso)) / output; in vfe_set_scale_cfg()
836 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_H_PHASE); in vfe_set_scale_cfg()
838 input = line->fmt[MSM_VFE_PAD_SINK].height - 1; in vfe_set_scale_cfg()
839 output = line->compose.height - 1; in vfe_set_scale_cfg()
841 output = line->compose.height / 2 - 1; in vfe_set_scale_cfg()
842 reg = (output << 16) | input; in vfe_set_scale_cfg()
843 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_V_IMAGE_SIZE); in vfe_set_scale_cfg()
845 interp_reso = vfe_calc_interp_reso(input, output); in vfe_set_scale_cfg()
846 phase_mult = input * (1 << (14 + interp_reso)) / output; in vfe_set_scale_cfg()
848 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_V_PHASE); in vfe_set_scale_cfg()
853 u32 p = line->video_out.active_fmt.fmt.pix_mp.pixelformat; in vfe_set_crop_cfg()
857 first = line->crop.left; in vfe_set_crop_cfg()
858 last = line->crop.left + line->crop.width - 1; in vfe_set_crop_cfg()
860 writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_Y_WIDTH); in vfe_set_crop_cfg()
862 first = line->crop.top; in vfe_set_crop_cfg()
863 last = line->crop.top + line->crop.height - 1; in vfe_set_crop_cfg()
865 writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_Y_HEIGHT); in vfe_set_crop_cfg()
867 first = line->crop.left / 2; in vfe_set_crop_cfg()
868 last = line->crop.left / 2 + line->crop.width / 2 - 1; in vfe_set_crop_cfg()
870 writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_CBCR_WIDTH); in vfe_set_crop_cfg()
872 first = line->crop.top; in vfe_set_crop_cfg()
873 last = line->crop.top + line->crop.height - 1; in vfe_set_crop_cfg()
875 first = line->crop.top / 2; in vfe_set_crop_cfg()
876 last = line->crop.top / 2 + line->crop.height / 2 - 1; in vfe_set_crop_cfg()
879 writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_CBCR_HEIGHT); in vfe_set_crop_cfg()
888 writel_relaxed(val, vfe->base + VFE_0_CLAMP_ENC_MAX_CFG); in vfe_set_clamp_cfg()
894 writel_relaxed(val, vfe->base + VFE_0_CLAMP_ENC_MIN_CFG); in vfe_set_clamp_cfg()
902 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_0); in vfe_set_qos()
903 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_1); in vfe_set_qos()
904 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_2); in vfe_set_qos()
905 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_3); in vfe_set_qos()
906 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_4); in vfe_set_qos()
907 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_5); in vfe_set_qos()
908 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_6); in vfe_set_qos()
909 writel_relaxed(val7, vfe->base + VFE_0_BUS_BDG_QOS_CFG_7); in vfe_set_qos()
917 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_0); in vfe_set_ds()
918 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_1); in vfe_set_ds()
919 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_2); in vfe_set_ds()
920 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_3); in vfe_set_ds()
921 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_4); in vfe_set_ds()
922 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_5); in vfe_set_ds()
923 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_6); in vfe_set_ds()
924 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_7); in vfe_set_ds()
925 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_8); in vfe_set_ds()
926 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_9); in vfe_set_ds()
927 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_10); in vfe_set_ds()
928 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_11); in vfe_set_ds()
929 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_12); in vfe_set_ds()
930 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_13); in vfe_set_ds()
931 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_14); in vfe_set_ds()
932 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_15); in vfe_set_ds()
933 writel_relaxed(val16, vfe->base + VFE_0_BUS_BDG_DS_CFG_16); in vfe_set_ds()
936 static void vfe_set_cgc_override(struct vfe_device *vfe, u8 wm, u8 enable) in vfe_set_cgc_override() argument
945 switch (line->fmt[MSM_VFE_PAD_SINK].code) { in vfe_set_camif_cfg()
962 writel_relaxed(val, vfe->base + VFE_0_CORE_CFG); in vfe_set_camif_cfg()
964 val = line->fmt[MSM_VFE_PAD_SINK].width * 2 - 1; in vfe_set_camif_cfg()
965 val |= (line->fmt[MSM_VFE_PAD_SINK].height - 1) << 16; in vfe_set_camif_cfg()
966 writel_relaxed(val, vfe->base + VFE_0_CAMIF_FRAME_CFG); in vfe_set_camif_cfg()
968 val = line->fmt[MSM_VFE_PAD_SINK].width * 2 - 1; in vfe_set_camif_cfg()
969 writel_relaxed(val, vfe->base + VFE_0_CAMIF_WINDOW_WIDTH_CFG); in vfe_set_camif_cfg()
971 val = line->fmt[MSM_VFE_PAD_SINK].height - 1; in vfe_set_camif_cfg()
972 writel_relaxed(val, vfe->base + VFE_0_CAMIF_WINDOW_HEIGHT_CFG); in vfe_set_camif_cfg()
975 writel_relaxed(val, vfe->base + VFE_0_CAMIF_SUBSAMPLE_CFG); in vfe_set_camif_cfg()
978 writel_relaxed(val, vfe->base + VFE_0_CAMIF_IRQ_FRAMEDROP_PATTERN); in vfe_set_camif_cfg()
981 writel_relaxed(val, vfe->base + VFE_0_CAMIF_IRQ_SUBSAMPLE_PATTERN); in vfe_set_camif_cfg()
987 writel_relaxed(val, vfe->base + VFE_0_CAMIF_CFG); in vfe_set_camif_cfg()
990 static void vfe_set_camif_cmd(struct vfe_device *vfe, u8 enable) in vfe_set_camif_cmd() argument
995 writel_relaxed(cmd, vfe->base + VFE_0_CAMIF_CMD); in vfe_set_camif_cmd()
1000 if (enable) in vfe_set_camif_cmd()
1005 writel_relaxed(cmd, vfe->base + VFE_0_CAMIF_CMD); in vfe_set_camif_cmd()
1008 static void vfe_set_module_cfg(struct vfe_device *vfe, u8 enable) in vfe_set_module_cfg() argument
1015 if (enable) { in vfe_set_module_cfg()
1029 ret = readl_poll_timeout(vfe->base + VFE_0_CAMIF_STATUS, in vfe_camif_wait_for_stop()
1043 * vfe_isr - VFE module interrupt handler
1055 vfe->ops->isr_read(vfe, &value0, &value1); in vfe_isr()
1057 dev_dbg(vfe->camss->dev, "VFE: status0 = 0x%08x, status1 = 0x%08x\n", in vfe_isr()
1061 vfe->isr_ops.reset_ack(vfe); in vfe_isr()
1064 vfe->ops->violation_read(vfe); in vfe_isr()
1067 vfe->isr_ops.halt_ack(vfe); in vfe_isr()
1069 for (i = VFE_LINE_RDI0; i < vfe->line_num; i++) in vfe_isr()
1071 vfe->isr_ops.reg_update(vfe, i); in vfe_isr()
1074 vfe->isr_ops.sof(vfe, VFE_LINE_PIX); in vfe_isr()
1078 vfe->isr_ops.sof(vfe, i); in vfe_isr()
1082 vfe->isr_ops.comp_done(vfe, i); in vfe_isr()
1083 for (j = 0; j < ARRAY_SIZE(vfe->wm_output_map); j++) in vfe_isr()
1084 if (vfe->wm_output_map[j] == VFE_LINE_PIX) in vfe_isr()
1090 vfe->isr_ops.wm_done(vfe, i); in vfe_isr()
1097 *value0 = readl_relaxed(vfe->base + VFE_0_IRQ_STATUS_0); in vfe_isr_read()
1098 *value1 = readl_relaxed(vfe->base + VFE_0_IRQ_STATUS_1); in vfe_isr_read()
1100 writel_relaxed(*value0, vfe->base + VFE_0_IRQ_CLEAR_0); in vfe_isr_read()
1101 writel_relaxed(*value1, vfe->base + VFE_0_IRQ_CLEAR_1); in vfe_isr_read()
1105 writel_relaxed(VFE_0_IRQ_CMD_GLOBAL_CLEAR, vfe->base + VFE_0_IRQ_CMD); in vfe_isr_read()
1109 * vfe_pm_domain_off - Disable power domains specific to this VFE.
1119 camss = vfe->camss; in vfe_pm_domain_off()
1121 device_link_del(camss->genpd_link[vfe->id]); in vfe_pm_domain_off()
1125 * vfe_pm_domain_on - Enable power domains specific to this VFE.
1130 struct camss *camss = vfe->camss; in vfe_pm_domain_on()
1131 enum vfe_line_id id = vfe->id; in vfe_pm_domain_on()
1133 camss->genpd_link[id] = device_link_add(camss->dev, camss->genpd[id], DL_FLAG_STATELESS | in vfe_pm_domain_on()
1136 if (!camss->genpd_link[id]) { in vfe_pm_domain_on()
1137 dev_err(vfe->camss->dev, "Failed to add VFE#%d to power domain\n", id); in vfe_pm_domain_on()
1138 return -EINVAL; in vfe_pm_domain_on()
1146 u32 violation = readl_relaxed(vfe->base + VFE_0_VIOLATION_STATUS); in vfe_violation_read()
1190 vfe->isr_ops = vfe_isr_ops_gen1; in vfe_subdev_init()
1191 vfe->ops_gen1 = &vfe_ops_gen1_4_7; in vfe_subdev_init()
1192 vfe->video_ops = vfe_video_ops_gen1; in vfe_subdev_init()
1194 vfe->line_num = VFE_LINE_NUM_GEN1; in vfe_subdev_init()