Lines Matching +full:output +full:- +full:enable
1 // SPDX-License-Identifier: GPL-2.0
3 * camss-vfe-4-1.c
5 * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module v4.1
7 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
8 * Copyright (C) 2015-2018 Linaro Ltd.
16 #include "camss-vfe.h"
17 #include "camss-vfe-gen1.h"
215 u32 hw_version = readl_relaxed(vfe->base + VFE_0_HW_VERSION); in vfe_hw_version_read()
230 u32 bits = readl_relaxed(vfe->base + reg); in vfe_reg_clr()
232 writel_relaxed(bits & ~clr_bits, vfe->base + reg); in vfe_reg_clr()
237 u32 bits = readl_relaxed(vfe->base + reg); in vfe_reg_set()
239 writel_relaxed(bits | set_bits, vfe->base + reg); in vfe_reg_set()
254 writel_relaxed(reset_bits, vfe->base + VFE_0_GLOBAL_RESET_CMD); in vfe_global_reset()
260 vfe->base + VFE_0_BUS_BDG_CMD); in vfe_halt_request()
265 writel_relaxed(0x0, vfe->base + VFE_0_BUS_BDG_CMD); in vfe_halt_clear()
268 static void vfe_wm_enable(struct vfe_device *vfe, u8 wm, u8 enable) in vfe_wm_enable() argument
270 if (enable) in vfe_wm_enable()
278 static void vfe_wm_frame_based(struct vfe_device *vfe, u8 wm, u8 enable) in vfe_wm_frame_based() argument
280 if (enable) in vfe_wm_frame_based()
291 switch (pix->pixelformat) { in vfe_get_wm_sizes()
294 *width = pix->width; in vfe_get_wm_sizes()
295 *height = pix->height; in vfe_get_wm_sizes()
296 *bytesperline = pix->plane_fmt[0].bytesperline; in vfe_get_wm_sizes()
302 *width = pix->width; in vfe_get_wm_sizes()
303 *height = pix->height; in vfe_get_wm_sizes()
304 *bytesperline = pix->plane_fmt[0].bytesperline; in vfe_get_wm_sizes()
311 u8 plane, u32 enable) in vfe_wm_line_based() argument
315 if (enable) { in vfe_wm_line_based()
320 wpl = vfe_word_per_line(pix->pixelformat, width); in vfe_wm_line_based()
322 reg = height - 1; in vfe_wm_line_based()
323 reg |= ((wpl + 1) / 2 - 1) << 16; in vfe_wm_line_based()
325 writel_relaxed(reg, vfe->base + in vfe_wm_line_based()
328 wpl = vfe_word_per_line(pix->pixelformat, bytesperline); in vfe_wm_line_based()
331 reg |= (height - 1) << 4; in vfe_wm_line_based()
334 writel_relaxed(reg, vfe->base + in vfe_wm_line_based()
337 writel_relaxed(0, vfe->base + in vfe_wm_line_based()
339 writel_relaxed(0, vfe->base + in vfe_wm_line_based()
348 reg = readl_relaxed(vfe->base + in vfe_wm_set_framedrop_period()
357 vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(wm)); in vfe_wm_set_framedrop_period()
364 vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_FRAMEDROP_PATTERN(wm)); in vfe_wm_set_framedrop_pattern()
374 writel_relaxed(reg, vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG(wm)); in vfe_wm_set_ub_cfg()
380 writel_relaxed(VFE_0_BUS_CMD_Mx_RLD_CMD(wm), vfe->base + VFE_0_BUS_CMD); in vfe_bus_reload_wm()
387 vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_PING_ADDR(wm)); in vfe_wm_set_ping_addr()
393 vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_PONG_ADDR(wm)); in vfe_wm_set_pong_addr()
400 reg = readl_relaxed(vfe->base + VFE_0_BUS_PING_PONG_STATUS); in vfe_wm_get_ping_pong_status()
405 static void vfe_bus_enable_wr_if(struct vfe_device *vfe, u8 enable) in vfe_bus_enable_wr_if() argument
407 if (enable) in vfe_bus_enable_wr_if()
408 writel_relaxed(0x10000009, vfe->base + VFE_0_BUS_CFG); in vfe_bus_enable_wr_if()
410 writel_relaxed(0, vfe->base + VFE_0_BUS_CFG); in vfe_bus_enable_wr_if()
452 vfe->base + in vfe_wm_set_subsample()
489 static void vfe_set_xbar_cfg(struct vfe_device *vfe, struct vfe_output *output, in vfe_set_xbar_cfg() argument
490 u8 enable) in vfe_set_xbar_cfg() argument
492 struct vfe_line *line = container_of(output, struct vfe_line, output); in vfe_set_xbar_cfg()
493 u32 p = line->video_out.active_fmt.fmt.pix_mp.pixelformat; in vfe_set_xbar_cfg()
497 for (i = 0; i < output->wm_num; i++) { in vfe_set_xbar_cfg()
506 /* On current devices output->wm_num is always <= 2 */ in vfe_set_xbar_cfg()
510 if (output->wm_idx[i] % 2 == 1) in vfe_set_xbar_cfg()
513 if (enable) in vfe_set_xbar_cfg()
515 VFE_0_BUS_XBAR_CFG_x(output->wm_idx[i]), in vfe_set_xbar_cfg()
519 VFE_0_BUS_XBAR_CFG_x(output->wm_idx[i]), in vfe_set_xbar_cfg()
525 u8 enable) in vfe_set_realign_cfg() argument
540 vfe->reg_update |= VFE_0_REG_UPDATE_line_n(line_id); in vfe_reg_update()
542 writel_relaxed(vfe->reg_update, vfe->base + VFE_0_REG_UPDATE); in vfe_reg_update()
549 vfe->reg_update &= ~VFE_0_REG_UPDATE_line_n(line_id); in vfe_reg_update_clear()
553 enum vfe_line_id line_id, u8 enable) in vfe_enable_irq_wm_line() argument
560 if (enable) { in vfe_enable_irq_wm_line()
570 enum vfe_line_id line_id, u8 enable) in vfe_enable_irq_pix_line() argument
572 struct vfe_output *output = &vfe->line[line_id].output; in vfe_enable_irq_pix_line() local
583 for (i = 0; i < output->wm_num; i++) { in vfe_enable_irq_pix_line()
585 output->wm_idx[i]); in vfe_enable_irq_pix_line()
586 comp_mask |= (1 << output->wm_idx[i]) << comp * 8; in vfe_enable_irq_pix_line()
589 if (enable) { in vfe_enable_irq_pix_line()
614 writel_relaxed(VFE_0_DEMUX_CFG_PERIOD, vfe->base + VFE_0_DEMUX_CFG); in vfe_set_demux_cfg()
617 writel_relaxed(val, vfe->base + VFE_0_DEMUX_GAIN_0); in vfe_set_demux_cfg()
620 writel_relaxed(val, vfe->base + VFE_0_DEMUX_GAIN_1); in vfe_set_demux_cfg()
622 switch (line->fmt[MSM_VFE_PAD_SINK].code) { in vfe_set_demux_cfg()
642 writel_relaxed(even_cfg, vfe->base + VFE_0_DEMUX_EVEN_CFG); in vfe_set_demux_cfg()
643 writel_relaxed(odd_cfg, vfe->base + VFE_0_DEMUX_ODD_CFG); in vfe_set_demux_cfg()
648 u32 p = line->video_out.active_fmt.fmt.pix_mp.pixelformat; in vfe_set_scale_cfg()
650 u16 input, output; in vfe_set_scale_cfg() local
654 writel_relaxed(0x3, vfe->base + VFE_0_SCALE_ENC_Y_CFG); in vfe_set_scale_cfg()
656 input = line->fmt[MSM_VFE_PAD_SINK].width; in vfe_set_scale_cfg()
657 output = line->compose.width; in vfe_set_scale_cfg()
658 reg = (output << 16) | input; in vfe_set_scale_cfg()
659 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_H_IMAGE_SIZE); in vfe_set_scale_cfg()
661 interp_reso = vfe_calc_interp_reso(input, output); in vfe_set_scale_cfg()
662 phase_mult = input * (1 << (13 + interp_reso)) / output; in vfe_set_scale_cfg()
664 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_H_PHASE); in vfe_set_scale_cfg()
666 input = line->fmt[MSM_VFE_PAD_SINK].height; in vfe_set_scale_cfg()
667 output = line->compose.height; in vfe_set_scale_cfg()
668 reg = (output << 16) | input; in vfe_set_scale_cfg()
669 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_V_IMAGE_SIZE); in vfe_set_scale_cfg()
671 interp_reso = vfe_calc_interp_reso(input, output); in vfe_set_scale_cfg()
672 phase_mult = input * (1 << (13 + interp_reso)) / output; in vfe_set_scale_cfg()
674 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_V_PHASE); in vfe_set_scale_cfg()
676 writel_relaxed(0x3, vfe->base + VFE_0_SCALE_ENC_CBCR_CFG); in vfe_set_scale_cfg()
678 input = line->fmt[MSM_VFE_PAD_SINK].width; in vfe_set_scale_cfg()
679 output = line->compose.width / 2; in vfe_set_scale_cfg()
680 reg = (output << 16) | input; in vfe_set_scale_cfg()
681 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_H_IMAGE_SIZE); in vfe_set_scale_cfg()
683 interp_reso = vfe_calc_interp_reso(input, output); in vfe_set_scale_cfg()
684 phase_mult = input * (1 << (13 + interp_reso)) / output; in vfe_set_scale_cfg()
686 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_H_PHASE); in vfe_set_scale_cfg()
688 input = line->fmt[MSM_VFE_PAD_SINK].height; in vfe_set_scale_cfg()
689 output = line->compose.height; in vfe_set_scale_cfg()
691 output = line->compose.height / 2; in vfe_set_scale_cfg()
692 reg = (output << 16) | input; in vfe_set_scale_cfg()
693 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_V_IMAGE_SIZE); in vfe_set_scale_cfg()
695 interp_reso = vfe_calc_interp_reso(input, output); in vfe_set_scale_cfg()
696 phase_mult = input * (1 << (13 + interp_reso)) / output; in vfe_set_scale_cfg()
698 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_V_PHASE); in vfe_set_scale_cfg()
703 u32 p = line->video_out.active_fmt.fmt.pix_mp.pixelformat; in vfe_set_crop_cfg()
707 first = line->crop.left; in vfe_set_crop_cfg()
708 last = line->crop.left + line->crop.width - 1; in vfe_set_crop_cfg()
710 writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_Y_WIDTH); in vfe_set_crop_cfg()
712 first = line->crop.top; in vfe_set_crop_cfg()
713 last = line->crop.top + line->crop.height - 1; in vfe_set_crop_cfg()
715 writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_Y_HEIGHT); in vfe_set_crop_cfg()
717 first = line->crop.left / 2; in vfe_set_crop_cfg()
718 last = line->crop.left / 2 + line->crop.width / 2 - 1; in vfe_set_crop_cfg()
720 writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_CBCR_WIDTH); in vfe_set_crop_cfg()
722 first = line->crop.top; in vfe_set_crop_cfg()
723 last = line->crop.top + line->crop.height - 1; in vfe_set_crop_cfg()
725 first = line->crop.top / 2; in vfe_set_crop_cfg()
726 last = line->crop.top / 2 + line->crop.height / 2 - 1; in vfe_set_crop_cfg()
729 writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_CBCR_HEIGHT); in vfe_set_crop_cfg()
738 writel_relaxed(val, vfe->base + VFE_0_CLAMP_ENC_MAX_CFG); in vfe_set_clamp_cfg()
744 writel_relaxed(val, vfe->base + VFE_0_CLAMP_ENC_MIN_CFG); in vfe_set_clamp_cfg()
752 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_0); in vfe_set_qos()
753 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_1); in vfe_set_qos()
754 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_2); in vfe_set_qos()
755 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_3); in vfe_set_qos()
756 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_4); in vfe_set_qos()
757 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_5); in vfe_set_qos()
758 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_6); in vfe_set_qos()
759 writel_relaxed(val7, vfe->base + VFE_0_BUS_BDG_QOS_CFG_7); in vfe_set_qos()
767 static void vfe_set_cgc_override(struct vfe_device *vfe, u8 wm, u8 enable) in vfe_set_cgc_override() argument
771 if (enable) in vfe_set_cgc_override()
783 switch (line->fmt[MSM_VFE_PAD_SINK].code) { in vfe_set_camif_cfg()
799 writel_relaxed(val, vfe->base + VFE_0_CORE_CFG); in vfe_set_camif_cfg()
801 val = line->fmt[MSM_VFE_PAD_SINK].width * 2; in vfe_set_camif_cfg()
802 val |= line->fmt[MSM_VFE_PAD_SINK].height << 16; in vfe_set_camif_cfg()
803 writel_relaxed(val, vfe->base + VFE_0_CAMIF_FRAME_CFG); in vfe_set_camif_cfg()
805 val = line->fmt[MSM_VFE_PAD_SINK].width * 2 - 1; in vfe_set_camif_cfg()
806 writel_relaxed(val, vfe->base + VFE_0_CAMIF_WINDOW_WIDTH_CFG); in vfe_set_camif_cfg()
808 val = line->fmt[MSM_VFE_PAD_SINK].height - 1; in vfe_set_camif_cfg()
809 writel_relaxed(val, vfe->base + VFE_0_CAMIF_WINDOW_HEIGHT_CFG); in vfe_set_camif_cfg()
812 writel_relaxed(val, vfe->base + VFE_0_CAMIF_SUBSAMPLE_CFG_0); in vfe_set_camif_cfg()
815 writel_relaxed(val, vfe->base + VFE_0_CAMIF_IRQ_SUBSAMPLE_PATTERN); in vfe_set_camif_cfg()
821 writel_relaxed(val, vfe->base + VFE_0_CAMIF_CFG); in vfe_set_camif_cfg()
824 static void vfe_set_camif_cmd(struct vfe_device *vfe, u8 enable) in vfe_set_camif_cmd() argument
829 writel_relaxed(cmd, vfe->base + VFE_0_CAMIF_CMD); in vfe_set_camif_cmd()
832 if (enable) in vfe_set_camif_cmd()
837 writel_relaxed(cmd, vfe->base + VFE_0_CAMIF_CMD); in vfe_set_camif_cmd()
840 static void vfe_set_module_cfg(struct vfe_device *vfe, u8 enable) in vfe_set_module_cfg() argument
847 if (enable) in vfe_set_module_cfg()
848 writel_relaxed(val, vfe->base + VFE_0_MODULE_CFG); in vfe_set_module_cfg()
850 writel_relaxed(0x0, vfe->base + VFE_0_MODULE_CFG); in vfe_set_module_cfg()
858 ret = readl_poll_timeout(vfe->base + VFE_0_CAMIF_STATUS, in vfe_camif_wait_for_stop()
871 *value0 = readl_relaxed(vfe->base + VFE_0_IRQ_STATUS_0); in vfe_isr_read()
872 *value1 = readl_relaxed(vfe->base + VFE_0_IRQ_STATUS_1); in vfe_isr_read()
874 writel_relaxed(*value0, vfe->base + VFE_0_IRQ_CLEAR_0); in vfe_isr_read()
875 writel_relaxed(*value1, vfe->base + VFE_0_IRQ_CLEAR_1); in vfe_isr_read()
878 writel_relaxed(VFE_0_IRQ_CMD_GLOBAL_CLEAR, vfe->base + VFE_0_IRQ_CMD); in vfe_isr_read()
883 u32 violation = readl_relaxed(vfe->base + VFE_0_VIOLATION_STATUS); in vfe_violation_read()
889 * vfe_isr - VFE module interrupt handler
901 vfe->ops->isr_read(vfe, &value0, &value1); in vfe_isr()
903 dev_dbg(vfe->camss->dev, "VFE: status0 = 0x%08x, status1 = 0x%08x\n", in vfe_isr()
907 vfe->isr_ops.reset_ack(vfe); in vfe_isr()
910 vfe->ops->violation_read(vfe); in vfe_isr()
913 vfe->isr_ops.halt_ack(vfe); in vfe_isr()
917 vfe->isr_ops.reg_update(vfe, i); in vfe_isr()
920 vfe->isr_ops.sof(vfe, VFE_LINE_PIX); in vfe_isr()
924 vfe->isr_ops.sof(vfe, i); in vfe_isr()
928 vfe->isr_ops.comp_done(vfe, i); in vfe_isr()
929 for (j = 0; j < ARRAY_SIZE(vfe->wm_output_map); j++) in vfe_isr()
930 if (vfe->wm_output_map[j] == VFE_LINE_PIX) in vfe_isr()
936 vfe->isr_ops.wm_done(vfe, i); in vfe_isr()
942 * vfe_pm_domain_off - Disable power domains specific to this VFE.
951 * vfe_pm_domain_on - Enable power domains specific to this VFE.
998 vfe->isr_ops = vfe_isr_ops_gen1; in vfe_subdev_init()
999 vfe->ops_gen1 = &vfe_ops_gen1_4_1; in vfe_subdev_init()
1000 vfe->video_ops = vfe_video_ops_gen1; in vfe_subdev_init()
1002 vfe->line_num = VFE_LINE_NUM_GEN1; in vfe_subdev_init()