Lines Matching +full:8 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0 */
8 #include <linux/dma-mapping.h>
15 #include <media/media-device.h>
16 #include <media/media-entity.h>
17 #include <media/v4l2-async.h>
18 #include <media/v4l2-dev.h>
19 #include <media/v4l2-device.h>
20 #include <media/v4l2-subdev.h>
21 #include <media/videobuf2-core.h>
22 #include <media/videobuf2-v4l2.h>
27 #define CIO2_NAME "ipu3-cio2"
29 #define CIO2_ENTITY_NAME "ipu3-csi2"
37 /* 32MB = 8xFBPT_entry */
38 #define CIO2_MAX_LOPS 8
52 /* Register and bit field definitions */
68 #define CIO2_CSIRX_IF_CONFIG_FLAG_ERROR BIT(2)
74 /* Termination enable and settle in 0.0625ns units, lane=0..3 or -1 for clock */
76 (CIO2_REG_CSIRX_BASE + 0x2c + 8 * (lane))
78 (CIO2_REG_CSIRX_BASE + 0x30 + 8 * (lane))
85 #define CIO2_REG_MIPIBE_FORCE_RAW8_ENABLE BIT(0)
86 #define CIO2_REG_MIPIBE_FORCE_RAW8_USE_TYPEID BIT(1)
106 /* IRQ registers are 18-bit wide, see cio2_irq_error for bit definitions */
120 #define CIO2_CGC_CSI2_TGE BIT(0)
121 #define CIO2_CGC_PRIM_TGE BIT(1)
122 #define CIO2_CGC_SIDE_TGE BIT(2)
123 #define CIO2_CGC_XOSC_TGE BIT(3)
124 #define CIO2_CGC_MPLL_SHUTDOWN_EN BIT(4)
125 #define CIO2_CGC_D3I3_TGE BIT(5)
126 #define CIO2_CGC_CSI2_INTERFRAME_TGE BIT(6)
127 #define CIO2_CGC_CSI2_PORT_DCGE BIT(8)
128 #define CIO2_CGC_CSI2_DCGE BIT(9)
129 #define CIO2_CGC_SIDE_DCGE BIT(10)
130 #define CIO2_CGC_PRIM_DCGE BIT(11)
131 #define CIO2_CGC_ROSC_DCGE BIT(12)
132 #define CIO2_CGC_XOSC_DCGE BIT(13)
133 #define CIO2_CGC_FLIS_DCGE BIT(14)
137 #define CIO2_D0I3C_I3 BIT(2) /* Set D0I3 */
138 #define CIO2_D0I3C_RR BIT(3) /* Restore? */
152 * Interrupt on completion bit, Eg. DMA 0-3 maps to bit 0-3,
153 * DMA4 & DMA5 map to bit 4 ... DMA18 & DMA19 map to bit 11 Et cetera
161 #define CIO2_INT_IOIE BIT(22)
162 #define CIO2_INT_IOOE BIT(23)
163 #define CIO2_INT_IOIRQ BIT(24)
168 #define CIO2_PBM_ARB_CTRL_LANES_DIV 0U /* 4-4-2-2 lanes */
170 #define CIO2_PBM_ARB_CTRL_LE_EN BIT(7)
172 #define CIO2_PBM_ARB_CTRL_PLL_POST_SHTDN_SHIFT 8U
177 #define CIO2_PBM_WMCTRL1_MID1_2CK_SHIFT 8U
179 #define CIO2_PBM_WMCTRL1_TS_COUNT_DISABLE BIT(31)
187 #define CIO2_PBM_WMCTRL2_LWM_2CK_SHIFT 8U
192 #define CIO2_PBM_WMCTRL2_DYNWMEN BIT(28)
193 #define CIO2_PBM_WMCTRL2_OBFF_MEM_EN BIT(29)
194 #define CIO2_PBM_WMCTRL2_OBFF_CPU_EN BIT(30)
195 #define CIO2_PBM_WMCTRL2_DRAINNOW BIT(31)
199 #define CIO2_PBM_FOPN_ABORT(n) (0x1 << 8U * (n))
200 #define CIO2_PBM_FOPN_FORCE_ABORT(n) (0x2 << 8U * (n))
201 #define CIO2_PBM_FOPN_FRAMEOPEN(n) (0x8 << 8U * (n))
203 #define CIO2_LTRCTRL_LTRDYNEN BIT(16)
204 #define CIO2_LTRCTRL_LTRSTABLETIME_SHIFT 8U
206 #define CIO2_LTRCTRL_LTRSEL1S3 BIT(7)
207 #define CIO2_LTRCTRL_LTRSEL1S2 BIT(6)
208 #define CIO2_LTRCTRL_LTRSEL1S1 BIT(5)
209 #define CIO2_LTRCTRL_LTRSEL1S0 BIT(4)
210 #define CIO2_LTRCTRL_LTRSEL2S3 BIT(3)
211 #define CIO2_LTRCTRL_LTRSEL2S2 BIT(2)
212 #define CIO2_LTRCTRL_LTRSEL2S1 BIT(1)
213 #define CIO2_LTRCTRL_LTRSEL2S0 BIT(0)
237 #define CIO2_CDMAC0_FBPT_WIDTH_SHIFT 8U
238 #define CIO2_CDMAC0_FBPT_NS BIT(25)
239 #define CIO2_CDMAC0_DMA_INTR_ON_FS BIT(26)
240 #define CIO2_CDMAC0_DMA_INTR_ON_FE BIT(27)
241 #define CIO2_CDMAC0_FBPT_UPDATE_FIFO_FULL BIT(28)
242 #define CIO2_CDMAC0_FBPT_FIFO_FULL_FIX_DIS BIT(29)
243 #define CIO2_CDMAC0_DMA_EN BIT(30)
244 #define CIO2_CDMAC0_DMA_HALTED BIT(31)
265 #define CIO2_PXM_PXF_FMT_CFG_PSWAP4_1ST_CD (1 << 8)
270 #define CIO2_INT_EXT_IE_ECC_RE(n) (0x01 << (8U * (n)))
271 #define CIO2_INT_EXT_IE_DPHY_NR(n) (0x02 << (8U * (n)))
272 #define CIO2_INT_EXT_IE_ECC_NR(n) (0x04 << (8U * (n)))
273 #define CIO2_INT_EXT_IE_CRCERR(n) (0x08 << (8U * (n)))
274 #define CIO2_INT_EXT_IE_INTERFRAMEDATA(n) (0x10 << (8U * (n)))
275 #define CIO2_INT_EXT_IE_PKT2SHORT(n) (0x20 << (8U * (n)))
276 #define CIO2_INT_EXT_IE_PKT2LONG(n) (0x40 << (8U * (n)))
277 #define CIO2_INT_EXT_IE_IRQ(n) (0x80 << (8U * (n)))
279 #define CIO2_PXM_FRF_CFG_FNSEL BIT(0)
280 #define CIO2_PXM_FRF_CFG_FN_RST BIT(1)
281 #define CIO2_PXM_FRF_CFG_ABORT BIT(2)
283 #define CIO2_PXM_FRF_CFG_MSK_ECC_DPHY_NR BIT(8)
284 #define CIO2_PXM_FRF_CFG_MSK_ECC_RE BIT(9)
285 #define CIO2_PXM_FRF_CFG_MSK_ECC_DPHY_NE BIT(10)
287 #define CIO2_PXM_FRF_CFG_MASK_CRC_THRES BIT(13)
288 #define CIO2_PXM_FRF_CFG_MASK_CSI_ACCEPT BIT(14)
289 #define CIO2_PXM_FRF_CFG_CIOHC_FS_MODE BIT(15)
308 #define CIO2_CSIRX_DLY_CNT_CLANE_IDX -1
313 #define CIO2_CSIRX_DLY_CNT_SETTLE_CLANE_B -8
318 #define CIO2_CSIRX_DLY_CNT_SETTLE_DLANE_B -2
354 /* Subdev, /dev/v4l-subdevX */
416 #define CIO2_FBPT_CTRL_VALID BIT(0)
417 #define CIO2_FBPT_CTRL_IOC BIT(1)
418 #define CIO2_FBPT_CTRL_IOS BIT(2)
419 #define CIO2_FBPT_CTRL_SUCCXFAIL BIT(3)
425 * several sub-entries