31 #define OV8865_SW_STANDBY_REG			0x100
32 #define OV8865_SW_STANDBY_STREAM_ON		BIT(0)
34 #define OV8865_SW_RESET_REG			0x103
35 #define OV8865_SW_RESET_RESET			BIT(0)
37 #define OV8865_PLL_CTRL0_REG			0x300
38 #define OV8865_PLL_CTRL0_PRE_DIV(v)		((v) & GENMASK(2, 0))
39 #define OV8865_PLL_CTRL1_REG			0x301
41 #define OV8865_PLL_CTRL2_REG			0x302
42 #define OV8865_PLL_CTRL2_MUL_L(v)		((v) & GENMASK(7, 0))
43 #define OV8865_PLL_CTRL3_REG			0x303
44 #define OV8865_PLL_CTRL3_M_DIV(v)		(((v) - 1) & GENMASK(3, 0))
45 #define OV8865_PLL_CTRL4_REG			0x304
46 #define OV8865_PLL_CTRL4_MIPI_DIV(v)		((v) & GENMASK(1, 0))
47 #define OV8865_PLL_CTRL5_REG			0x305
48 #define OV8865_PLL_CTRL5_SYS_PRE_DIV(v)		((v) & GENMASK(1, 0))
49 #define OV8865_PLL_CTRL6_REG			0x306
50 #define OV8865_PLL_CTRL6_SYS_DIV(v)		(((v) - 1) & BIT(0))
52 #define OV8865_PLL_CTRL8_REG			0x308
53 #define OV8865_PLL_CTRL9_REG			0x309
54 #define OV8865_PLL_CTRLA_REG			0x30a
55 #define OV8865_PLL_CTRLA_PRE_DIV_HALF(v)	(((v) - 1) & BIT(0))
56 #define OV8865_PLL_CTRLB_REG			0x30b
57 #define OV8865_PLL_CTRLB_PRE_DIV(v)		((v) & GENMASK(2, 0))
58 #define OV8865_PLL_CTRLC_REG			0x30c
60 #define OV8865_PLL_CTRLD_REG			0x30d
61 #define OV8865_PLL_CTRLD_MUL_L(v)		((v) & GENMASK(7, 0))
62 #define OV8865_PLL_CTRLE_REG			0x30e
63 #define OV8865_PLL_CTRLE_SYS_DIV(v)		((v) & GENMASK(2, 0))
64 #define OV8865_PLL_CTRLF_REG			0x30f
65 #define OV8865_PLL_CTRLF_SYS_PRE_DIV(v)		(((v) - 1) & GENMASK(3, 0))
66 #define OV8865_PLL_CTRL10_REG			0x310
67 #define OV8865_PLL_CTRL11_REG			0x311
68 #define OV8865_PLL_CTRL12_REG			0x312
70 #define OV8865_PLL_CTRL12_DAC_DIV(v)		(((v) - 1) & GENMASK(3, 0))
72 #define OV8865_PLL_CTRL1B_REG			0x31b
73 #define OV8865_PLL_CTRL1C_REG			0x31c
75 #define OV8865_PLL_CTRL1E_REG			0x31e
78 #define OV8865_PAD_OEN0_REG			0x3000
80 #define OV8865_PAD_OEN2_REG			0x3002
82 #define OV8865_CLK_RST5_REG			0x3005
84 #define OV8865_CHIP_ID_HH_REG			0x300a
85 #define OV8865_CHIP_ID_HH_VALUE			0x00
86 #define OV8865_CHIP_ID_H_REG			0x300b
87 #define OV8865_CHIP_ID_H_VALUE			0x88
88 #define OV8865_CHIP_ID_L_REG			0x300c
89 #define OV8865_CHIP_ID_L_VALUE			0x65
90 #define OV8865_PAD_OUT2_REG			0x300d
92 #define OV8865_PAD_SEL2_REG			0x3010
93 #define OV8865_PAD_PK_REG			0x3011
94 #define OV8865_PAD_PK_DRIVE_STRENGTH_1X		(0 << 5)
99 #define OV8865_PUMP_CLK_DIV_REG			0x3015
101 #define OV8865_PUMP_CLK_DIV_PUMP_P(v)		((v) & GENMASK(2, 0))
103 #define OV8865_MIPI_SC_CTRL0_REG		0x3018
108 #define OV8865_MIPI_SC_CTRL0_LANES_PD_MIPI	BIT(0)
109 #define OV8865_MIPI_SC_CTRL1_REG		0x3019
110 #define OV8865_CLK_RST0_REG			0x301a
111 #define OV8865_CLK_RST1_REG			0x301b
112 #define OV8865_CLK_RST2_REG			0x301c
113 #define OV8865_CLK_RST3_REG			0x301d
114 #define OV8865_CLK_RST4_REG			0x301e
116 #define OV8865_PCLK_SEL_REG			0x3020
120 #define OV8865_MISC_CTRL_REG			0x3021
121 #define OV8865_MIPI_SC_CTRL2_REG		0x3022
123 #define OV8865_MIPI_SC_CTRL2_PD_MIPI_RST_SYNC	BIT(0)
125 #define OV8865_MIPI_BIT_SEL_REG			0x3031
126 #define OV8865_MIPI_BIT_SEL(v)			(((v) << 0) & GENMASK(4, 0))
127 #define OV8865_CLK_SEL0_REG			0x3032
129 #define OV8865_CLK_SEL1_REG			0x3033
135 #define OV8865_SCLK_CTRL_REG			0x3106
138 #define OV8865_SCLK_CTRL_UNKNOWN		BIT(0)
142 #define OV8865_EXPOSURE_CTRL_HH_REG		0x3500
144 #define OV8865_EXPOSURE_CTRL_H_REG		0x3501
146 #define OV8865_EXPOSURE_CTRL_L_REG		0x3502
147 #define OV8865_EXPOSURE_CTRL_L(v)		((v) & GENMASK(7, 0))
148 #define OV8865_EXPOSURE_GAIN_MANUAL_REG		0x3503
150 #define OV8865_GAIN_CTRL_H_REG			0x3508
152 #define OV8865_GAIN_CTRL_L_REG			0x3509
153 #define OV8865_GAIN_CTRL_L(v)			((v) & GENMASK(7, 0))
157 #define OV8865_CROP_START_X_H_REG		0x3800
159 #define OV8865_CROP_START_X_L_REG		0x3801
160 #define OV8865_CROP_START_X_L(v)		((v) & GENMASK(7, 0))
161 #define OV8865_CROP_START_Y_H_REG		0x3802
163 #define OV8865_CROP_START_Y_L_REG		0x3803
164 #define OV8865_CROP_START_Y_L(v)		((v) & GENMASK(7, 0))
165 #define OV8865_CROP_END_X_H_REG			0x3804
167 #define OV8865_CROP_END_X_L_REG			0x3805
168 #define OV8865_CROP_END_X_L(v)			((v) & GENMASK(7, 0))
169 #define OV8865_CROP_END_Y_H_REG			0x3806
171 #define OV8865_CROP_END_Y_L_REG			0x3807
172 #define OV8865_CROP_END_Y_L(v)			((v) & GENMASK(7, 0))
173 #define OV8865_OUTPUT_SIZE_X_H_REG		0x3808
175 #define OV8865_OUTPUT_SIZE_X_L_REG		0x3809
176 #define OV8865_OUTPUT_SIZE_X_L(v)		((v) & GENMASK(7, 0))
177 #define OV8865_OUTPUT_SIZE_Y_H_REG		0x380a
179 #define OV8865_OUTPUT_SIZE_Y_L_REG		0x380b
180 #define OV8865_OUTPUT_SIZE_Y_L(v)		((v) & GENMASK(7, 0))
181 #define OV8865_HTS_H_REG			0x380c
183 #define OV8865_HTS_L_REG			0x380d
184 #define OV8865_HTS_L(v)				((v) & GENMASK(7, 0))
185 #define OV8865_VTS_H_REG			0x380e
187 #define OV8865_VTS_L_REG			0x380f
188 #define OV8865_VTS_L(v)				((v) & GENMASK(7, 0))
189 #define OV8865_OFFSET_X_H_REG			0x3810
191 #define OV8865_OFFSET_X_L_REG			0x3811
192 #define OV8865_OFFSET_X_L(v)			((v) & GENMASK(7, 0))
193 #define OV8865_OFFSET_Y_H_REG			0x3812
195 #define OV8865_OFFSET_Y_L_REG			0x3813
196 #define OV8865_OFFSET_Y_L(v)			((v) & GENMASK(7, 0))
197 #define OV8865_INC_X_ODD_REG			0x3814
198 #define OV8865_INC_X_ODD(v)			((v) & GENMASK(4, 0))
199 #define OV8865_INC_X_EVEN_REG			0x3815
200 #define OV8865_INC_X_EVEN(v)			((v) & GENMASK(4, 0))
201 #define OV8865_VSYNC_START_H_REG		0x3816
203 #define OV8865_VSYNC_START_L_REG		0x3817
204 #define OV8865_VSYNC_START_L(v)			((v) & GENMASK(7, 0))
205 #define OV8865_VSYNC_END_H_REG			0x3818
207 #define OV8865_VSYNC_END_L_REG			0x3819
208 #define OV8865_VSYNC_END_L(v)			((v) & GENMASK(7, 0))
209 #define OV8865_HSYNC_FIRST_H_REG		0x381a
211 #define OV8865_HSYNC_FIRST_L_REG		0x381b
212 #define OV8865_HSYNC_FIRST_L(v)			((v) & GENMASK(7, 0))
214 #define OV8865_FORMAT1_REG			0x3820
217 #define OV8865_FORMAT2_REG			0x3821
224 #define OV8865_FORMAT2_SYNC_HBIN_EN		BIT(0)
226 #define OV8865_INC_Y_ODD_REG			0x382a
227 #define OV8865_INC_Y_ODD(v)			((v) & GENMASK(4, 0))
228 #define OV8865_INC_Y_EVEN_REG			0x382b
229 #define OV8865_INC_Y_EVEN(v)			((v) & GENMASK(4, 0))
231 #define OV8865_ABLC_NUM_REG			0x3830
232 #define OV8865_ABLC_NUM(v)			((v) & GENMASK(4, 0))
234 #define OV8865_ZLINE_NUM_REG			0x3836
235 #define OV8865_ZLINE_NUM(v)			((v) & GENMASK(4, 0))
237 #define OV8865_AUTO_SIZE_CTRL_REG		0x3841
243 #define OV8865_AUTO_SIZE_CTRL_CROP_START_X_REG	BIT(0)
244 #define OV8865_AUTO_SIZE_X_OFFSET_H_REG		0x3842
245 #define OV8865_AUTO_SIZE_X_OFFSET_L_REG		0x3843
246 #define OV8865_AUTO_SIZE_Y_OFFSET_H_REG		0x3844
247 #define OV8865_AUTO_SIZE_Y_OFFSET_L_REG		0x3845
248 #define OV8865_AUTO_SIZE_BOUNDARIES_REG		0x3846
250 #define OV8865_AUTO_SIZE_BOUNDARIES_X(v)	((v) & GENMASK(3, 0))
254 #define OV8865_PSRAM_CTRL8_REG			0x3f08
258 #define OV8865_BLC_CTRL0_REG			0x4000
266 #define OV8865_BLC_CTRL0_FILTER_EN		BIT(0)
267 #define OV8865_BLC_CTRL1_REG			0x4001
270 #define OV8865_BLC_CTRL1_COL_SHIFT_256		(0 << 4)
276 #define OV8865_BLC_CTRL2_REG			0x4002
277 #define OV8865_BLC_CTRL3_REG			0x4003
278 #define OV8865_BLC_CTRL4_REG			0x4004
279 #define OV8865_BLC_CTRL5_REG			0x4005
280 #define OV8865_BLC_CTRL6_REG			0x4006
281 #define OV8865_BLC_CTRL7_REG			0x4007
282 #define OV8865_BLC_CTRL8_REG			0x4008
283 #define OV8865_BLC_CTRL9_REG			0x4009
284 #define OV8865_BLC_CTRLA_REG			0x400a
285 #define OV8865_BLC_CTRLB_REG			0x400b
286 #define OV8865_BLC_CTRLC_REG			0x400c
287 #define OV8865_BLC_CTRLD_REG			0x400d
288 #define OV8865_BLC_CTRLD_OFFSET_TRIGGER(v)	((v) & GENMASK(7, 0))
290 #define OV8865_BLC_CTRL1F_REG			0x401f
295 #define OV8865_BLC_ANCHOR_LEFT_START_H_REG	0x4020
297 #define OV8865_BLC_ANCHOR_LEFT_START_L_REG	0x4021
298 #define OV8865_BLC_ANCHOR_LEFT_START_L(v)	((v) & GENMASK(7, 0))
299 #define OV8865_BLC_ANCHOR_LEFT_END_H_REG	0x4022
301 #define OV8865_BLC_ANCHOR_LEFT_END_L_REG	0x4023
302 #define OV8865_BLC_ANCHOR_LEFT_END_L(v)		((v) & GENMASK(7, 0))
303 #define OV8865_BLC_ANCHOR_RIGHT_START_H_REG	0x4024
305 #define OV8865_BLC_ANCHOR_RIGHT_START_L_REG	0x4025
306 #define OV8865_BLC_ANCHOR_RIGHT_START_L(v)	((v) & GENMASK(7, 0))
307 #define OV8865_BLC_ANCHOR_RIGHT_END_H_REG	0x4026
309 #define OV8865_BLC_ANCHOR_RIGHT_END_L_REG	0x4027
310 #define OV8865_BLC_ANCHOR_RIGHT_END_L(v)	((v) & GENMASK(7, 0))
312 #define OV8865_BLC_TOP_ZLINE_START_REG		0x4028
313 #define OV8865_BLC_TOP_ZLINE_START(v)		((v) & GENMASK(5, 0))
314 #define OV8865_BLC_TOP_ZLINE_NUM_REG		0x4029
315 #define OV8865_BLC_TOP_ZLINE_NUM(v)		((v) & GENMASK(4, 0))
316 #define OV8865_BLC_TOP_BLKLINE_START_REG	0x402a
317 #define OV8865_BLC_TOP_BLKLINE_START(v)		((v) & GENMASK(5, 0))
318 #define OV8865_BLC_TOP_BLKLINE_NUM_REG		0x402b
319 #define OV8865_BLC_TOP_BLKLINE_NUM(v)		((v) & GENMASK(4, 0))
320 #define OV8865_BLC_BOT_ZLINE_START_REG		0x402c
321 #define OV8865_BLC_BOT_ZLINE_START(v)		((v) & GENMASK(5, 0))
322 #define OV8865_BLC_BOT_ZLINE_NUM_REG		0x402d
323 #define OV8865_BLC_BOT_ZLINE_NUM(v)		((v) & GENMASK(4, 0))
324 #define OV8865_BLC_BOT_BLKLINE_START_REG	0x402e
325 #define OV8865_BLC_BOT_BLKLINE_START(v)		((v) & GENMASK(5, 0))
326 #define OV8865_BLC_BOT_BLKLINE_NUM_REG		0x402f
327 #define OV8865_BLC_BOT_BLKLINE_NUM(v)		((v) & GENMASK(4, 0))
329 #define OV8865_BLC_OFFSET_LIMIT_REG		0x4034
330 #define OV8865_BLC_OFFSET_LIMIT(v)		((v) & GENMASK(7, 0))
334 #define OV8865_VFIFO_READ_START_H_REG		0x4600
336 #define OV8865_VFIFO_READ_START_L_REG		0x4601
337 #define OV8865_VFIFO_READ_START_L(v)		((v) & GENMASK(7, 0))
341 #define OV8865_MIPI_CTRL0_REG			0x4800
342 #define OV8865_MIPI_CTRL1_REG			0x4801
343 #define OV8865_MIPI_CTRL2_REG			0x4802
344 #define OV8865_MIPI_CTRL3_REG			0x4803
345 #define OV8865_MIPI_CTRL4_REG			0x4804
346 #define OV8865_MIPI_CTRL5_REG			0x4805
347 #define OV8865_MIPI_CTRL6_REG			0x4806
348 #define OV8865_MIPI_CTRL7_REG			0x4807
349 #define OV8865_MIPI_CTRL8_REG			0x4808
351 #define OV8865_MIPI_FCNT_MAX_H_REG		0x4810
352 #define OV8865_MIPI_FCNT_MAX_L_REG		0x4811
354 #define OV8865_MIPI_CTRL13_REG			0x4813
355 #define OV8865_MIPI_CTRL14_REG			0x4814
356 #define OV8865_MIPI_CTRL15_REG			0x4815
357 #define OV8865_MIPI_EMBEDDED_DT_REG		0x4816
359 #define OV8865_MIPI_HS_ZERO_MIN_H_REG		0x4818
360 #define OV8865_MIPI_HS_ZERO_MIN_L_REG		0x4819
361 #define OV8865_MIPI_HS_TRAIL_MIN_H_REG		0x481a
362 #define OV8865_MIPI_HS_TRAIL_MIN_L_REG		0x481b
363 #define OV8865_MIPI_CLK_ZERO_MIN_H_REG		0x481c
364 #define OV8865_MIPI_CLK_ZERO_MIN_L_REG		0x481d
365 #define OV8865_MIPI_CLK_PREPARE_MAX_REG		0x481e
366 #define OV8865_MIPI_CLK_PREPARE_MIN_REG		0x481f
367 #define OV8865_MIPI_CLK_POST_MIN_H_REG		0x4820
368 #define OV8865_MIPI_CLK_POST_MIN_L_REG		0x4821
369 #define OV8865_MIPI_CLK_TRAIL_MIN_H_REG		0x4822
370 #define OV8865_MIPI_CLK_TRAIL_MIN_L_REG		0x4823
371 #define OV8865_MIPI_LPX_P_MIN_H_REG		0x4824
372 #define OV8865_MIPI_LPX_P_MIN_L_REG		0x4825
373 #define OV8865_MIPI_HS_PREPARE_MIN_REG		0x4826
374 #define OV8865_MIPI_HS_PREPARE_MAX_REG		0x4827
375 #define OV8865_MIPI_HS_EXIT_MIN_H_REG		0x4828
376 #define OV8865_MIPI_HS_EXIT_MIN_L_REG		0x4829
377 #define OV8865_MIPI_UI_HS_ZERO_MIN_REG		0x482a
378 #define OV8865_MIPI_UI_HS_TRAIL_MIN_REG		0x482b
379 #define OV8865_MIPI_UI_CLK_ZERO_MIN_REG		0x482c
380 #define OV8865_MIPI_UI_CLK_PREPARE_REG		0x482d
381 #define OV8865_MIPI_UI_CLK_POST_MIN_REG		0x482e
382 #define OV8865_MIPI_UI_CLK_TRAIL_MIN_REG	0x482f
383 #define OV8865_MIPI_UI_LPX_P_MIN_REG		0x4830
384 #define OV8865_MIPI_UI_HS_PREPARE_REG		0x4831
385 #define OV8865_MIPI_UI_HS_EXIT_MIN_REG		0x4832
386 #define OV8865_MIPI_PKT_START_SIZE_REG		0x4833
388 #define OV8865_MIPI_PCLK_PERIOD_REG		0x4837
389 #define OV8865_MIPI_LP_GPIO0_REG		0x4838
390 #define OV8865_MIPI_LP_GPIO1_REG		0x4839
392 #define OV8865_MIPI_CTRL3C_REG			0x483c
393 #define OV8865_MIPI_LP_GPIO4_REG		0x483d
395 #define OV8865_MIPI_CTRL4A_REG			0x484a
396 #define OV8865_MIPI_CTRL4B_REG			0x484b
397 #define OV8865_MIPI_CTRL4C_REG			0x484c
398 #define OV8865_MIPI_LANE_TEST_PATTERN_REG	0x484d
399 #define OV8865_MIPI_FRAME_END_DELAY_REG		0x484e
400 #define OV8865_MIPI_CLOCK_TEST_PATTERN_REG	0x484f
401 #define OV8865_MIPI_LANE_SEL01_REG		0x4850
402 #define OV8865_MIPI_LANE_SEL01_LANE0(v)		(((v) << 0) & GENMASK(2, 0))
404 #define OV8865_MIPI_LANE_SEL23_REG		0x4851
405 #define OV8865_MIPI_LANE_SEL23_LANE2(v)		(((v) << 0) & GENMASK(2, 0))
410 #define OV8865_ISP_CTRL0_REG			0x5000
415 #define OV8865_ISP_CTRL1_REG			0x5001
416 #define OV8865_ISP_CTRL1_BLC_EN			BIT(0)
417 #define OV8865_ISP_CTRL2_REG			0x5002
420 #define OV8865_ISP_CTRL2_VSYNC_LATCH_EN		BIT(0)
421 #define OV8865_ISP_CTRL3_REG			0x5003
423 #define OV8865_ISP_GAIN_RED_H_REG		0x5018
425 #define OV8865_ISP_GAIN_RED_L_REG		0x5019
426 #define OV8865_ISP_GAIN_RED_L(v)		((v) & GENMASK(5, 0))
427 #define OV8865_ISP_GAIN_GREEN_H_REG		0x501a
429 #define OV8865_ISP_GAIN_GREEN_L_REG		0x501b
430 #define OV8865_ISP_GAIN_GREEN_L(v)		((v) & GENMASK(5, 0))
431 #define OV8865_ISP_GAIN_BLUE_H_REG		0x501c
433 #define OV8865_ISP_GAIN_BLUE_L_REG		0x501d
434 #define OV8865_ISP_GAIN_BLUE_L(v)		((v) & GENMASK(5, 0))
438 #define OV8865_VAP_CTRL0_REG			0x5900
439 #define OV8865_VAP_CTRL1_REG			0x5901
442 #define OV8865_VAP_CTRL1_VSUB_COEF(v)		(((v) - 1) & GENMASK(1, 0))
446 #define OV8865_PRE_CTRL0_REG			0x5e00
451 #define OV8865_PRE_CTRL0_PATTERN_COLOR_BARS	0
478  * +-+ pll_pre_div_half (0x30a [0])
480  *   +-+ pll_pre_div (0x300 [2:0], special values:
481  *     |              0: 1, 1: 1.5, 3: 2.5, 4: 3, 5: 4, 7: 8)
482  *     +-+ pll_mul (0x301 [1:0], 0x302 [7:0])
484  *       +-+ m_div (0x303 [3:0])
488  *       | +-+ mipi_div (0x304 [1:0], special values: 0: 4, 1: 5, 2: 6, 3: 8)
490  *       |   +-+ pclk_div (0x3020 [3])
494  *       +-+ sys_pre_div (0x305 [1:0], special values: 0: 3, 1: 4, 2: 5, 3: 6)
496  *         +-+ sys_div (0x306 [0])
498  *           +-+ sys_sel (0x3032 [7], 0: PLL1, 1: PLL2)
500  *             +-+ sclk_sel (0x3033 [1], 0: sys_sel, 1: PLL2 DAC_CLK)
502  *               +-+ sclk_pre_div (0x3106 [3:2], special values:
503  *                 |               0: 1, 1: 2, 2: 4, 3: 1)
505  *                 +-+ sclk_div (0x3106 [7:4], special values: 0: 1)
526  * +-+ pll_pre_div_half (0x312 [4])
528  *   +-+ pll_pre_div (0x30b [2:0], special values:
529  *     |              0: 1, 1: 1.5, 3: 2.5, 4: 3, 5: 4, 7: 8)
530  *     +-+ pll_mul (0x30c [1:0], 0x30d [7:0])
532  *       +-+ dac_div (0x312 [3:0])
536  *       +-+ sys_pre_div (0x30f [3:0])
538  *         +-+ sys_div (0x30e [2:0], special values:
539  *           |          0: 1, 1: 1.5, 3: 2.5, 4: 3, 5: 3.5, 6: 4, 7:5)
541  *           +-+ sys_sel (0x3032 [7], 0: PLL1, 1: PLL2)
543  *             +-+ sclk_sel (0x3033 [1], 0: sys_sel, 1: PLL2 DAC_CLK)
545  *               +-+ sclk_pre_div (0x3106 [3:2], special values:
546  *                 |               0: 1, 1: 2, 2: 4, 3: 1)
548  *                 +-+ sclk_div (0x3106 [7:4], special values: 0: 1)
688 	.pll_pre_div		= 0,
705 	.pll_pre_div		= 0,
709 	.sys_div		= 0,
720 	.pll_pre_div		= 0,
724 	.sys_div		= 0,
729 	.sclk_sel		= 0,
730 	.sclk_pre_div		= 0,
731 	.sclk_div		= 0,
737 	{ 0x3700, 0x48 },
738 	{ 0x3701, 0x18 },
739 	{ 0x3702, 0x50 },
740 	{ 0x3703, 0x32 },
741 	{ 0x3704, 0x28 },
742 	{ 0x3706, 0x70 },
743 	{ 0x3707, 0x08 },
744 	{ 0x3708, 0x48 },
745 	{ 0x3709, 0x80 },
746 	{ 0x370a, 0x01 },
747 	{ 0x370b, 0x70 },
748 	{ 0x370c, 0x07 },
749 	{ 0x3718, 0x14 },
750 	{ 0x3712, 0x44 },
751 	{ 0x371e, 0x31 },
752 	{ 0x371f, 0x7f },
753 	{ 0x3720, 0x0a },
754 	{ 0x3721, 0x0a },
755 	{ 0x3724, 0x04 },
756 	{ 0x3725, 0x04 },
757 	{ 0x3726, 0x0c },
758 	{ 0x3728, 0x0a },
759 	{ 0x3729, 0x03 },
760 	{ 0x372a, 0x06 },
761 	{ 0x372b, 0xa6 },
762 	{ 0x372c, 0xa6 },
763 	{ 0x372d, 0xa6 },
764 	{ 0x372e, 0x0c },
765 	{ 0x372f, 0x20 },
766 	{ 0x3730, 0x02 },
767 	{ 0x3731, 0x0c },
768 	{ 0x3732, 0x28 },
769 	{ 0x3736, 0x30 },
770 	{ 0x373a, 0x04 },
771 	{ 0x373b, 0x18 },
772 	{ 0x373c, 0x14 },
773 	{ 0x373e, 0x06 },
774 	{ 0x375a, 0x0c },
775 	{ 0x375b, 0x26 },
776 	{ 0x375d, 0x04 },
777 	{ 0x375f, 0x28 },
778 	{ 0x3767, 0x1e },
779 	{ 0x3772, 0x46 },
780 	{ 0x3773, 0x04 },
781 	{ 0x3774, 0x2c },
782 	{ 0x3775, 0x13 },
783 	{ 0x3776, 0x10 },
784 	{ 0x37a0, 0x88 },
785 	{ 0x37a1, 0x7a },
786 	{ 0x37a2, 0x7a },
787 	{ 0x37a3, 0x02 },
788 	{ 0x37a5, 0x09 },
789 	{ 0x37a7, 0x88 },
790 	{ 0x37a8, 0xb0 },
791 	{ 0x37a9, 0xb0 },
792 	{ 0x37aa, 0x88 },
793 	{ 0x37ab, 0x5c },
794 	{ 0x37ac, 0x5c },
795 	{ 0x37ad, 0x55 },
796 	{ 0x37ae, 0x19 },
797 	{ 0x37af, 0x19 },
798 	{ 0x37b3, 0x84 },
799 	{ 0x37b4, 0x84 },
800 	{ 0x37b5, 0x66 },
804 	{ OV8865_PSRAM_CTRL8_REG, 0x16 },
808 	{ 0x4500, 0x68 },
814 	{ 0x3700, 0x24 },
815 	{ 0x3701, 0x0c },
816 	{ 0x3702, 0x28 },
817 	{ 0x3703, 0x19 },
818 	{ 0x3704, 0x14 },
819 	{ 0x3706, 0x38 },
820 	{ 0x3707, 0x04 },
821 	{ 0x3708, 0x24 },
822 	{ 0x3709, 0x40 },
823 	{ 0x370a, 0x00 },
824 	{ 0x370b, 0xb8 },
825 	{ 0x370c, 0x04 },
826 	{ 0x3718, 0x12 },
827 	{ 0x3712, 0x42 },
828 	{ 0x371e, 0x19 },
829 	{ 0x371f, 0x40 },
830 	{ 0x3720, 0x05 },
831 	{ 0x3721, 0x05 },
832 	{ 0x3724, 0x02 },
833 	{ 0x3725, 0x02 },
834 	{ 0x3726, 0x06 },
835 	{ 0x3728, 0x05 },
836 	{ 0x3729, 0x02 },
837 	{ 0x372a, 0x03 },
838 	{ 0x372b, 0x53 },
839 	{ 0x372c, 0xa3 },
840 	{ 0x372d, 0x53 },
841 	{ 0x372e, 0x06 },
842 	{ 0x372f, 0x10 },
843 	{ 0x3730, 0x01 },
844 	{ 0x3731, 0x06 },
845 	{ 0x3732, 0x14 },
846 	{ 0x3736, 0x20 },
847 	{ 0x373a, 0x02 },
848 	{ 0x373b, 0x0c },
849 	{ 0x373c, 0x0a },
850 	{ 0x373e, 0x03 },
851 	{ 0x375a, 0x06 },
852 	{ 0x375b, 0x13 },
853 	{ 0x375d, 0x02 },
854 	{ 0x375f, 0x14 },
855 	{ 0x3767, 0x1c },
856 	{ 0x3772, 0x23 },
857 	{ 0x3773, 0x02 },
858 	{ 0x3774, 0x16 },
859 	{ 0x3775, 0x12 },
860 	{ 0x3776, 0x08 },
861 	{ 0x37a0, 0x44 },
862 	{ 0x37a1, 0x3d },
863 	{ 0x37a2, 0x3d },
864 	{ 0x37a3, 0x01 },
865 	{ 0x37a5, 0x08 },
866 	{ 0x37a7, 0x44 },
867 	{ 0x37a8, 0x58 },
868 	{ 0x37a9, 0x58 },
869 	{ 0x37aa, 0x44 },
870 	{ 0x37ab, 0x2e },
871 	{ 0x37ac, 0x2e },
872 	{ 0x37ad, 0x33 },
873 	{ 0x37ae, 0x0d },
874 	{ 0x37af, 0x0d },
875 	{ 0x37b3, 0x42 },
876 	{ 0x37b4, 0x42 },
877 	{ 0x37b5, 0x33 },
881 	{ OV8865_PSRAM_CTRL8_REG, 0x0b },
885 	{ 0x4500, 0x40 },
917 		.blc_top_zero_line_start	= 0,
973 		.blc_top_zero_line_start	= 0,
1033 		.blc_top_zero_line_start	= 0,
1097 		.blc_top_zero_line_start	= 0,
1102 		.blc_bottom_zero_line_start	= 0,
1103 		.blc_bottom_zero_line_num	= 0,
1136 	{ 0x3604, 0x04 },
1137 	{ 0x3602, 0x30 },
1138 	{ 0x3605, 0x00 },
1139 	{ 0x3607, 0x20 },
1140 	{ 0x3608, 0x11 },
1141 	{ 0x3609, 0x68 },
1142 	{ 0x360a, 0x40 },
1143 	{ 0x360c, 0xdd },
1144 	{ 0x360e, 0x0c },
1145 	{ 0x3610, 0x07 },
1146 	{ 0x3612, 0x86 },
1147 	{ 0x3613, 0x58 },
1148 	{ 0x3614, 0x28 },
1149 	{ 0x3617, 0x40 },
1150 	{ 0x3618, 0x5a },
1151 	{ 0x3619, 0x9b },
1152 	{ 0x361c, 0x00 },
1153 	{ 0x361d, 0x60 },
1154 	{ 0x3631, 0x60 },
1155 	{ 0x3633, 0x10 },
1156 	{ 0x3634, 0x10 },
1157 	{ 0x3635, 0x10 },
1158 	{ 0x3636, 0x10 },
1159 	{ 0x3638, 0xff },
1160 	{ 0x3641, 0x55 },
1161 	{ 0x3646, 0x86 },
1162 	{ 0x3647, 0x27 },
1163 	{ 0x364a, 0x1b },
1167 	{ 0x3700, 0x24 },
1168 	{ 0x3701, 0x0c },
1169 	{ 0x3702, 0x28 },
1170 	{ 0x3703, 0x19 },
1171 	{ 0x3704, 0x14 },
1172 	{ 0x3705, 0x00 },
1173 	{ 0x3706, 0x38 },
1174 	{ 0x3707, 0x04 },
1175 	{ 0x3708, 0x24 },
1176 	{ 0x3709, 0x40 },
1177 	{ 0x370a, 0x00 },
1178 	{ 0x370b, 0xb8 },
1179 	{ 0x370c, 0x04 },
1180 	{ 0x3718, 0x12 },
1181 	{ 0x3719, 0x31 },
1182 	{ 0x3712, 0x42 },
1183 	{ 0x3714, 0x12 },
1184 	{ 0x371e, 0x19 },
1185 	{ 0x371f, 0x40 },
1186 	{ 0x3720, 0x05 },
1187 	{ 0x3721, 0x05 },
1188 	{ 0x3724, 0x02 },
1189 	{ 0x3725, 0x02 },
1190 	{ 0x3726, 0x06 },
1191 	{ 0x3728, 0x05 },
1192 	{ 0x3729, 0x02 },
1193 	{ 0x372a, 0x03 },
1194 	{ 0x372b, 0x53 },
1195 	{ 0x372c, 0xa3 },
1196 	{ 0x372d, 0x53 },
1197 	{ 0x372e, 0x06 },
1198 	{ 0x372f, 0x10 },
1199 	{ 0x3730, 0x01 },
1200 	{ 0x3731, 0x06 },
1201 	{ 0x3732, 0x14 },
1202 	{ 0x3733, 0x10 },
1203 	{ 0x3734, 0x40 },
1204 	{ 0x3736, 0x20 },
1205 	{ 0x373a, 0x02 },
1206 	{ 0x373b, 0x0c },
1207 	{ 0x373c, 0x0a },
1208 	{ 0x373e, 0x03 },
1209 	{ 0x3755, 0x40 },
1210 	{ 0x3758, 0x00 },
1211 	{ 0x3759, 0x4c },
1212 	{ 0x375a, 0x06 },
1213 	{ 0x375b, 0x13 },
1214 	{ 0x375c, 0x40 },
1215 	{ 0x375d, 0x02 },
1216 	{ 0x375e, 0x00 },
1217 	{ 0x375f, 0x14 },
1218 	{ 0x3767, 0x1c },
1219 	{ 0x3768, 0x04 },
1220 	{ 0x3769, 0x20 },
1221 	{ 0x376c, 0xc0 },
1222 	{ 0x376d, 0xc0 },
1223 	{ 0x376a, 0x08 },
1224 	{ 0x3761, 0x00 },
1225 	{ 0x3762, 0x00 },
1226 	{ 0x3763, 0x00 },
1227 	{ 0x3766, 0xff },
1228 	{ 0x376b, 0x42 },
1229 	{ 0x3772, 0x23 },
1230 	{ 0x3773, 0x02 },
1231 	{ 0x3774, 0x16 },
1232 	{ 0x3775, 0x12 },
1233 	{ 0x3776, 0x08 },
1234 	{ 0x37a0, 0x44 },
1235 	{ 0x37a1, 0x3d },
1236 	{ 0x37a2, 0x3d },
1237 	{ 0x37a3, 0x01 },
1238 	{ 0x37a4, 0x00 },
1239 	{ 0x37a5, 0x08 },
1240 	{ 0x37a6, 0x00 },
1241 	{ 0x37a7, 0x44 },
1242 	{ 0x37a8, 0x58 },
1243 	{ 0x37a9, 0x58 },
1244 	{ 0x3760, 0x00 },
1245 	{ 0x376f, 0x01 },
1246 	{ 0x37aa, 0x44 },
1247 	{ 0x37ab, 0x2e },
1248 	{ 0x37ac, 0x2e },
1249 	{ 0x37ad, 0x33 },
1250 	{ 0x37ae, 0x0d },
1251 	{ 0x37af, 0x0d },
1252 	{ 0x37b0, 0x00 },
1253 	{ 0x37b1, 0x00 },
1254 	{ 0x37b2, 0x00 },
1255 	{ 0x37b3, 0x42 },
1256 	{ 0x37b4, 0x42 },
1257 	{ 0x37b5, 0x33 },
1258 	{ 0x37b6, 0x00 },
1259 	{ 0x37b7, 0x00 },
1260 	{ 0x37b8, 0x00 },
1261 	{ 0x37b9, 0xff },
1265 	{ 0x4503, 0x10 },
1282 	0,
1296 	unsigned char data[2] = { address >> 8, address & 0xff };  in ov8865_read()
1301 	if (ret < 0) {  in ov8865_read()
1308 	if (ret < 0) {  in ov8865_read()
1314 	return 0;  in ov8865_read()
1319 	unsigned char data[3] = { address >> 8, address & 0xff, value };  in ov8865_write()
1324 	if (ret < 0) {  in ov8865_write()
1330 	return 0;  in ov8865_write()
1338 	int ret = 0;  in ov8865_write_sequence()
1340 	for (i = 0; i < sequence_count; i++) {  in ov8865_write_sequence()
1356 	u8 value = 0;  in ov8865_update_bits()
1378 	u8 value = 0;  in ov8865_sw_standby()
1396 	for (i = 0; i < ARRAY_SIZE(regs); i++) {  in ov8865_chip_id_check()
1398 		if (ret < 0)  in ov8865_chip_id_check()
1409 	return 0;  in ov8865_chip_id_check()
1439 				   OV8865_MIPI_LANE_SEL01_LANE0(0) |  in ov8865_mipi_configure()
1464 	return ov8865_write(sensor, OV8865_MIPI_PCLK_PERIOD_REG, 0x16);  in ov8865_mipi_configure()
1487 	ret = ov8865_write(sensor, OV8865_BLC_CTRL1F_REG, 0);  in ov8865_black_level_configure()
1523 	case 0:  in ov8865_mode_pll1_rate()
1687 	ret = ov8865_write(sensor, OV8865_FORMAT1_REG, 0);  in ov8865_mode_binning_configure()
1712 				 OV8865_ISP_CTRL2_VARIOPIXEL_EN : 0);  in ov8865_mode_binning_configure()
2049 	return 0;  in ov8865_mode_configure()
2136 				  enable ? bits : 0);  in ov8865_flip_vert_configure()
2145 				  enable ? bits : 0);  in ov8865_flip_horz_configure()
2179 	for (i = 0; i < ARRAY_SIZE(ov8865_link_freq_menu); i++) {  in ov8865_state_mipi_configure()
2186 	for (j = 0; j < sensor->endpoint.nr_of_link_frequencies; j++) {  in ov8865_state_mipi_configure()
2218 	return 0;  in ov8865_state_mipi_configure()
2245 	return 0;  in ov8865_state_configure()
2250 	return ov8865_state_configure(sensor, &ov8865_modes[0],  in ov8865_state_init()
2251 				      ov8865_mbus_codes[0]);  in ov8865_state_init()
2317 	return 0;  in ov8865_sensor_init()
2323 	int ret = 0;  in ov8865_sensor_power()
2356 		gpiod_set_value_cansleep(sensor->reset, 0);  in ov8865_sensor_power()
2357 		gpiod_set_value_cansleep(sensor->powerdown, 0);  in ov8865_sensor_power()
2387 		return 0;  in ov8865_s_ctrl()
2415 	return 0;  in ov8865_s_ctrl()
2453 	v4l2_ctrl_new_std(handler, ops, V4L2_CID_HFLIP, 0, 1, 1, 0);  in ov8865_ctrls_init()
2454 	v4l2_ctrl_new_std(handler, ops, V4L2_CID_VFLIP, 0, 1, 1, 0);  in ov8865_ctrls_init()
2460 				     0, 0, ov8865_test_pattern_menu);  in ov8865_ctrls_init()
2467 				       0, ov8865_link_freq_menu);  in ov8865_ctrls_init()
2483 	return 0;  in ov8865_ctrls_init()
2501 		if (ret < 0)  in ov8865_s_stream()
2517 	return 0;  in ov8865_s_stream()
2533 	return 0;  in ov8865_g_frame_interval()
2553 	return 0;  in ov8865_enum_mbus_code()
2591 	return 0;  in ov8865_get_fmt()
2601 	u32 mbus_code = 0;  in ov8865_set_fmt()
2603 	int ret = 0;  in ov8865_set_fmt()
2613 	for (index = 0; index < ARRAY_SIZE(ov8865_mbus_codes); index++) {  in ov8865_set_fmt()
2622 		mbus_code = ov8865_mbus_codes[0];  in ov8865_set_fmt()
2662 	return 0;  in ov8865_enum_frame_size()
2673 	if (interval_enum->index > 0)  in ov8865_enum_frame_interval()
2679 	for (mode_index = 0, interval_index = 0;  in ov8865_enum_frame_interval()
2697 	return 0;  in ov8865_enum_frame_interval()
2719 	int ret = 0;  in ov8865_suspend()
2745 	int ret = 0;  in ov8865_resume()
2909 	return 0;  in ov8865_probe()
2942 	return 0;  in ov8865_remove()