Lines Matching +full:2 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
2 /* Copyright (C) 2019--2020 Intel Corporation */
4 * Generated by Documentation/driver-api/media/drivers/ccs/mk-ccs-regs;
14 #define CCS_FL_16BIT BIT(CCS_FL_BASE)
15 #define CCS_FL_32BIT BIT(CCS_FL_BASE + 1)
16 #define CCS_FL_FLOAT_IREAL BIT(CCS_FL_BASE + 2)
17 #define CCS_FL_IREAL BIT(CCS_FL_BASE + 3)
26 #define CCS_PIXEL_ORDER_BGGR 2U
46 #define CCS_MODULE_DATE_PHASE_CS 2U
56 #define CCS_FRAME_FORMAT_MODEL_TYPE_4_BYTE 2U
62 #define CCS_R_FRAME_FORMAT_DESCRIPTOR(n) ((0x0042 | CCS_FL_16BIT) + (n) * 2)
71 #define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_DUMMY_PIXEL 2U
89 #define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_DUMMY_PIXEL 2U
102 #define CCS_ANALOG_GAIN_CAPABILITY_ALTERNATE_GLOBAL 2U
119 #define CCS_DATA_FORMAT_MODEL_TYPE_EXTENDED 2U
125 #define CCS_R_DATA_FORMAT_DESCRIPTOR(n) ((0x00c2 | CCS_FL_16BIT) + (n) * 2)
136 #define CCS_IMAGE_ORIENTATION_HORIZONTAL_MIRROR BIT(0)
137 #define CCS_IMAGE_ORIENTATION_VERTICAL_FLIP BIT(1)
150 #define CCS_2ND_CCI_IF_CTRL_ENABLE BIT(0)
151 #define CCS_2ND_CCI_IF_CTRL_ACK BIT(1)
155 #define CCS_CSI_SIGNALING_MODE_CSI_2_DPHY 2U
167 #define CCS_EMB_DATA_CTRL_RAW8_PACKING_FOR_RAW16 BIT(0)
168 #define CCS_EMB_DATA_CTRL_RAW10_PACKING_FOR_RAW20 BIT(1)
169 #define CCS_EMB_DATA_CTRL_RAW12_PACKING_FOR_RAW24 BIT(2)
173 #define CCS_TEMP_SENSOR_CTRL_ENABLE BIT(0)
185 #define CCS_HDR_MODE_ENABLED BIT(0)
186 #define CCS_HDR_MODE_SEPARATE_ANALOG_GAIN BIT(1)
187 #define CCS_HDR_MODE_UPSCALING BIT(2)
188 #define CCS_HDR_MODE_RESET_SYNC BIT(3)
189 #define CCS_HDR_MODE_TIMING_MODE BIT(4)
190 #define CCS_HDR_MODE_EXPOSURE_CTRL_DIRECT BIT(5)
191 #define CCS_HDR_MODE_SEPARATE_DIGITAL_GAIN BIT(6)
226 #define CCS_FRAME_LENGTH_CTRL_AUTOMATIC BIT(0)
228 #define CCS_TIMING_MODE_CTRL_MANUAL_READOUT BIT(0)
229 #define CCS_TIMING_MODE_CTRL_DELAYED_EXPOSURE BIT(1)
231 #define CCS_START_READOUT_RS_MANUAL_READOUT_START BIT(0)
254 #define CCS_TEST_PATTERN_MODE_COLOR_BARS 2U
275 #define CCS_PHY_CTRL_MANUAL 2U
286 #define CCS_DPHY_EQUALIZATION_MODE_EQ2 BIT(0)
288 #define CCS_PHY_EQUALIZATION_CTRL_ENABLE BIT(0)
290 #define CCS_DPHY_PREAMBLE_CTRL_ENABLE BIT(0)
293 #define CCS_PHY_SSC_CTRL_ENABLE BIT(0)
295 #define CCS_MANUAL_LP_CTRL_ENABLE BIT(0)
301 #define CCS_PHY_PERIODIC_CALIBRATION_CTRL_FRAME_BLANKING BIT(0)
304 #define CCS_PHY_INIT_CALIBRATION_CTRL_STREAM_START BIT(0)
306 #define CCS_DPHY_CALIBRATION_MODE_ALSO_ALTERNATE BIT(0)
310 #define CCS_CPHY_CALIBRATION_MODE_FORMAT_3 2U
319 #define CCS_TGR_PREAMBLE_LENGTH_PREAMABLE_PROG_SEQ BIT(7)
335 #define CCS_ALPS_CTRL_LVLP_DPHY BIT(0)
336 #define CCS_ALPS_CTRL_LVLP_CPHY BIT(1)
337 #define CCS_ALPS_CTRL_ALP_CPHY BIT(2)
345 #define CCS_SCRAMBLING_CTRL_ENABLED BIT(0)
346 #define CCS_SCRAMBLING_CTRL_SHIFT 2U
350 #define CCS_R_LANE_SEED_VALUE(seed, lane) ((0x0872 | CCS_FL_16BIT) + (seed) * 16 + (lane) * 2)
363 #define CCS_TX_USL_OPERATION_RESET BIT(0)
365 #define CCS_TX_USL_ALP_CTRL_CLOCK_PAUSE BIT(0)
369 #define CCS_USL_CLOCK_MODE_D_CTRL_CONT_CLOCK_STANDBY BIT(0)
370 #define CCS_USL_CLOCK_MODE_D_CTRL_CONT_CLOCK_VBLANK BIT(1)
371 #define CCS_USL_CLOCK_MODE_D_CTRL_CONT_CLOCK_HBLANK BIT(2)
376 #define CCS_DATA_TRANSFER_IF_1_CTRL_ENABLE BIT(0)
377 #define CCS_DATA_TRANSFER_IF_1_CTRL_WRITE BIT(1)
378 #define CCS_DATA_TRANSFER_IF_1_CTRL_CLEAR_ERROR BIT(2)
380 #define CCS_DATA_TRANSFER_IF_1_STATUS_READ_IF_READY BIT(0)
381 #define CCS_DATA_TRANSFER_IF_1_STATUS_WRITE_IF_READY BIT(1)
382 #define CCS_DATA_TRANSFER_IF_1_STATUS_DATA_CORRUPTED BIT(2)
383 #define CCS_DATA_TRANSFER_IF_1_STATUS_IMPROPER_IF_USAGE BIT(3)
389 #define CCS_SHADING_CORRECTION_EN_ENABLE BIT(0)
392 #define CCS_GREEN_IMBALANCE_FILTER_EN_ENABLE BIT(0)
394 #define CCS_MAPPED_DEFECT_CORRECT_EN_ENABLE BIT(0)
396 #define CCS_SINGLE_DEFECT_CORRECT_EN_ENABLE BIT(0)
398 #define CCS_DYNAMIC_COUPLET_CORRECT_EN_ENABLE BIT(0)
400 #define CCS_COMBINED_DEFECT_CORRECT_EN_ENABLE BIT(0)
402 #define CCS_MODULE_SPECIFIC_CORRECTION_EN_ENABLE BIT(0)
404 #define CCS_DYNAMIC_TRIPLET_DEFECT_CORRECT_EN_ENABLE BIT(0)
406 #define CCS_NF_CTRL_LUMA BIT(0)
407 #define CCS_NF_CTRL_CHROMA BIT(1)
408 #define CCS_NF_CTRL_COMBINED BIT(2)
410 #define CCS_OB_READOUT_CONTROL_ENABLE BIT(0)
411 #define CCS_OB_READOUT_CONTROL_INTERLEAVING BIT(1)
421 #define CCS_CFA_CONVERSION_CTRL_BAYER_CONVERSION_ENABLE BIT(0)
427 #define CCS_FLASH_MODE_RS_CONTINUOUS BIT(0)
428 #define CCS_FLASH_MODE_RS_TRUNCATE BIT(1)
429 #define CCS_FLASH_MODE_RS_ASYNC BIT(3)
432 #define CCS_FLASH_STATUS_RETIMED BIT(0)
434 #define CCS_SA_STROBE_MODE_CONTINUOUS BIT(0)
435 #define CCS_SA_STROBE_MODE_TRUNCATE BIT(1)
436 #define CCS_SA_STROBE_MODE_ASYNC BIT(3)
437 #define CCS_SA_STROBE_MODE_ADJUST_EDGE BIT(4)
443 #define CCS_SA_STROBE_STATUS_RETIMED BIT(0)
447 #define CCS_PDAF_CTRL_ENABLE BIT(0)
448 #define CCS_PDAF_CTRL_PROCESSED BIT(1)
449 #define CCS_PDAF_CTRL_INTERLEAVED BIT(2)
450 #define CCS_PDAF_CTRL_VISIBLE_PDAF_CORRECTION BIT(3)
459 #define CCS_BRACKETING_LUT_MODE_CONTINUE_STREAMING BIT(0)
460 #define CCS_BRACKETING_LUT_MODE_LOOP_MODE BIT(1)
466 #define CCS_INTEGRATION_TIME_CAPABILITY_FINE BIT(0)
473 #define CCS_DIGITAL_GAIN_CAPABILITY_GLOBAL 2U
479 #define CCS_ADC_CAPABILITY_BIT_DEPTH_CTRL BIT(0)
500 #define CCS_CLOCK_CALCULATION_LANE_SPEED BIT(0)
501 #define CCS_CLOCK_CALCULATION_LINK_DECOUPLED BIT(1)
502 #define CCS_CLOCK_CALCULATION_DUAL_PLL_OP_SYS_DDR BIT(2)
503 #define CCS_CLOCK_CALCULATION_DUAL_PLL_OP_PIX_DDR BIT(3)
515 #define CCS_TIMING_MODE_CAPABILITY_AUTO_FRAME_LENGTH BIT(0)
516 #define CCS_TIMING_MODE_CAPABILITY_ROLLING_SHUTTER_MANUAL_READOUT BIT(2)
517 #define CCS_TIMING_MODE_CAPABILITY_DELAYED_EXPOSURE_START BIT(3)
518 #define CCS_TIMING_MODE_CAPABILITY_MANUAL_EXPOSURE_EMBEDDED_DATA BIT(4)
549 #define CCS_NON_FLEXIBLE_RESOLUTION_SUPPORT_NEW_PIX_ADDR BIT(0)
550 #define CCS_NON_FLEXIBLE_RESOLUTION_SUPPORT_NEW_OUTPUT_RES BIT(1)
551 #define CCS_NON_FLEXIBLE_RESOLUTION_SUPPORT_OUTPUT_CROP_NO_PAD BIT(2)
552 #define CCS_NON_FLEXIBLE_RESOLUTION_SUPPORT_OUTPUT_SIZE_LANE_DEP BIT(3)
562 #define CCS_CLOCK_TREE_PLL_CAPABILITY_DUAL_PLL BIT(0)
563 #define CCS_CLOCK_TREE_PLL_CAPABILITY_SINGLE_PLL BIT(1)
564 #define CCS_CLOCK_TREE_PLL_CAPABILITY_EXT_DIVIDER BIT(2)
565 #define CCS_CLOCK_TREE_PLL_CAPABILITY_FLEXIBLE_OP_PIX_CLK_DIV BIT(3)
567 #define CCS_CLOCK_CAPA_TYPE_CAPABILITY_IREAL BIT(0)
573 #define CCS_AUX_SUBSAMP_CAPABILITY_FACTOR_POWER_OF_2 BIT(1)
575 #define CCS_AUX_SUBSAMP_MONO_CAPABILITY_FACTOR_POWER_OF_2 BIT(1)
582 #define CCS_PIXEL_READOUT_CAPABILITY_BAYER_AND_MONO 2U
598 #define CCS_SCALING_CAPABILITY_RESERVED 2U
607 #define CCS_HDR_CAPABILITY_1_2X2_BINNING BIT(0)
608 #define CCS_HDR_CAPABILITY_1_COMBINED_ANALOG_GAIN BIT(1)
609 #define CCS_HDR_CAPABILITY_1_SEPARATE_ANALOG_GAIN BIT(2)
610 #define CCS_HDR_CAPABILITY_1_UPSCALING BIT(3)
611 #define CCS_HDR_CAPABILITY_1_RESET_SYNC BIT(4)
612 #define CCS_HDR_CAPABILITY_1_DIRECT_SHORT_EXP_TIMING BIT(5)
613 #define CCS_HDR_CAPABILITY_1_DIRECT_SHORT_EXP_SYNTHESIS BIT(6)
624 #define CCS_HDR_CAPABILITY_2_COMBINED_DIGITAL_GAIN BIT(0)
625 #define CCS_HDR_CAPABILITY_2_SEPARATE_DIGITAL_GAIN BIT(1)
626 #define CCS_HDR_CAPABILITY_2_TIMING_MODE BIT(3)
627 #define CCS_HDR_CAPABILITY_2_SYNTHESIS_MODE BIT(4)
630 #define CCS_USL_SUPPORT_CAPABILITY_CLOCK_TREE BIT(0)
631 #define CCS_USL_SUPPORT_CAPABILITY_REV_CLOCK_TREE BIT(1)
632 #define CCS_USL_SUPPORT_CAPABILITY_REV_CLOCK_CALC BIT(2)
634 #define CCS_USL_CLOCK_MODE_D_CAPABILITY_CONT_CLOCK_STANDBY BIT(0)
635 #define CCS_USL_CLOCK_MODE_D_CAPABILITY_CONT_CLOCK_VBLANK BIT(1)
636 #define CCS_USL_CLOCK_MODE_D_CAPABILITY_CONT_CLOCK_HBLANK BIT(2)
637 #define CCS_USL_CLOCK_MODE_D_CAPABILITY_NONCONT_CLOCK_STANDBY BIT(3)
638 #define CCS_USL_CLOCK_MODE_D_CAPABILITY_NONCONT_CLOCK_VBLANK BIT(4)
639 #define CCS_USL_CLOCK_MODE_D_CAPABILITY_NONCONT_CLOCK_HBLANK BIT(5)
651 #define CCS_COMPRESSION_CAPABILITY_DPCM_PCM_SIMPLE BIT(0)
653 #define CCS_TEST_MODE_CAPABILITY_SOLID_COLOR BIT(0)
654 #define CCS_TEST_MODE_CAPABILITY_COLOR_BARS BIT(1)
655 #define CCS_TEST_MODE_CAPABILITY_FADE_TO_GREY BIT(2)
656 #define CCS_TEST_MODE_CAPABILITY_PN9 BIT(3)
657 #define CCS_TEST_MODE_CAPABILITY_COLOR_TILE BIT(5)
665 #define CCS_PN9_MISC_CAPABILITY_COMPRESSION BIT(3)
667 #define CCS_TEST_PATTERN_CAPABILITY_NO_REPEAT BIT(1)
672 #define CCS_FIFO_SUPPORT_CAPABILITY_DERATING_OVERRATING 2U
674 #define CCS_PHY_CTRL_CAPABILITY_AUTO_PHY_CTL BIT(0)
675 #define CCS_PHY_CTRL_CAPABILITY_UI_PHY_CTL BIT(1)
676 #define CCS_PHY_CTRL_CAPABILITY_DPHY_TIME_UI_REG_1_CTL BIT(2)
677 #define CCS_PHY_CTRL_CAPABILITY_DPHY_TIME_UI_REG_2_CTL BIT(3)
678 #define CCS_PHY_CTRL_CAPABILITY_DPHY_TIME_CTL BIT(4)
679 #define CCS_PHY_CTRL_CAPABILITY_DPHY_EXT_TIME_UI_REG_1_CTL BIT(5)
680 #define CCS_PHY_CTRL_CAPABILITY_DPHY_EXT_TIME_UI_REG_2_CTL BIT(6)
681 #define CCS_PHY_CTRL_CAPABILITY_DPHY_EXT_TIME_CTL BIT(7)
683 #define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_1_LANE BIT(0)
684 #define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_2_LANE BIT(1)
685 #define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_3_LANE BIT(2)
686 #define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_4_LANE BIT(3)
687 #define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_5_LANE BIT(4)
688 #define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_6_LANE BIT(5)
689 #define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_7_LANE BIT(6)
690 #define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_8_LANE BIT(7)
692 #define CCS_CSI_SIGNALING_MODE_CAPABILITY_CSI_DPHY BIT(2)
693 #define CCS_CSI_SIGNALING_MODE_CAPABILITY_CSI_CPHY BIT(3)
698 #define CCS_CSI_ADDRESS_CONTROL_CAPABILITY_CCI_ADDR_CHANGE BIT(0)
699 #define CCS_CSI_ADDRESS_CONTROL_CAPABILITY_2ND_CCI_ADDR BIT(1)
700 #define CCS_CSI_ADDRESS_CONTROL_CAPABILITY_SW_CHANGEABLE_2ND_CCI_ADDR BIT(2)
702 #define CCS_DATA_TYPE_CAPABILITY_DPCM_PROGRAMMABLE BIT(0)
703 #define CCS_DATA_TYPE_CAPABILITY_BOTTOM_EMBEDDED_DT_PROGRAMMABLE BIT(1)
704 #define CCS_DATA_TYPE_CAPABILITY_BOTTOM_EMBEDDED_VC_PROGRAMMABLE BIT(2)
705 #define CCS_DATA_TYPE_CAPABILITY_EXT_VC_RANGE BIT(3)
707 #define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_1_LANE BIT(0)
708 #define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_2_LANE BIT(1)
709 #define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_3_LANE BIT(2)
710 #define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_4_LANE BIT(3)
711 #define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_5_LANE BIT(4)
712 #define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_6_LANE BIT(5)
713 #define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_7_LANE BIT(6)
714 #define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_8_LANE BIT(7)
716 #define CCS_EMB_DATA_CAPABILITY_TWO_BYTES_PER_RAW16 BIT(0)
717 #define CCS_EMB_DATA_CAPABILITY_TWO_BYTES_PER_RAW20 BIT(1)
718 #define CCS_EMB_DATA_CAPABILITY_TWO_BYTES_PER_RAW24 BIT(2)
719 #define CCS_EMB_DATA_CAPABILITY_NO_ONE_BYTE_PER_RAW16 BIT(3)
720 #define CCS_EMB_DATA_CAPABILITY_NO_ONE_BYTE_PER_RAW20 BIT(4)
721 #define CCS_EMB_DATA_CAPABILITY_NO_ONE_BYTE_PER_RAW24 BIT(5)
722 …DE_MBPS(n) ((0x1608 | (CCS_FL_32BIT | CCS_FL_IREAL)) + ((n) < 4 ? (n) * 4 : 0x32 + ((n) - 4) * 4))
726 #define CCS_TEMP_SENSOR_CAPABILITY_SUPPORTED BIT(0)
727 #define CCS_TEMP_SENSOR_CAPABILITY_CCS_FORMAT BIT(1)
728 #define CCS_TEMP_SENSOR_CAPABILITY_RESET_0X80 BIT(2)
729 …DE_MBPS(n) ((0x161a | (CCS_FL_32BIT | CCS_FL_IREAL)) + ((n) < 4 ? (n) * 4 : 0x30 + ((n) - 4) * 4))
733 #define CCS_DPHY_EQUALIZATION_CAPABILITY_EQUALIZATION_CTRL BIT(0)
734 #define CCS_DPHY_EQUALIZATION_CAPABILITY_EQ1 BIT(1)
735 #define CCS_DPHY_EQUALIZATION_CAPABILITY_EQ2 BIT(2)
737 #define CCS_CPHY_EQUALIZATION_CAPABILITY_EQUALIZATION_CTRL BIT(0)
739 #define CCS_DPHY_PREAMBLE_CAPABILITY_PREAMBLE_SEQ_CTRL BIT(0)
741 #define CCS_DPHY_SSC_CAPABILITY_SUPPORTED BIT(0)
743 #define CCS_CPHY_CALIBRATION_CAPABILITY_MANUAL BIT(0)
744 #define CCS_CPHY_CALIBRATION_CAPABILITY_MANUAL_STREAMING BIT(1)
745 #define CCS_CPHY_CALIBRATION_CAPABILITY_FORMAT_1_CTRL BIT(2)
746 #define CCS_CPHY_CALIBRATION_CAPABILITY_FORMAT_2_CTRL BIT(3)
747 #define CCS_CPHY_CALIBRATION_CAPABILITY_FORMAT_3_CTRL BIT(4)
749 #define CCS_DPHY_CALIBRATION_CAPABILITY_MANUAL BIT(0)
750 #define CCS_DPHY_CALIBRATION_CAPABILITY_MANUAL_STREAMING BIT(1)
751 #define CCS_DPHY_CALIBRATION_CAPABILITY_ALTERNATE_SEQ BIT(2)
753 #define CCS_PHY_CTRL_CAPABILITY_2_TGR_LENGTH BIT(0)
754 #define CCS_PHY_CTRL_CAPABILITY_2_TGR_PREAMBLE_PROG_SEQ BIT(1)
755 #define CCS_PHY_CTRL_CAPABILITY_2_EXTRA_CPHY_MANUAL_TIMING BIT(2)
756 #define CCS_PHY_CTRL_CAPABILITY_2_CLOCK_BASED_MANUAL_CDPHY BIT(3)
757 #define CCS_PHY_CTRL_CAPABILITY_2_CLOCK_BASED_MANUAL_DPHY BIT(4)
758 #define CCS_PHY_CTRL_CAPABILITY_2_CLOCK_BASED_MANUAL_CPHY BIT(5)
759 #define CCS_PHY_CTRL_CAPABILITY_2_MANUAL_LP_DPHY BIT(6)
760 #define CCS_PHY_CTRL_CAPABILITY_2_MANUAL_LP_CPHY BIT(7)
762 #define CCS_LRTE_CPHY_CAPABILITY_PDQ_SHORT BIT(0)
763 #define CCS_LRTE_CPHY_CAPABILITY_SPACER_SHORT BIT(1)
764 #define CCS_LRTE_CPHY_CAPABILITY_PDQ_LONG BIT(2)
765 #define CCS_LRTE_CPHY_CAPABILITY_SPACER_LONG BIT(3)
766 #define CCS_LRTE_CPHY_CAPABILITY_SPACER_NO_PDQ BIT(4)
768 #define CCS_LRTE_DPHY_CAPABILITY_PDQ_SHORT_OPT1 BIT(0)
769 #define CCS_LRTE_DPHY_CAPABILITY_SPACER_SHORT_OPT1 BIT(1)
770 #define CCS_LRTE_DPHY_CAPABILITY_PDQ_LONG_OPT1 BIT(2)
771 #define CCS_LRTE_DPHY_CAPABILITY_SPACER_LONG_OPT1 BIT(3)
772 #define CCS_LRTE_DPHY_CAPABILITY_SPACER_SHORT_OPT2 BIT(4)
773 #define CCS_LRTE_DPHY_CAPABILITY_SPACER_LONG_OPT2 BIT(5)
774 #define CCS_LRTE_DPHY_CAPABILITY_SPACER_NO_PDQ_OPT1 BIT(6)
775 #define CCS_LRTE_DPHY_CAPABILITY_SPACER_VARIABLE_OPT2 BIT(7)
779 #define CCS_ALPS_CAPABILITY_DPHY_CONTROLLABLE_LVLP 2U
783 #define CCS_ALPS_CAPABILITY_CPHY_CONTROLLABLE_LVLP 2U
788 #define CCS_SCRAMBLING_CAPABILITY_SCRAMBLING_SUPPORTED BIT(0)
798 #define CCS_SCRAMBLING_CAPABILITY_NUM_SEED_PER_LANE BIT(6)
802 #define CCS_CSI2_INTERFACE_CAPABILITY_MISC_EOTP_SHORT_PKT_OPT2 BIT(0)
804 #define CCS_PHY_CTRL_CAPABILITY_3_DPHY_TIMING_NOT_MULTIPLE BIT(0)
805 #define CCS_PHY_CTRL_CAPABILITY_3_DPHY_MIN_TIMING_VALUE_1 BIT(1)
806 #define CCS_PHY_CTRL_CAPABILITY_3_TWAKEUP_SUPPORTED BIT(2)
807 #define CCS_PHY_CTRL_CAPABILITY_3_TINIT_SUPPORTED BIT(3)
808 #define CCS_PHY_CTRL_CAPABILITY_3_THS_EXIT_SUPPORTED BIT(4)
809 #define CCS_PHY_CTRL_CAPABILITY_3_CPHY_TIMING_NOT_MULTIPLE BIT(5)
810 #define CCS_PHY_CTRL_CAPABILITY_3_CPHY_MIN_TIMING_VALUE_1 BIT(6)
868 #define CCS_BINNING_CAPABILITY_SUBSAMPLING_THEN_BINNING 2U
870 #define CCS_BINNING_WEIGHTING_CAPABILITY_AVERAGED BIT(0)
871 #define CCS_BINNING_WEIGHTING_CAPABILITY_SUMMED BIT(1)
872 #define CCS_BINNING_WEIGHTING_CAPABILITY_BAYER_CORRECTED BIT(2)
873 #define CCS_BINNING_WEIGHTING_CAPABILITY_MODULE_SPECIFIC_WEIGHT BIT(3)
883 #define CCS_BINNING_WEIGHTING_MONO_CAPABILITY_AVERAGED BIT(0)
884 #define CCS_BINNING_WEIGHTING_MONO_CAPABILITY_SUMMED BIT(1)
885 #define CCS_BINNING_WEIGHTING_MONO_CAPABILITY_BAYER_CORRECTED BIT(2)
886 #define CCS_BINNING_WEIGHTING_MONO_CAPABILITY_MODULE_SPECIFIC_WEIGHT BIT(3)
892 #define CCS_DATA_TRANSFER_IF_CAPABILITY_SUPPORTED BIT(0)
893 #define CCS_DATA_TRANSFER_IF_CAPABILITY_POLLING BIT(2)
895 #define CCS_SHADING_CORRECTION_CAPABILITY_COLOR_SHADING BIT(0)
896 #define CCS_SHADING_CORRECTION_CAPABILITY_LUMINANCE_CORRECTION BIT(1)
898 #define CCS_GREEN_IMBALANCE_CAPABILITY_SUPPORTED BIT(0)
901 #define CCS_DEFECT_CORRECTION_CAPABILITY_MAPPED_DEFECT BIT(0)
902 #define CCS_DEFECT_CORRECTION_CAPABILITY_DYNAMIC_COUPLET BIT(2)
903 #define CCS_DEFECT_CORRECTION_CAPABILITY_DYNAMIC_SINGLE BIT(5)
904 #define CCS_DEFECT_CORRECTION_CAPABILITY_COMBINED_DYNAMIC BIT(8)
906 #define CCS_DEFECT_CORRECTION_CAPABILITY_2_DYNAMIC_TRIPLET BIT(3)
908 #define CCS_NF_CAPABILITY_LUMA BIT(0)
909 #define CCS_NF_CAPABILITY_CHROMA BIT(1)
910 #define CCS_NF_CAPABILITY_COMBINED BIT(2)
912 #define CCS_OB_READOUT_CAPABILITY_CONTROLLABLE_READOUT BIT(0)
913 #define CCS_OB_READOUT_CAPABILITY_VISIBLE_PIXEL_READOUT BIT(1)
914 #define CCS_OB_READOUT_CAPABILITY_DIFFERENT_VC_READOUT BIT(2)
915 #define CCS_OB_READOUT_CAPABILITY_DIFFERENT_DT_READOUT BIT(3)
916 #define CCS_OB_READOUT_CAPABILITY_PROG_DATA_FORMAT BIT(4)
918 #define CCS_COLOR_FEEDBACK_CAPABILITY_KELVIN BIT(0)
919 #define CCS_COLOR_FEEDBACK_CAPABILITY_AWB_GAIN BIT(1)
923 #define CCS_CFA_PATTERN_CAPABILITY_4X4_QUAD_BAYER 2U
926 #define CCS_CFA_PATTERN_CONVERSION_CAPABILITY_BAYER BIT(0)
928 #define CCS_FLASH_MODE_CAPABILITY_SINGLE_STROBE BIT(0)
930 #define CCS_SA_STROBE_MODE_CAPABILITY_FIXED_WIDTH BIT(0)
931 #define CCS_SA_STROBE_MODE_CAPABILITY_EDGE_CTRL BIT(1)
935 #define CCS_PDAF_CAPABILITY_1_SUPPORTED BIT(0)
936 #define CCS_PDAF_CAPABILITY_1_PROCESSED_BOTTOM_EMBEDDED BIT(1)
937 #define CCS_PDAF_CAPABILITY_1_PROCESSED_INTERLEAVED BIT(2)
938 #define CCS_PDAF_CAPABILITY_1_RAW_BOTTOM_EMBEDDED BIT(3)
939 #define CCS_PDAF_CAPABILITY_1_RAW_INTERLEAVED BIT(4)
940 #define CCS_PDAF_CAPABILITY_1_VISIBLE_PDAF_CORRECTION BIT(5)
941 #define CCS_PDAF_CAPABILITY_1_VC_INTERLEAVING BIT(6)
942 #define CCS_PDAF_CAPABILITY_1_DT_INTERLEAVING BIT(7)
944 #define CCS_PDAF_CAPABILITY_2_ROI BIT(0)
945 #define CCS_PDAF_CAPABILITY_2_AFTER_DIGITAL_CROP BIT(1)
946 #define CCS_PDAF_CAPABILITY_2_CTRL_RETIMED BIT(2)
948 #define CCS_BRACKETING_LUT_CAPABILITY_1_COARSE_INTEGRATION BIT(0)
949 #define CCS_BRACKETING_LUT_CAPABILITY_1_GLOBAL_ANALOG_GAIN BIT(1)
950 #define CCS_BRACKETING_LUT_CAPABILITY_1_FLASH BIT(4)
951 #define CCS_BRACKETING_LUT_CAPABILITY_1_GLOBAL_DIGITAL_GAIN BIT(5)
952 #define CCS_BRACKETING_LUT_CAPABILITY_1_ALTERNATE_GLOBAL_ANALOG_GAIN BIT(6)
954 #define CCS_BRACKETING_LUT_CAPABILITY_2_SINGLE_BRACKETING_MODE BIT(0)
955 #define CCS_BRACKETING_LUT_CAPABILITY_2_LOOPED_BRACKETING_MODE BIT(1)