25 #define ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM		0x0
26 #define ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM_PED		0x1
27 #define ADV7180_STD_AD_PAL_N_NTSC_J_SECAM		0x2
28 #define ADV7180_STD_AD_PAL_N_NTSC_M_SECAM		0x3
29 #define ADV7180_STD_NTSC_J				0x4
30 #define ADV7180_STD_NTSC_M				0x5
31 #define ADV7180_STD_PAL60				0x6
32 #define ADV7180_STD_NTSC_443				0x7
33 #define ADV7180_STD_PAL_BG				0x8
34 #define ADV7180_STD_PAL_N				0x9
35 #define ADV7180_STD_PAL_M				0xa
36 #define ADV7180_STD_PAL_M_PED				0xb
37 #define ADV7180_STD_PAL_COMB_N				0xc
38 #define ADV7180_STD_PAL_COMB_N_PED			0xd
39 #define ADV7180_STD_PAL_SECAM				0xe
40 #define ADV7180_STD_PAL_SECAM_PED			0xf
42 #define ADV7180_REG_INPUT_CONTROL			0x0000
43 #define ADV7180_INPUT_CONTROL_INSEL_MASK		0x0f
45 #define ADV7182_REG_INPUT_VIDSEL			0x0002
47 #define ADV7180_REG_OUTPUT_CONTROL			0x0003
48 #define ADV7180_REG_EXTENDED_OUTPUT_CONTROL		0x0004
49 #define ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS		0xC5
51 #define ADV7180_REG_AUTODETECT_ENABLE			0x0007
52 #define ADV7180_AUTODETECT_DEFAULT			0x7f
54 #define ADV7180_REG_CON		0x0008	/*Unsigned */
55 #define ADV7180_CON_MIN		0
59 #define ADV7180_REG_BRI		0x000a	/*Signed */
61 #define ADV7180_BRI_DEF		0
64 #define ADV7180_REG_HUE		0x000b	/*Signed, inverted */
66 #define ADV7180_HUE_DEF		0
69 #define ADV7180_REG_CTRL		0x000e
70 #define ADV7180_CTRL_IRQ_SPACE		0x20
72 #define ADV7180_REG_PWR_MAN		0x0f
73 #define ADV7180_PWR_MAN_ON		0x04
74 #define ADV7180_PWR_MAN_OFF		0x24
75 #define ADV7180_PWR_MAN_RES		0x80
77 #define ADV7180_REG_STATUS1		0x0010
78 #define ADV7180_STATUS1_IN_LOCK		0x01
79 #define ADV7180_STATUS1_AUTOD_MASK	0x70
80 #define ADV7180_STATUS1_AUTOD_NTSM_M_J	0x00
81 #define ADV7180_STATUS1_AUTOD_NTSC_4_43 0x10
82 #define ADV7180_STATUS1_AUTOD_PAL_M	0x20
83 #define ADV7180_STATUS1_AUTOD_PAL_60	0x30
84 #define ADV7180_STATUS1_AUTOD_PAL_B_G	0x40
85 #define ADV7180_STATUS1_AUTOD_SECAM	0x50
86 #define ADV7180_STATUS1_AUTOD_PAL_COMB	0x60
87 #define ADV7180_STATUS1_AUTOD_SECAM_525	0x70
89 #define ADV7180_REG_IDENT 0x0011
90 #define ADV7180_ID_7180 0x18
92 #define ADV7180_REG_STATUS3		0x0013
93 #define ADV7180_REG_ANALOG_CLAMP_CTL	0x0014
94 #define ADV7180_REG_SHAP_FILTER_CTL_1	0x0017
95 #define ADV7180_REG_CTRL_2		0x001d
96 #define ADV7180_REG_VSYNC_FIELD_CTL_1	0x0031
97 #define ADV7180_VSYNC_FIELD_CTL_1_NEWAV 0x12
98 #define ADV7180_REG_MANUAL_WIN_CTL_1	0x003d
99 #define ADV7180_REG_MANUAL_WIN_CTL_2	0x003e
100 #define ADV7180_REG_MANUAL_WIN_CTL_3	0x003f
101 #define ADV7180_REG_LOCK_CNT		0x0051
102 #define ADV7180_REG_CVBS_TRIM		0x0052
103 #define ADV7180_REG_CLAMP_ADJ		0x005a
104 #define ADV7180_REG_RES_CIR		0x005f
105 #define ADV7180_REG_DIFF_MODE		0x0060
107 #define ADV7180_REG_ICONF1		0x2040
108 #define ADV7180_ICONF1_ACTIVE_LOW	0x01
109 #define ADV7180_ICONF1_PSYNC_ONLY	0x10
110 #define ADV7180_ICONF1_ACTIVE_TO_CLR	0xC0
112 #define ADV7180_REG_SD_SAT_CB	0x00e3	/*Unsigned */
113 #define ADV7180_REG_SD_SAT_CR	0x00e4	/*Unsigned */
114 #define ADV7180_SAT_MIN		0
118 #define ADV7180_IRQ1_LOCK	0x01
119 #define ADV7180_IRQ1_UNLOCK	0x02
120 #define ADV7180_REG_ISR1	0x2042
121 #define ADV7180_REG_ICR1	0x2043
122 #define ADV7180_REG_IMR1	0x2044
123 #define ADV7180_REG_IMR2	0x2048
124 #define ADV7180_IRQ3_AD_CHANGE	0x08
125 #define ADV7180_REG_ISR3	0x204A
126 #define ADV7180_REG_ICR3	0x204B
127 #define ADV7180_REG_IMR3	0x204C
128 #define ADV7180_REG_IMR4	0x2050
130 #define ADV7180_REG_NTSC_V_BIT_END	0x00E6
131 #define ADV7180_NTSC_V_BIT_END_MANUAL_NVEND	0x4F
133 #define ADV7180_REG_VPP_SLAVE_ADDR	0xFD
134 #define ADV7180_REG_CSI_SLAVE_ADDR	0xFE
136 #define ADV7180_REG_ACE_CTRL1		0x4080
137 #define ADV7180_REG_ACE_CTRL5		0x4084
138 #define ADV7180_REG_FLCONTROL		0x40e0
139 #define ADV7180_FLCONTROL_FL_ENABLE 0x1
141 #define ADV7180_REG_RST_CLAMP	0x809c
142 #define ADV7180_REG_AGC_ADJ1	0x80b6
143 #define ADV7180_REG_AGC_ADJ2	0x80c0
145 #define ADV7180_CSI_REG_PWRDN	0x00
146 #define ADV7180_CSI_PWRDN	0x80
148 #define ADV7180_INPUT_CVBS_AIN1 0x00
149 #define ADV7180_INPUT_CVBS_AIN2 0x01
150 #define ADV7180_INPUT_CVBS_AIN3 0x02
151 #define ADV7180_INPUT_CVBS_AIN4 0x03
152 #define ADV7180_INPUT_CVBS_AIN5 0x04
153 #define ADV7180_INPUT_CVBS_AIN6 0x05
154 #define ADV7180_INPUT_SVIDEO_AIN1_AIN2 0x06
155 #define ADV7180_INPUT_SVIDEO_AIN3_AIN4 0x07
156 #define ADV7180_INPUT_SVIDEO_AIN5_AIN6 0x08
157 #define ADV7180_INPUT_YPRPB_AIN1_AIN2_AIN3 0x09
158 #define ADV7180_INPUT_YPRPB_AIN4_AIN5_AIN6 0x0a
160 #define ADV7182_INPUT_CVBS_AIN1 0x00
161 #define ADV7182_INPUT_CVBS_AIN2 0x01
162 #define ADV7182_INPUT_CVBS_AIN3 0x02
163 #define ADV7182_INPUT_CVBS_AIN4 0x03
164 #define ADV7182_INPUT_CVBS_AIN5 0x04
165 #define ADV7182_INPUT_CVBS_AIN6 0x05
166 #define ADV7182_INPUT_CVBS_AIN7 0x06
167 #define ADV7182_INPUT_CVBS_AIN8 0x07
168 #define ADV7182_INPUT_SVIDEO_AIN1_AIN2 0x08
169 #define ADV7182_INPUT_SVIDEO_AIN3_AIN4 0x09
170 #define ADV7182_INPUT_SVIDEO_AIN5_AIN6 0x0a
171 #define ADV7182_INPUT_SVIDEO_AIN7_AIN8 0x0b
172 #define ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3 0x0c
173 #define ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6 0x0d
174 #define ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2 0x0e
175 #define ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4 0x0f
176 #define ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6 0x10
177 #define ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8 0x11
179 #define ADV7180_DEFAULT_CSI_I2C_ADDR 0x44
180 #define ADV7180_DEFAULT_VPP_I2C_ADDR 0x42
182 #define V4L2_CID_ADV_FAST_SWITCH	(V4L2_CID_USER_ADV7180_BASE + 0x00)
189 #define ADV7180_FLAG_RESET_POWERED	BIT(0)
235 	return 0;  in adv7180_select_page()
243 	return i2c_smbus_write_byte_data(state->client, reg & 0xff, value);  in adv7180_write()
250 	return i2c_smbus_read_byte_data(state->client, reg & 0xff);  in adv7180_read()
327 	return 0;  in adv7180_status_to_v4l2()
335 	if (status1 < 0)  in __adv7180_status()
343 	return 0;  in __adv7180_status()
372 	if (err < 0)  in adv7180_querystd()
398 	if (ret == 0)  in adv7180_s_routing()
422 	if (ret < 0)  in adv7180_program_std()
426 	if (ret < 0)  in adv7180_program_std()
428 	return 0;  in adv7180_program_std()
441 	if (ret < 0)  in adv7180_s_std()
458 	return 0;  in adv7180_g_std()
474 	return 0;  in adv7180_g_frame_interval()
483 		gpiod_set_value_cansleep(state->pwdn_gpio, 0);  in adv7180_set_power_pin()
498 		gpiod_set_value_cansleep(state->rst_gpio, 0);  in adv7180_set_reset_pin()
519 			adv7180_csi_write(state, 0xDE, 0x02);  in adv7180_set_power()
520 			adv7180_csi_write(state, 0xD2, 0xF7);  in adv7180_set_power()
521 			adv7180_csi_write(state, 0xD8, 0x65);  in adv7180_set_power()
522 			adv7180_csi_write(state, 0xE0, 0x09);  in adv7180_set_power()
523 			adv7180_csi_write(state, 0x2C, 0x00);  in adv7180_set_power()
525 				adv7180_csi_write(state, 0x1D, 0x80);  in adv7180_set_power()
526 			adv7180_csi_write(state, 0x00, 0x00);  in adv7180_set_power()
528 			adv7180_csi_write(state, 0x00, 0x80);  in adv7180_set_power()
532 	return 0;  in adv7180_set_power()
545 	if (ret == 0)  in adv7180_s_power()
579 		if (ret < 0)  in adv7180_s_ctrl()
586 			adv7180_write(state, 0x80d9, 0x44);  in adv7180_s_ctrl()
591 			adv7180_write(state, 0x80d9, 0xc4);  in adv7180_s_ctrl()
592 			adv7180_write(state, ADV7180_REG_FLCONTROL, 0x00);  in adv7180_s_ctrl()
612 	.min = 0,
644 	return 0;  in adv7180_init_controls()
655 	if (code->index != 0)  in adv7180_enum_mbus_code()
660 	return 0;  in adv7180_enum_mbus_code()
676 	return 0;  in adv7180_mbus_fmt()
682 		return 0;  in adv7180_set_field_mode()
686 			adv7180_csi_write(state, 0x01, 0x20);  in adv7180_set_field_mode()
687 			adv7180_csi_write(state, 0x02, 0x28);  in adv7180_set_field_mode()
688 			adv7180_csi_write(state, 0x03, 0x38);  in adv7180_set_field_mode()
689 			adv7180_csi_write(state, 0x04, 0x30);  in adv7180_set_field_mode()
690 			adv7180_csi_write(state, 0x05, 0x30);  in adv7180_set_field_mode()
691 			adv7180_csi_write(state, 0x06, 0x80);  in adv7180_set_field_mode()
692 			adv7180_csi_write(state, 0x07, 0x70);  in adv7180_set_field_mode()
693 			adv7180_csi_write(state, 0x08, 0x50);  in adv7180_set_field_mode()
695 		adv7180_vpp_write(state, 0xa3, 0x00);  in adv7180_set_field_mode()
696 		adv7180_vpp_write(state, 0x5b, 0x00);  in adv7180_set_field_mode()
697 		adv7180_vpp_write(state, 0x55, 0x80);  in adv7180_set_field_mode()
700 			adv7180_csi_write(state, 0x01, 0x18);  in adv7180_set_field_mode()
701 			adv7180_csi_write(state, 0x02, 0x18);  in adv7180_set_field_mode()
702 			adv7180_csi_write(state, 0x03, 0x30);  in adv7180_set_field_mode()
703 			adv7180_csi_write(state, 0x04, 0x20);  in adv7180_set_field_mode()
704 			adv7180_csi_write(state, 0x05, 0x28);  in adv7180_set_field_mode()
705 			adv7180_csi_write(state, 0x06, 0x40);  in adv7180_set_field_mode()
706 			adv7180_csi_write(state, 0x07, 0x58);  in adv7180_set_field_mode()
707 			adv7180_csi_write(state, 0x08, 0x30);  in adv7180_set_field_mode()
709 		adv7180_vpp_write(state, 0xa3, 0x70);  in adv7180_set_field_mode()
710 		adv7180_vpp_write(state, 0x5b, 0x80);  in adv7180_set_field_mode()
711 		adv7180_vpp_write(state, 0x55, 0x00);  in adv7180_set_field_mode()
714 	return 0;  in adv7180_set_field_mode()
724 		format->format = *v4l2_subdev_get_try_format(sd, sd_state, 0);  in adv7180_get_pad_format()
730 	return 0;  in adv7180_get_pad_format()
761 		framefmt = v4l2_subdev_get_try_format(sd, sd_state, 0);  in adv7180_set_pad_format()
800 	return 0;  in adv7180_get_mbus_config()
807 	return 0;  in adv7180_get_skip_frames()
822 	return 0;  in adv7180_g_pixelaspect()
828 	return 0;  in adv7180_g_tvnorms()
839 		return 0;  in adv7180_s_stream()
848 	return 0;  in adv7180_s_stream()
932 	if (ret < 0)  in adv7180_init()
951 	if (ret < 0)  in adv7180_select_input()
971 		adv7180_write(state, 0x0080, 0x51);  in adv7182_init()
972 		adv7180_write(state, 0x0081, 0x51);  in adv7182_init()
973 		adv7180_write(state, 0x0082, 0x68);  in adv7182_init()
978 		adv7180_write(state, ADV7180_REG_OUTPUT_CONTROL, 0x4e);  in adv7182_init()
979 		adv7180_write(state, ADV7180_REG_EXTENDED_OUTPUT_CONTROL, 0x57);  in adv7182_init()
980 		adv7180_write(state, ADV7180_REG_CTRL_2, 0xc0);  in adv7182_init()
999 					      0x17);  in adv7182_init()
1005 				      0x07);  in adv7182_init()
1006 		adv7180_write(state, ADV7180_REG_OUTPUT_CONTROL, 0x0c);  in adv7182_init()
1007 		adv7180_write(state, ADV7180_REG_CTRL_2, 0x40);  in adv7182_init()
1010 	adv7180_write(state, 0x0013, 0x00);  in adv7182_init()
1012 	return 0;  in adv7182_init()
1053 		return 0;  in adv7182_get_input_type()
1057 /* ADI recommended writes to registers 0x52, 0x53, 0x54 */
1059 	[ADV7182_INPUT_TYPE_CVBS] = { 0xCB, 0x4E, 0x80 },
1060 	[ADV7182_INPUT_TYPE_DIFF_CVBS] = { 0xC0, 0x4E, 0x80 },
1061 	[ADV7182_INPUT_TYPE_SVIDEO] = { 0x0B, 0xCE, 0x80 },
1062 	[ADV7182_INPUT_TYPE_YPBPR] = { 0x0B, 0x4E, 0xC0 },
1066 	[ADV7182_INPUT_TYPE_CVBS] = { 0xCD, 0x4E, 0x80 },
1067 	[ADV7182_INPUT_TYPE_DIFF_CVBS] = { 0xC0, 0x4E, 0x80 },
1068 	[ADV7182_INPUT_TYPE_SVIDEO] = { 0x0B, 0xCE, 0x80 },
1069 	[ADV7182_INPUT_TYPE_YPBPR] = { 0x0B, 0x4E, 0xC0 },
1084 	adv7180_write(state, ADV7180_REG_RST_CLAMP, 0x00);  in adv7182_select_input()
1085 	adv7180_write(state, ADV7180_REG_RST_CLAMP, 0xff);  in adv7182_select_input()
1093 		adv7180_write(state, ADV7180_REG_SHAP_FILTER_CTL_1, 0x41);  in adv7182_select_input()
1096 		adv7180_write(state, ADV7180_REG_SHAP_FILTER_CTL_1, 0x01);  in adv7182_select_input()
1105 	for (i = 0; i < ARRAY_SIZE(adv7182_lbias_settings[0]); i++)  in adv7182_select_input()
1110 		adv7180_write(state, ADV7180_REG_RES_CIR, 0xa8);  in adv7182_select_input()
1111 		adv7180_write(state, ADV7180_REG_CLAMP_ADJ, 0x90);  in adv7182_select_input()
1112 		adv7180_write(state, ADV7180_REG_DIFF_MODE, 0xb0);  in adv7182_select_input()
1113 		adv7180_write(state, ADV7180_REG_AGC_ADJ1, 0x08);  in adv7182_select_input()
1114 		adv7180_write(state, ADV7180_REG_AGC_ADJ2, 0xa0);  in adv7182_select_input()
1116 		adv7180_write(state, ADV7180_REG_RES_CIR, 0xf0);  in adv7182_select_input()
1117 		adv7180_write(state, ADV7180_REG_CLAMP_ADJ, 0xd0);  in adv7182_select_input()
1118 		adv7180_write(state, ADV7180_REG_DIFF_MODE, 0x10);  in adv7182_select_input()
1119 		adv7180_write(state, ADV7180_REG_AGC_ADJ1, 0x9c);  in adv7182_select_input()
1120 		adv7180_write(state, ADV7180_REG_AGC_ADJ2, 0x00);  in adv7182_select_input()
1123 	return 0;  in adv7182_select_input()
1314 	if (state->irq > 0) {  in init_device()
1319 		if (ret < 0)  in init_device()
1322 		ret = adv7180_write(state, ADV7180_REG_IMR1, 0);  in init_device()
1323 		if (ret < 0)  in init_device()
1326 		ret = adv7180_write(state, ADV7180_REG_IMR2, 0);  in init_device()
1327 		if (ret < 0)  in init_device()
1333 		if (ret < 0)  in init_device()
1336 		ret = adv7180_write(state, ADV7180_REG_IMR4, 0);  in init_device()
1337 		if (ret < 0)  in init_device()
1409 	state->input = 0;  in adv7180_probe()
1443 	if (ret < 0)  in adv7180_probe()
1446 	v4l_info(client, "chip id 0x%x found @ 0x%02x (%s)\n",  in adv7180_probe()
1449 	return 0;  in adv7180_probe()
1454 	if (state->irq > 0)  in adv7180_probe()
1475 	if (state->irq > 0)  in adv7180_remove()
1489 	return 0;  in adv7180_remove()
1524 	if (ret < 0)  in adv7180_resume()
1531 	return 0;  in adv7180_resume()