Lines Matching +full:0 +full:x7090
23 MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
27 MODULE_PARM_DESC(buggy_sfn_workaround, "Enable work-around for buggy SFNs (default: 0)");
33 } while (0)
67 #define SOC7090 0x7090
89 DIB7000P_POWER_ALL = 0,
104 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) { in dib7000p_read_word()
106 return 0; in dib7000p_read_word()
109 state->i2c_write_buffer[0] = reg >> 8; in dib7000p_read_word()
110 state->i2c_write_buffer[1] = reg & 0xff; in dib7000p_read_word()
112 memset(state->msg, 0, 2 * sizeof(struct i2c_msg)); in dib7000p_read_word()
113 state->msg[0].addr = state->i2c_addr >> 1; in dib7000p_read_word()
114 state->msg[0].flags = 0; in dib7000p_read_word()
115 state->msg[0].buf = state->i2c_write_buffer; in dib7000p_read_word()
116 state->msg[0].len = 2; in dib7000p_read_word()
125 ret = (state->i2c_read_buffer[0] << 8) | state->i2c_read_buffer[1]; in dib7000p_read_word()
134 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) { in dib7000p_write_word()
139 state->i2c_write_buffer[0] = (reg >> 8) & 0xff; in dib7000p_write_word()
140 state->i2c_write_buffer[1] = reg & 0xff; in dib7000p_write_word()
141 state->i2c_write_buffer[2] = (val >> 8) & 0xff; in dib7000p_write_word()
142 state->i2c_write_buffer[3] = val & 0xff; in dib7000p_write_word()
144 memset(&state->msg[0], 0, sizeof(struct i2c_msg)); in dib7000p_write_word()
145 state->msg[0].addr = state->i2c_addr >> 1; in dib7000p_write_word()
146 state->msg[0].flags = 0; in dib7000p_write_word()
147 state->msg[0].buf = state->i2c_write_buffer; in dib7000p_write_word()
148 state->msg[0].len = 4; in dib7000p_write_word()
151 -EREMOTEIO : 0); in dib7000p_write_word()
158 u16 l = 0, r, *n; in dib7000p_write_tab()
174 int ret = 0; in dib7000p_set_output_mode()
177 outreg = 0; in dib7000p_set_output_mode()
179 smo_mode = (dib7000p_read_word(state, 235) & 0x0050) | (1 << 1); in dib7000p_set_output_mode()
185 outreg = (1 << 10); /* 0x0400 */ in dib7000p_set_output_mode()
188 outreg = (1 << 10) | (1 << 6); /* 0x0440 */ in dib7000p_set_output_mode()
191 outreg = (1 << 10) | (2 << 6) | (0 << 1); /* 0x0480 */ in dib7000p_set_output_mode()
195 outreg = (1 << 10) | (4 << 6); /* 0x0500 */ in dib7000p_set_output_mode()
208 outreg = 0; in dib7000p_set_output_mode()
232 onoff = 0; in dib7000p_set_diversity_in()
233 dib7000p_write_word(state, 207, 0); in dib7000p_set_diversity_in()
235 dib7000p_write_word(state, 207, (state->div_sync_wait << 4) | (1 << 2) | (2 << 0)); in dib7000p_set_diversity_in()
242 /* P_dvsy_sync_mode = 0, P_dvsy_sync_enable=1, P_dvcb_comb_mode=2 */ in dib7000p_set_diversity_in()
245 dib7000p_write_word(state, 205, 0); in dib7000p_set_diversity_in()
248 return 0; in dib7000p_set_diversity_in()
254 …u16 reg_774 = 0x3fff, reg_775 = 0xffff, reg_776 = 0x0007, reg_899 = 0x0003, reg_1280 = (0xfe00) | … in dib7000p_set_power_mode()
260 reg_774 = 0x0000; in dib7000p_set_power_mode()
261 reg_775 = 0x0000; in dib7000p_set_power_mode()
262 reg_776 = 0x0; in dib7000p_set_power_mode()
263 reg_899 = 0x0; in dib7000p_set_power_mode()
265 reg_1280 &= 0x001f; in dib7000p_set_power_mode()
267 reg_1280 &= 0x01ff; in dib7000p_set_power_mode()
274 reg_776 &= ~((1 << 0)); in dib7000p_set_power_mode()
299 return 0; in dib7000p_set_power_mode()
304 u16 reg_908 = 0, reg_909 = 0; in dib7000p_set_adc_state()
321 dib7000p_write_word(state, 1925, reg & ~(1 << 4)); /* en_slowAdc = 1 & reset_sladc = 0 */ in dib7000p_set_adc_state()
323 reg = dib7000p_read_word(state, 72) & ~((0x3 << 14) | (0x3 << 12)); in dib7000p_set_adc_state()
326 reg_909 |= (1 << 1) | (1 << 0); in dib7000p_set_adc_state()
335 …ib7000p_write_word(state, 1925, (reg & ~(1 << 2)) | (1 << 4)); /* reset_sladc = 1 en_slowAdc = 0 */ in dib7000p_set_adc_state()
337 reg_909 |= (1 << 1) | (1 << 0); in dib7000p_set_adc_state()
341 reg_908 &= 0x0fff; in dib7000p_set_adc_state()
342 reg_909 &= 0x0003; in dib7000p_set_adc_state()
380 if (state->timf == 0) { in dib7000p_set_bandwidth()
390 dib7000p_write_word(state, 23, (u16) ((timf >> 16) & 0xffff)); in dib7000p_set_bandwidth()
391 dib7000p_write_word(state, 24, (u16) ((timf) & 0xffff)); in dib7000p_set_bandwidth()
393 return 0; in dib7000p_set_bandwidth()
399 dib7000p_write_word(state, 73, (0 << 1) | (0 << 0)); in dib7000p_sad_calib()
407 dib7000p_write_word(state, 73, (1 << 0)); in dib7000p_sad_calib()
408 dib7000p_write_word(state, 73, (0 << 0)); in dib7000p_sad_calib()
412 return 0; in dib7000p_sad_calib()
421 return dib7000p_write_word(state, 105, (dib7000p_read_word(state, 105) & 0xf000) | value); in dib7000p_set_wbd_ref()
438 return 0; in dib7000p_get_agc_values()
449 struct dibx000_bandwidth_config *bw = &state->cfg.bw[0]; in dib7000p_reset_pll()
455 while (((dib7000p_read_word(state, 1856) >> 15) & 0x1) != 1) in dib7000p_reset_pll()
461 clk_cfg0 = (1 << 15) | ((bw->pll_ratio & 0x3f) << 9) | in dib7000p_reset_pll()
462 …rc << 6) | (bw->IO_CLK_en_core << 5) | (bw->bypclk_div << 2) | (bw->enable_refdiv << 1) | (0 << 0); in dib7000p_reset_pll()
467 …dib7000p_write_word(state, 903, (bw->pll_prediv << 5) | (((bw->pll_ratio >> 6) & 0x3) << 3) | (bw-… in dib7000p_reset_pll()
468 clk_cfg0 = (bw->pll_bypass << 15) | (clk_cfg0 & 0x7fff); in dib7000p_reset_pll()
472 dib7000p_write_word(state, 18, (u16) (((bw->internal * 1000) >> 16) & 0xffff)); in dib7000p_reset_pll()
473 dib7000p_write_word(state, 19, (u16) ((bw->internal * 1000) & 0xffff)); in dib7000p_reset_pll()
474 dib7000p_write_word(state, 21, (u16) ((bw->ifreq >> 16) & 0xffff)); in dib7000p_reset_pll()
475 dib7000p_write_word(state, 22, (u16) ((bw->ifreq) & 0xffff)); in dib7000p_reset_pll()
497 prediv = reg_1856 & 0x3f; in dib7000p_update_pll()
498 loopdiv = (reg_1856 >> 6) & 0x3f; in dib7000p_update_pll()
502 reg_1856 &= 0xf000; in dib7000p_update_pll()
506 …dib7000p_write_word(state, 1856, reg_1856 | ((bw->pll_ratio & 0x3f) << 6) | (bw->pll_prediv & 0x3f… in dib7000p_update_pll()
512 dib7000p_write_word(state, 18, (u16) ((internal >> 16) & 0xffff)); in dib7000p_update_pll()
513 dib7000p_write_word(state, 19, (u16) (internal & 0xffff)); in dib7000p_update_pll()
517 while (((dib7000p_read_word(state, 1856) >> 15) & 0x1) != 1) in dib7000p_update_pll()
520 return 0; in dib7000p_update_pll()
538 return 0; in dib7000p_reset_gpio()
545 st->gpio_dir |= (dir & 0x1) << num; /* set the new direction */ in dib7000p_cfg_gpio()
550 st->gpio_val |= (val & 0x01) << num; /* set the new value */ in dib7000p_cfg_gpio()
553 return 0; in dib7000p_cfg_gpio()
565 0x0004,
567 0x0814, /* Equal Lock */
570 0x001b,
571 0x7740,
572 0x005b,
573 0x8d80,
574 0x01c9,
575 0xc380,
576 0x0000,
577 0x0080,
578 0x0000,
579 0x0090,
580 0x0001,
581 0xd4c0,
584 0x6680,
601 0x0410,
605 0,
606 0,
607 0,
608 0,
609 0,
610 0,
611 0,
612 0,
618 0x0ccd,
621 0x200f,
624 0x169,
627 0x023d,
628 0x00a4,
629 0x00a4,
630 0x7ff0,
631 0x3ccc,
634 0x800,
637 0x0010,
640 0x0062,
642 0,
657 dib7000p_write_word(state, 770, 0xffff); in dib7000p_demod_reset()
658 dib7000p_write_word(state, 771, 0xffff); in dib7000p_demod_reset()
659 dib7000p_write_word(state, 772, 0x001f); in dib7000p_demod_reset()
660 dib7000p_write_word(state, 1280, 0x001f - ((1 << 4) | (1 << 3))); in dib7000p_demod_reset()
662 dib7000p_write_word(state, 770, 0); in dib7000p_demod_reset()
663 dib7000p_write_word(state, 771, 0); in dib7000p_demod_reset()
664 dib7000p_write_word(state, 772, 0); in dib7000p_demod_reset()
665 dib7000p_write_word(state, 1280, 0); in dib7000p_demod_reset()
668 dib7000p_write_word(state, 898, 0x0003); in dib7000p_demod_reset()
669 dib7000p_write_word(state, 898, 0); in dib7000p_demod_reset()
675 if (dib7000p_reset_gpio(state) != 0) in dib7000p_demod_reset()
679 dib7000p_write_word(state, 899, 0); in dib7000p_demod_reset()
683 dib7000p_write_word(state, 43, 0x2d4); /*-300 fag P_iqc_dect_min = -280 */ in dib7000p_demod_reset()
685 dib7000p_write_word(state, 273, (0<<6) | 30); in dib7000p_demod_reset()
687 if (dib7000p_set_output_mode(state, OUTMODE_HIGH_Z) != 0) in dib7000p_demod_reset()
700 …dib7000p_write_word(state, 36, 0x0755);/* P_iqc_impnc_on =1 & P_iqc_corr_inh = 1 for impulsive noi… in dib7000p_demod_reset()
703 dib7000p_write_word(state, 36, 0x0755); in dib7000p_demod_reset()
705 dib7000p_write_word(state, 36, 0x1f55); in dib7000p_demod_reset()
710 dib7000p_write_word(state, 901, 0x0006); in dib7000p_demod_reset()
712 dib7000p_write_word(state, 905, 0x2c8e); in dib7000p_demod_reset()
717 return 0; in dib7000p_demod_reset()
722 u16 tmp = 0; in dib7000p_pll_clk_cfg()
724 dib7000p_write_word(state, 903, (tmp | 0x1)); in dib7000p_pll_clk_cfg()
726 dib7000p_write_word(state, 900, (tmp & 0x7fff) | (1 << 6)); in dib7000p_pll_clk_cfg()
733 dib7000p_write_word(state, 770, 0x0000); in dib7000p_restart_agc()
748 return 0; in dib7000p_update_lna()
756 return 0; in dib7000p_set_agc_config()
759 for (i = 0; i < state->cfg.agc_config_count; i++) in dib7000p_set_agc_config()
766 dprintk("no valid AGC configuration found for band 0x%02x\n", band); in dib7000p_set_agc_config()
784 …state->wbd_ref != 0 ? state->wbd_ref : agc->wbd_ref, agc->wbd_sel, !agc->perform_agc_softsplit, ag… in dib7000p_set_agc_config()
786 if (state->wbd_ref != 0) in dib7000p_set_agc_config()
802 return 0; in dib7000p_set_agc_config()
810 u32 dds = state->cfg.bw->ifreq & 0x1ffffff; in dib7000p_set_dds()
812 if (internal == 0) { in dib7000p_set_dds()
813 pr_warn("DIB7000P: dib7000p_get_internal_freq returned 0\n"); in dib7000p_set_dds()
821 if (offset_khz < 0) in dib7000p_set_dds()
831 dib7000p_write_word(state, 21, (u16) (((dds >> 16) & 0x1ff) | (0 << 10) | (invert << 9))); in dib7000p_set_dds()
832 dib7000p_write_word(state, 22, (u16) (dds & 0xffff)); in dib7000p_set_dds()
834 return 0; in dib7000p_set_dds()
845 u32 upd_demod_gain_period = 0x1000; in dib7000p_agc_startup()
846 s32 frequency_offset = 0; in dib7000p_agc_startup()
849 case 0: in dib7000p_agc_startup()
852 reg = dib7000p_read_word(state, 0x79b) & 0xff00; in dib7000p_agc_startup()
853 dib7000p_write_word(state, 0x79a, upd_demod_gain_period & 0xFFFF); /* lsb */ in dib7000p_agc_startup()
854 dib7000p_write_word(state, 0x79b, reg | (1 << 14) | ((upd_demod_gain_period >> 16) & 0xFF)); in dib7000p_agc_startup()
857 reg = dib7000p_read_word(state, 0x780); in dib7000p_agc_startup()
858 dib7000p_write_word(state, 0x780, (reg | (0x3)) & (~(1 << 7))); in dib7000p_agc_startup()
864 if (dib7000p_set_agc_config(state, BAND_OF_FREQUENCY(ch->frequency / 1000)) != 0) in dib7000p_agc_startup()
874 if (dib7000p_set_dds(state, frequency_offset) < 0) in dib7000p_agc_startup()
888 /* force 0 split on WBD and restart AGC */ in dib7000p_agc_startup()
904 …dib7000p_write_word(state, 106, (state->current_agc->wbd_sel << 13) | (2 << 9) | (0 << 8)); /* fas… in dib7000p_agc_startup()
935 state->cfg.agc_control(&state->demod, 0); in dib7000p_agc_startup()
949 dib7000p_write_word(state, 24, (u16) (timf & 0xffff)); in dib7000p_update_timf()
979 value = 0; in dib7000p_set_channel()
982 value |= (0 << 7); in dib7000p_set_channel()
994 value |= (0 << 5); in dib7000p_set_channel()
1009 value |= (0 << 3); in dib7000p_set_channel()
1031 dib7000p_write_word(state, 0, value); in dib7000p_set_channel()
1032 dib7000p_write_word(state, 5, (seq << 4) | 1); /* do not force tps, search list 0 */ in dib7000p_set_channel()
1035 value = 0; in dib7000p_set_channel()
1036 if (1 != 0) in dib7000p_set_channel()
1042 switch ((ch->hierarchy == 0 || 1 == 1) ? ch->code_rate_HP : ch->code_rate_LP) { in dib7000p_set_channel()
1063 dib7000p_write_word(state, 26, 0x6680); in dib7000p_set_channel()
1064 dib7000p_write_word(state, 32, 0x0003); in dib7000p_set_channel()
1065 dib7000p_write_word(state, 29, 0x1273); in dib7000p_set_channel()
1066 dib7000p_write_word(state, 33, 0x0005); in dib7000p_set_channel()
1096 if (state->cfg.diversity_delay == 0) in dib7000p_set_channel()
1108 est[0] = 0x0148; /* P_adp_regul_cnt 0.04 */ in dib7000p_set_channel()
1109 est[1] = 0xfff0; /* P_adp_noise_cnt -0.002 */ in dib7000p_set_channel()
1110 est[2] = 0x00a4; /* P_adp_regul_ext 0.02 */ in dib7000p_set_channel()
1111 est[3] = 0xfff8; /* P_adp_noise_ext -0.001 */ in dib7000p_set_channel()
1114 est[0] = 0x023d; /* P_adp_regul_cnt 0.07 */ in dib7000p_set_channel()
1115 est[1] = 0xffdf; /* P_adp_noise_cnt -0.004 */ in dib7000p_set_channel()
1116 est[2] = 0x00a4; /* P_adp_regul_ext 0.02 */ in dib7000p_set_channel()
1117 est[3] = 0xfff0; /* P_adp_noise_ext -0.002 */ in dib7000p_set_channel()
1120 est[0] = 0x099a; /* P_adp_regul_cnt 0.3 */ in dib7000p_set_channel()
1121 est[1] = 0xffae; /* P_adp_noise_cnt -0.01 */ in dib7000p_set_channel()
1122 est[2] = 0x0333; /* P_adp_regul_ext 0.1 */ in dib7000p_set_channel()
1123 est[3] = 0xfff8; /* P_adp_noise_ext -0.002 */ in dib7000p_set_channel()
1126 for (value = 0; value < 4; value++) in dib7000p_set_channel()
1144 schan.hierarchy = 0; in dib7000p_autosearch_start()
1158 dib7000p_write_word(state, 6, (u16) ((value >> 16) & 0xffff)); in dib7000p_autosearch_start()
1159 dib7000p_write_word(state, 7, (u16) (value & 0xffff)); in dib7000p_autosearch_start()
1161 dib7000p_write_word(state, 8, (u16) ((value >> 16) & 0xffff)); in dib7000p_autosearch_start()
1162 dib7000p_write_word(state, 9, (u16) (value & 0xffff)); in dib7000p_autosearch_start()
1164 dib7000p_write_word(state, 10, (u16) ((value >> 16) & 0xffff)); in dib7000p_autosearch_start()
1165 dib7000p_write_word(state, 11, (u16) (value & 0xffff)); in dib7000p_autosearch_start()
1167 value = dib7000p_read_word(state, 0); in dib7000p_autosearch_start()
1168 dib7000p_write_word(state, 0, (u16) ((1 << 9) | value)); in dib7000p_autosearch_start()
1170 dib7000p_write_word(state, 0, (u16) value); in dib7000p_autosearch_start()
1172 return 0; in dib7000p_autosearch_start()
1180 if (irq_pending & 0x1) in dib7000p_autosearch_is_irq()
1183 if (irq_pending & 0x2) in dib7000p_autosearch_is_irq()
1186 return 0; in dib7000p_autosearch_is_irq()
1192 static u8 sine[] = { 0, 2, 3, 5, 6, 8, 9, 11, 13, 14, 16, 17, 19, 20, 22, in dib7000p_spur_protect()
1225 dib7000p_write_word(state, 142, 0x0610); in dib7000p_spur_protect()
1227 for (k = 0; k < 8; k++) { in dib7000p_spur_protect()
1228 pha = ((f_rel * (k + 1) * 112 * 80 / bw_khz) / 1000) & 0x3ff; in dib7000p_spur_protect()
1230 if (pha == 0) { in dib7000p_spur_protect()
1232 coef_im[k] = 0; in dib7000p_spur_protect()
1234 coef_re[k] = sine[256 - (pha & 0xff)]; in dib7000p_spur_protect()
1235 coef_im[k] = sine[pha & 0xff]; in dib7000p_spur_protect()
1237 coef_re[k] = 0; in dib7000p_spur_protect()
1240 coef_re[k] = -sine[pha & 0xff]; in dib7000p_spur_protect()
1241 coef_im[k] = sine[256 - (pha & 0xff)]; in dib7000p_spur_protect()
1244 coef_im[k] = 0; in dib7000p_spur_protect()
1246 coef_re[k] = -sine[256 - (pha & 0xff)]; in dib7000p_spur_protect()
1247 coef_im[k] = -sine[pha & 0xff]; in dib7000p_spur_protect()
1249 coef_re[k] = 0; in dib7000p_spur_protect()
1252 coef_re[k] = sine[pha & 0xff]; in dib7000p_spur_protect()
1253 coef_im[k] = -sine[256 - (pha & 0xff)]; in dib7000p_spur_protect()
1270 dib7000p_write_word(state, 143, (0 << 14) | (k << 10) | (coef_re[k] & 0x3ff)); in dib7000p_spur_protect()
1271 dib7000p_write_word(state, 144, coef_im[k] & 0x3ff); in dib7000p_spur_protect()
1272 dib7000p_write_word(state, 143, (1 << 14) | (k << 10) | (coef_re[k] & 0x3ff)); in dib7000p_spur_protect()
1274 dib7000p_write_word(state, 143, 0); in dib7000p_spur_protect()
1281 u16 tmp = 0; in dib7000p_tune()
1284 dib7000p_set_channel(state, ch, 0); in dib7000p_tune()
1289 dib7000p_write_word(state, 770, 0x4000); in dib7000p_tune()
1290 dib7000p_write_word(state, 770, 0x0000); in dib7000p_tune()
1293 …/* P_ctrl_inh_cor=0, P_ctrl_alpha_cor=4, P_ctrl_inh_isi=0, P_ctrl_alpha_isi=3, P_ctrl_inh_cor4=1, … in dib7000p_tune()
1294 tmp = (0 << 14) | (4 << 10) | (0 << 9) | (3 << 5) | (1 << 4) | (0x3); in dib7000p_tune()
1298 dib7000p_write_word(state, 166, 0x4000); in dib7000p_tune()
1300 dib7000p_write_word(state, 166, 0x0000); in dib7000p_tune()
1305 if (state->timf == 0) in dib7000p_tune()
1310 /* P_timf_alpha, P_corm_alpha=6, P_corm_thres=0x80 */ in dib7000p_tune()
1311 tmp = (6 << 8) | 0x80; in dib7000p_tune()
1326 /* P_ctrl_freeze_pha_shift=0, P_ctrl_pha_off_max */ in dib7000p_tune()
1327 tmp = (0 << 4); in dib7000p_tune()
1330 tmp |= 0x6; in dib7000p_tune()
1333 tmp |= 0x7; in dib7000p_tune()
1337 tmp |= 0x8; in dib7000p_tune()
1342 /* P_ctrl_sfreq_inh=0, P_ctrl_sfreq_step */ in dib7000p_tune()
1343 tmp = (0 << 4); in dib7000p_tune()
1346 tmp |= 0x6; in dib7000p_tune()
1349 tmp |= 0x7; in dib7000p_tune()
1353 tmp |= 0x8; in dib7000p_tune()
1359 if (!((tmp >> 6) & 0x1)) { in dib7000p_tune()
1368 if ((tmp >> 6) & 0x1) { in dib7000p_tune()
1372 dib7000p_write_word(state, 26, (tmp & ~(0xf << 12)) | ((((tmp >> 12) & 0xf) + 5) << 12)); in dib7000p_tune()
1382 return 0; in dib7000p_tune()
1392 return 0; in dib7000p_wakeup()
1408 if ((value = dib7000p_read_word(st, 768)) != 0x01b3) { in dib7000p_identify()
1409 dprintk("wrong Vendor ID (read=0x%x)\n", value); in dib7000p_identify()
1413 if ((value = dib7000p_read_word(st, 769)) != 0x4000) { in dib7000p_identify()
1418 return 0; in dib7000p_identify()
1431 switch ((tps >> 8) & 0x3) { in dib7000p_get_frontend()
1432 case 0: in dib7000p_get_frontend()
1441 switch (tps & 0x3) { in dib7000p_get_frontend()
1442 case 0: in dib7000p_get_frontend()
1456 switch ((tps >> 14) & 0x3) { in dib7000p_get_frontend()
1457 case 0: in dib7000p_get_frontend()
1470 /* (tps >> 13) & 0x1 == hrch is used, (tps >> 10) & 0x7 == alpha */ in dib7000p_get_frontend()
1473 switch ((tps >> 5) & 0x7) { in dib7000p_get_frontend()
1493 switch ((tps >> 2) & 0x7) { in dib7000p_get_frontend()
1512 /* native interleaver: (dib7000p_read_word(state, 464) >> 5) & 0x1 */ in dib7000p_get_frontend()
1514 return 0; in dib7000p_get_frontend()
1524 dib7090_set_diversity_in(fe, 0); in dib7000p_set_frontend()
1535 state->agc_state = 0; in dib7000p_set_frontend()
1550 } while (found == 0 && i--); in dib7000p_set_frontend()
1553 if (found == 0 || found == 1) in dib7000p_set_frontend()
1554 return 0; in dib7000p_set_frontend()
1564 if (state->cfg.enMpegOutput == 0) { in dib7000p_set_frontend()
1581 *stat = 0; in dib7000p_read_status()
1583 if (lock & 0x8000) in dib7000p_read_status()
1585 if (lock & 0x3000) in dib7000p_read_status()
1587 if (lock & 0x0100) in dib7000p_read_status()
1589 if (lock & 0x0010) in dib7000p_read_status()
1591 if ((lock & 0x0038) == 0x38) in dib7000p_read_status()
1596 return 0; in dib7000p_read_status()
1603 return 0; in dib7000p_read_ber()
1610 return 0; in dib7000p_read_unc_blocks()
1618 return 0; in dib7000p_read_signal_strength()
1626 u32 result = 0; in dib7000p_get_snr()
1629 noise_mant = (val >> 4) & 0xff; in dib7000p_get_snr()
1630 noise_exp = ((val & 0xf) << 2); in dib7000p_get_snr()
1632 noise_exp += ((val >> 14) & 0x3); in dib7000p_get_snr()
1633 if ((noise_exp & 0x20) != 0) in dib7000p_get_snr()
1634 noise_exp -= 0x40; in dib7000p_get_snr()
1636 signal_mant = (val >> 6) & 0xFF; in dib7000p_get_snr()
1637 signal_exp = (val & 0x3F); in dib7000p_get_snr()
1638 if ((signal_exp & 0x20) != 0) in dib7000p_get_snr()
1639 signal_exp -= 0x40; in dib7000p_get_snr()
1641 if (signal_mant != 0) in dib7000p_get_snr()
1646 if (noise_mant != 0) in dib7000p_get_snr()
1661 return 0; in dib7000p_read_snr()
1670 memset(&c->strength, 0, sizeof(c->strength)); in dib7000p_reset_stats()
1671 memset(&c->cnr, 0, sizeof(c->cnr)); in dib7000p_reset_stats()
1672 memset(&c->post_bit_error, 0, sizeof(c->post_bit_error)); in dib7000p_reset_stats()
1673 memset(&c->post_bit_count, 0, sizeof(c->post_bit_count)); in dib7000p_reset_stats()
1674 memset(&c->block_error, 0, sizeof(c->block_error)); in dib7000p_reset_stats()
1683 c->strength.stat[0].scale = FE_SCALE_DECIBEL; in dib7000p_reset_stats()
1684 c->strength.stat[0].uvalue = 0; in dib7000p_reset_stats()
1686 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in dib7000p_reset_stats()
1687 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in dib7000p_reset_stats()
1688 c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in dib7000p_reset_stats()
1689 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in dib7000p_reset_stats()
1690 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in dib7000p_reset_stats()
1695 state->ber_jiffies_stats = 0; in dib7000p_reset_stats()
1696 state->per_jiffies_stats = 0; in dib7000p_reset_stats()
1759 { 0, 0},
1770 if (value >= segments[0].x) in interpolate_value()
1771 return segments[0].y; in interpolate_value()
1802 int interleaving = 0, fft_div; in dib7000p_get_time_us()
1847 switch ((c->hierarchy == 0 || 1 == 1) ? c->code_rate_HP : c->code_rate_LP) { in dib7000p_get_time_us()
1880 return 0; in dib7000p_get_time_us()
1900 int show_per_stats = 0; in dib7000p_get_stats()
1901 u32 time_us = 0, val, snr; in dib7000p_get_stats()
1912 c->strength.stat[0].svalue = db; in dib7000p_get_stats()
1921 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in dib7000p_get_stats()
1922 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in dib7000p_get_stats()
1923 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in dib7000p_get_stats()
1924 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in dib7000p_get_stats()
1925 c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in dib7000p_get_stats()
1926 return 0; in dib7000p_get_stats()
1938 snr = 0; in dib7000p_get_stats()
1939 c->cnr.stat[0].svalue = snr; in dib7000p_get_stats()
1940 c->cnr.stat[0].scale = FE_SCALE_DECIBEL; in dib7000p_get_stats()
1946 ucb += 0x100000000LL; in dib7000p_get_stats()
1948 c->block_error.stat[0].scale = FE_SCALE_COUNTER; in dib7000p_get_stats()
1949 c->block_error.stat[0].uvalue = ucb; in dib7000p_get_stats()
1958 c->block_count.stat[0].scale = FE_SCALE_COUNTER; in dib7000p_get_stats()
1959 c->block_count.stat[0].uvalue += blocks; in dib7000p_get_stats()
1973 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER; in dib7000p_get_stats()
1974 c->post_bit_error.stat[0].uvalue += val; in dib7000p_get_stats()
1976 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; in dib7000p_get_stats()
1977 c->post_bit_count.stat[0].uvalue += 100000000; in dib7000p_get_stats()
1984 c->block_error.stat[0].scale = FE_SCALE_COUNTER; in dib7000p_get_stats()
1985 c->block_error.stat[0].uvalue += val; in dib7000p_get_stats()
1991 c->block_count.stat[0].scale = FE_SCALE_COUNTER; in dib7000p_get_stats()
1992 c->block_count.stat[0].uvalue += blocks; in dib7000p_get_stats()
1995 return 0; in dib7000p_get_stats()
2001 return 0; in dib7000p_fe_get_tune_settings()
2016 {.addr = 18 >> 1, .flags = 0, .len = 2}, in dib7000pc_detection()
2019 int ret = 0; in dib7000pc_detection()
2030 msg[0].buf = tx; in dib7000pc_detection()
2033 tx[0] = 0x03; in dib7000pc_detection()
2034 tx[1] = 0x00; in dib7000pc_detection()
2037 if (rx[0] == 0x01 && rx[1] == 0xb3) { in dib7000pc_detection()
2043 msg[0].addr = msg[1].addr = 0x40; in dib7000pc_detection()
2046 if (rx[0] == 0x01 && rx[1] == 0xb3) { in dib7000pc_detection()
2070 u16 val = dib7000p_read_word(state, 235) & 0xffef; in dib7000p_pid_filter_ctrl()
2071 val |= (onoff & 0x1) << 4; in dib7000p_pid_filter_ctrl()
2080 return dib7000p_write_word(state, 241 + id, onoff ? (1 << 13) | pid : 0); in dib7000p_pid_filter()
2086 int k = 0; in dib7000p_i2c_enumeration()
2087 u8 new_addr = 0; in dib7000p_i2c_enumeration()
2096 for (k = no_of_demods - 1; k >= 0; k--) { in dib7000p_i2c_enumeration()
2100 if (cfg[k].default_i2c_addr != 0) in dib7000p_i2c_enumeration()
2103 new_addr = (0x40 + k) << 1; in dib7000p_i2c_enumeration()
2105 dib7000p_write_word(dpst, 1287, 0x0003); /* sram lead in, rdy */ in dib7000p_i2c_enumeration()
2106 if (dib7000p_identify(dpst) != 0) { in dib7000p_i2c_enumeration()
2108 dib7000p_write_word(dpst, 1287, 0x0003); /* sram lead in, rdy */ in dib7000p_i2c_enumeration()
2109 if (dib7000p_identify(dpst) != 0) { in dib7000p_i2c_enumeration()
2120 dib7000p_write_word(dpst, 1285, (new_addr << 2) | 0x2); in dib7000p_i2c_enumeration()
2122 dprintk("IC %d initialized (to i2c_address 0x%x)\n", k, new_addr); in dib7000p_i2c_enumeration()
2125 for (k = 0; k < no_of_demods; k++) { in dib7000p_i2c_enumeration()
2127 if (cfg[k].default_i2c_addr != 0) in dib7000p_i2c_enumeration()
2130 dpst->i2c_addr = (0x40 + k) << 1; in dib7000p_i2c_enumeration()
2140 return 0; in dib7000p_i2c_enumeration()
2150 u32 tmp_val = 0, exp = 0, mant = 0; in dib7000p_get_adc_power()
2153 u8 ix = 0; in dib7000p_get_adc_power()
2155 buf[0] = dib7000p_read_word(state, 0x184); in dib7000p_get_adc_power()
2156 buf[1] = dib7000p_read_word(state, 0x185); in dib7000p_get_adc_power()
2157 pow_i = (buf[0] << 16) | buf[1]; in dib7000p_get_adc_power()
2179 if ((msg->buf[0] <= 15)) in map_addr_to_serpar_number()
2180 msg->buf[0] -= 1; in map_addr_to_serpar_number()
2181 else if (msg->buf[0] == 17) in map_addr_to_serpar_number()
2182 msg->buf[0] = 15; in map_addr_to_serpar_number()
2183 else if (msg->buf[0] == 16) in map_addr_to_serpar_number()
2184 msg->buf[0] = 17; in map_addr_to_serpar_number()
2185 else if (msg->buf[0] == 19) in map_addr_to_serpar_number()
2186 msg->buf[0] = 16; in map_addr_to_serpar_number()
2187 else if (msg->buf[0] >= 21 && msg->buf[0] <= 25) in map_addr_to_serpar_number()
2188 msg->buf[0] -= 3; in map_addr_to_serpar_number()
2189 else if (msg->buf[0] == 28) in map_addr_to_serpar_number()
2190 msg->buf[0] = 23; in map_addr_to_serpar_number()
2193 return 0; in map_addr_to_serpar_number()
2201 u16 serpar_num = msg[0].buf[0]; in w7090p_tuner_write_serpar()
2204 n_overflow = (dib7000p_read_word(state, 1984) >> 1) & 0x1; in w7090p_tuner_write_serpar()
2206 if (i == 0) in w7090p_tuner_write_serpar()
2209 dib7000p_write_word(state, 1985, (1 << 6) | (serpar_num & 0x3f)); in w7090p_tuner_write_serpar()
2210 dib7000p_write_word(state, 1986, (msg[0].buf[1] << 8) | msg[0].buf[2]); in w7090p_tuner_write_serpar()
2220 u16 serpar_num = msg[0].buf[0]; in w7090p_tuner_read_serpar()
2224 n_overflow = (dib7000p_read_word(state, 1984) >> 1) & 0x1; in w7090p_tuner_read_serpar()
2226 if (i == 0) in w7090p_tuner_read_serpar()
2229 dib7000p_write_word(state, 1985, (0 << 6) | (serpar_num & 0x3f)); in w7090p_tuner_read_serpar()
2233 n_empty = dib7000p_read_word(state, 1984) & 0x1; in w7090p_tuner_read_serpar()
2235 if (i == 0) in w7090p_tuner_read_serpar()
2239 msg[1].buf[0] = (read_word >> 8) & 0xff; in w7090p_tuner_read_serpar()
2240 msg[1].buf[1] = (read_word) & 0xff; in w7090p_tuner_read_serpar()
2247 …if (map_addr_to_serpar_number(&msg[0]) == 0) { /* else = Tuner regs to ignore : DIG_CFG, CTRL_RF_L… in w7090p_tuner_rw_serpar()
2264 dib7000p_write_word(state, apb_address, ((msg[0].buf[1] << 8) | (msg[0].buf[2]))); in dib7090p_rw_on_apb()
2267 msg[1].buf[0] = (word >> 8) & 0xff; in dib7090p_rw_on_apb()
2268 msg[1].buf[1] = (word) & 0xff; in dib7090p_rw_on_apb()
2278 u16 apb_address = 0, word; in dib7090_tuner_xfer()
2279 int i = 0; in dib7090_tuner_xfer()
2280 switch (msg[0].buf[0]) { in dib7090_tuner_xfer()
2281 case 0x12: in dib7090_tuner_xfer()
2284 case 0x14: in dib7090_tuner_xfer()
2287 case 0x24: in dib7090_tuner_xfer()
2290 case 0x1a: in dib7090_tuner_xfer()
2293 case 0x22: in dib7090_tuner_xfer()
2296 case 0x33: in dib7090_tuner_xfer()
2299 case 0x34: in dib7090_tuner_xfer()
2302 case 0x35: in dib7090_tuner_xfer()
2305 case 0x36: in dib7090_tuner_xfer()
2308 case 0x37: in dib7090_tuner_xfer()
2311 case 0x38: in dib7090_tuner_xfer()
2314 case 0x39: in dib7090_tuner_xfer()
2317 case 0x2a: in dib7090_tuner_xfer()
2320 case 0x2b: in dib7090_tuner_xfer()
2323 case 0x2c: in dib7090_tuner_xfer()
2326 case 0x2d: in dib7090_tuner_xfer()
2329 case 0x2e: in dib7090_tuner_xfer()
2332 case 0x2f: in dib7090_tuner_xfer()
2335 case 0x30: in dib7090_tuner_xfer()
2338 case 0x31: in dib7090_tuner_xfer()
2341 case 0x32: in dib7090_tuner_xfer()
2344 case 0x3e: in dib7090_tuner_xfer()
2347 case 0x3f: in dib7090_tuner_xfer()
2350 case 0x40: in dib7090_tuner_xfer()
2353 case 0x25: in dib7090_tuner_xfer()
2356 case 0x26: in dib7090_tuner_xfer()
2359 case 0x27: in dib7090_tuner_xfer()
2362 case 0x28: in dib7090_tuner_xfer()
2365 case 0x1d: in dib7090_tuner_xfer()
2366 i = ((dib7000p_read_word(state, 72) >> 12) & 0x3); in dib7090_tuner_xfer()
2368 msg[1].buf[0] = (word >> 8) & 0xff; in dib7090_tuner_xfer()
2369 msg[1].buf[1] = (word) & 0xff; in dib7090_tuner_xfer()
2371 case 0x1f: in dib7090_tuner_xfer()
2373 word = (u16) ((msg[0].buf[1] << 8) | msg[0].buf[2]); in dib7090_tuner_xfer()
2374 word &= 0x3; in dib7090_tuner_xfer()
2381 if (apb_address != 0) /* R/W access via APB */ in dib7090_tuner_xfer()
2386 return 0; in dib7090_tuner_xfer()
2410 reg = dib7000p_read_word(state, 1798) & ~((0x7) | (0x7 << 6) | (0x7 << 12)); in dib7090_host_bus_drive()
2415 reg = dib7000p_read_word(state, 1799) & ~((0x7 << 2) | (0x7 << 8)); in dib7090_host_bus_drive()
2420 reg = dib7000p_read_word(state, 1800) & ~((0x7) | (0x7 << 6) | (0x7 << 12)); in dib7090_host_bus_drive()
2425 reg = dib7000p_read_word(state, 1801) & ~((0x7 << 2) | (0x7 << 8)); in dib7090_host_bus_drive()
2430 reg = dib7000p_read_word(state, 1802) & ~((0x7) | (0x7 << 6) | (0x7 << 12)); in dib7090_host_bus_drive()
2434 return 0; in dib7090_host_bus_drive()
2444 if ((syncFreq & ((1 << quantif) - 1)) != 0) in dib7090_calcSyncFreq()
2449 if (syncFreq != 0) in dib7090_calcSyncFreq()
2464 dib7000p_write_word(state, 1609, (syncWord >> 16) & 0xffff); in dib7090_cfg_DibTx()
2465 dib7000p_write_word(state, 1610, syncWord & 0xffff); in dib7090_cfg_DibTx()
2467 dib7000p_write_word(state, 1615, 0); in dib7090_cfg_DibTx()
2469 return 0; in dib7090_cfg_DibTx()
2478 if ((P_Kin != 0) && (P_Kout != 0)) { in dib7090_cfg_DibRx()
2486 dib7000p_write_word(state, 1540, (syncWord >> 16) & 0xffff); in dib7090_cfg_DibRx()
2487 dib7000p_write_word(state, 1541, syncWord & 0xffff); in dib7090_cfg_DibRx()
2490 dib7000p_write_word(state, 1554, 0); in dib7090_cfg_DibRx()
2492 return 0; in dib7090_cfg_DibRx()
2503 case 0: in dib7090_enMpegMux()
2516 dib7090_enMpegMux(state, 0); in dib7090_configMpegMux()
2520 enSerialClkDiv2 = 0; in dib7090_configMpegMux()
2522 dib7000p_write_word(state, 1287, ((pulseWidth & 0x1f) << 2) in dib7090_configMpegMux()
2523 | ((enSerialMode & 0x1) << 1) in dib7090_configMpegMux()
2524 | (enSerialClkDiv2 & 0x1)); in dib7090_configMpegMux()
2531 u16 reg_1288 = dib7000p_read_word(state, 1288) & ~(0x7 << 7); in dib7090_setDibTxMux()
2536 dib7090_cfg_DibTx(state, 8, 5, 0, 0, 0, 0); in dib7090_setDibTxMux()
2541 dib7090_cfg_DibTx(state, 5, 5, 0, 0, 0, 0); in dib7090_setDibTxMux()
2546 dib7090_cfg_DibTx(state, 20, 5, 10, 0, 0, 0); in dib7090_setDibTxMux()
2557 u16 reg_1288 = dib7000p_read_word(state, 1288) & ~(0x7 << 4); in dib7090_setHostBusMux()
2562 dib7090_enMpegMux(state, 0); in dib7090_setHostBusMux()
2567 dib7090_enMpegMux(state, 0); in dib7090_setHostBusMux()
2586 case 0: /* only use the internal way - not the diversity input */ in dib7090_set_diversity_in()
2588 dib7090_cfg_DibRx(state, 8, 5, 0, 0, 0, 8, 0); in dib7090_set_diversity_in()
2594 if ((reg_1287 & 0x1) == 1) { in dib7090_set_diversity_in()
2595 /* force enSerialClkDiv2 = 0 */ in dib7090_set_diversity_in()
2596 reg_1287 &= ~0x1; in dib7090_set_diversity_in()
2604 dib7090_cfg_DibRx(state, 5, 5, 0, 0, 0, 0, 0); in dib7090_set_diversity_in()
2605 state->input_mode_mpeg = 0; in dib7090_set_diversity_in()
2610 return 0; in dib7090_set_diversity_in()
2619 int ret = 0; in dib7090_set_output_mode()
2624 smo_mode = (dib7000p_read_word(state, 235) & 0x0050) | (1 << 1); in dib7090_set_output_mode()
2625 outreg = dib7000p_read_word(state, 1286) & ~((1 << 10) | (0x7 << 6) | (1 << 1)); in dib7090_set_output_mode()
2629 outreg = 0; in dib7090_set_output_mode()
2640 outreg |= (2<<6) | (0 << 1); in dib7090_set_output_mode()
2647 dib7090_configMpegMux(state, 2, 0, 0); in dib7090_set_output_mode()
2652 outreg |= (0<<6); in dib7090_set_output_mode()
2704 if (en_cur_state > 0xff) in dib7090_tuner_sleep()
2708 en_cur_state &= 0x00ff; in dib7090_tuner_sleep()
2710 if (state->tuner_enable != 0) in dib7090_tuner_sleep()
2716 return 0; in dib7090_tuner_sleep()
2732 dib7000p_write_word(state, 1032, 0xffff); in dib7090_slave_reset()
2733 return 0; in dib7090_slave_reset()
2762 dib7000p_write_word(st, 1287, 0x0003); /* sram lead in, rdy */ in dib7000p_init()
2764 if (dib7000p_identify(st) != 0) in dib7000p_init()
2791 dib7090_set_diversity_in(demod, 0); in dib7000p_init()