Lines Matching +full:stm32 +full:- +full:hwspinlock
1 // SPDX-License-Identifier: GPL-2.0
5 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com>
10 #include <linux/hwspinlock.h>
23 #include <dt-bindings/interrupt-controller/arm-gic.h>
68 struct hwspinlock *hwlock;
231 if (!drv_data->desc_irqs) in stm32_exti_get_desc()
234 for (i = 0; i < drv_data->irq_nr; i++) { in stm32_exti_get_desc()
235 desc = &drv_data->desc_irqs[i]; in stm32_exti_get_desc()
236 if (desc->exti == hwirq) in stm32_exti_get_desc()
245 struct stm32_exti_chip_data *chip_data = gc->private; in stm32_exti_pending()
246 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; in stm32_exti_pending()
249 pending = irq_reg_readl(gc, stm32_bank->rpr_ofst); in stm32_exti_pending()
250 if (stm32_bank->fpr_ofst != UNDEF_REG) in stm32_exti_pending()
251 pending |= irq_reg_readl(gc, stm32_bank->fpr_ofst); in stm32_exti_pending()
260 unsigned int nbanks = domain->gc->num_chips; in stm32_irq_handler()
282 u32 mask = BIT(d->hwirq % IRQS_PER_BANK); in stm32_exti_set_type()
298 return -EINVAL; in stm32_exti_set_type()
307 struct stm32_exti_chip_data *chip_data = gc->private; in stm32_irq_set_type()
308 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; in stm32_irq_set_type()
309 struct hwspinlock *hwlock = chip_data->host_data->hwlock; in stm32_irq_set_type()
318 pr_err("%s can't get hwspinlock (%d)\n", __func__, err); in stm32_irq_set_type()
323 rtsr = irq_reg_readl(gc, stm32_bank->rtsr_ofst); in stm32_irq_set_type()
324 ftsr = irq_reg_readl(gc, stm32_bank->ftsr_ofst); in stm32_irq_set_type()
330 irq_reg_writel(gc, rtsr, stm32_bank->rtsr_ofst); in stm32_irq_set_type()
331 irq_reg_writel(gc, ftsr, stm32_bank->ftsr_ofst); in stm32_irq_set_type()
345 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; in stm32_chip_suspend()
346 void __iomem *base = chip_data->host_data->base; in stm32_chip_suspend()
349 chip_data->rtsr_cache = readl_relaxed(base + stm32_bank->rtsr_ofst); in stm32_chip_suspend()
350 chip_data->ftsr_cache = readl_relaxed(base + stm32_bank->ftsr_ofst); in stm32_chip_suspend()
352 writel_relaxed(wake_active, base + stm32_bank->imr_ofst); in stm32_chip_suspend()
358 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; in stm32_chip_resume()
359 void __iomem *base = chip_data->host_data->base; in stm32_chip_resume()
362 writel_relaxed(chip_data->rtsr_cache, base + stm32_bank->rtsr_ofst); in stm32_chip_resume()
363 writel_relaxed(chip_data->ftsr_cache, base + stm32_bank->ftsr_ofst); in stm32_chip_resume()
365 writel_relaxed(mask_cache, base + stm32_bank->imr_ofst); in stm32_chip_resume()
370 struct stm32_exti_chip_data *chip_data = gc->private; in stm32_irq_suspend()
373 stm32_chip_suspend(chip_data, gc->wake_active); in stm32_irq_suspend()
379 struct stm32_exti_chip_data *chip_data = gc->private; in stm32_irq_resume()
382 stm32_chip_resume(chip_data, gc->mask_cache); in stm32_irq_resume()
392 hwirq = fwspec->param[0]; in stm32_exti_alloc()
416 struct stm32_exti_chip_data *chip_data = gc->private; in stm32_irq_ack()
417 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; in stm32_irq_ack()
421 irq_reg_writel(gc, d->mask, stm32_bank->rpr_ofst); in stm32_irq_ack()
422 if (stm32_bank->fpr_ofst != UNDEF_REG) in stm32_irq_ack()
423 irq_reg_writel(gc, d->mask, stm32_bank->fpr_ofst); in stm32_irq_ack()
432 void __iomem *base = chip_data->host_data->base; in stm32_exti_write_bit()
433 u32 val = BIT(d->hwirq % IRQS_PER_BANK); in stm32_exti_write_bit()
441 void __iomem *base = chip_data->host_data->base; in stm32_exti_set_bit()
445 val |= BIT(d->hwirq % IRQS_PER_BANK); in stm32_exti_set_bit()
454 void __iomem *base = chip_data->host_data->base; in stm32_exti_clr_bit()
458 val &= ~BIT(d->hwirq % IRQS_PER_BANK); in stm32_exti_clr_bit()
467 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; in stm32_exti_h_eoi()
469 raw_spin_lock(&chip_data->rlock); in stm32_exti_h_eoi()
471 stm32_exti_write_bit(d, stm32_bank->rpr_ofst); in stm32_exti_h_eoi()
472 if (stm32_bank->fpr_ofst != UNDEF_REG) in stm32_exti_h_eoi()
473 stm32_exti_write_bit(d, stm32_bank->fpr_ofst); in stm32_exti_h_eoi()
475 raw_spin_unlock(&chip_data->rlock); in stm32_exti_h_eoi()
477 if (d->parent_data->chip) in stm32_exti_h_eoi()
484 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; in stm32_exti_h_mask()
486 raw_spin_lock(&chip_data->rlock); in stm32_exti_h_mask()
487 chip_data->mask_cache = stm32_exti_clr_bit(d, stm32_bank->imr_ofst); in stm32_exti_h_mask()
488 raw_spin_unlock(&chip_data->rlock); in stm32_exti_h_mask()
490 if (d->parent_data->chip) in stm32_exti_h_mask()
497 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; in stm32_exti_h_unmask()
499 raw_spin_lock(&chip_data->rlock); in stm32_exti_h_unmask()
500 chip_data->mask_cache = stm32_exti_set_bit(d, stm32_bank->imr_ofst); in stm32_exti_h_unmask()
501 raw_spin_unlock(&chip_data->rlock); in stm32_exti_h_unmask()
503 if (d->parent_data->chip) in stm32_exti_h_unmask()
510 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; in stm32_exti_h_set_type()
511 struct hwspinlock *hwlock = chip_data->host_data->hwlock; in stm32_exti_h_set_type()
512 void __iomem *base = chip_data->host_data->base; in stm32_exti_h_set_type()
516 raw_spin_lock(&chip_data->rlock); in stm32_exti_h_set_type()
521 pr_err("%s can't get hwspinlock (%d)\n", __func__, err); in stm32_exti_h_set_type()
526 rtsr = readl_relaxed(base + stm32_bank->rtsr_ofst); in stm32_exti_h_set_type()
527 ftsr = readl_relaxed(base + stm32_bank->ftsr_ofst); in stm32_exti_h_set_type()
533 writel_relaxed(rtsr, base + stm32_bank->rtsr_ofst); in stm32_exti_h_set_type()
534 writel_relaxed(ftsr, base + stm32_bank->ftsr_ofst); in stm32_exti_h_set_type()
540 raw_spin_unlock(&chip_data->rlock); in stm32_exti_h_set_type()
548 u32 mask = BIT(d->hwirq % IRQS_PER_BANK); in stm32_exti_h_set_wake()
550 raw_spin_lock(&chip_data->rlock); in stm32_exti_h_set_wake()
553 chip_data->wake_active |= mask; in stm32_exti_h_set_wake()
555 chip_data->wake_active &= ~mask; in stm32_exti_h_set_wake()
557 raw_spin_unlock(&chip_data->rlock); in stm32_exti_h_set_wake()
565 if (d->parent_data->chip) in stm32_exti_h_set_affinity()
568 return -EINVAL; in stm32_exti_h_set_affinity()
576 for (i = 0; i < stm32_host_data->drv_data->bank_nr; i++) { in stm32_exti_h_suspend()
577 chip_data = &stm32_host_data->chips_data[i]; in stm32_exti_h_suspend()
578 raw_spin_lock(&chip_data->rlock); in stm32_exti_h_suspend()
579 stm32_chip_suspend(chip_data, chip_data->wake_active); in stm32_exti_h_suspend()
580 raw_spin_unlock(&chip_data->rlock); in stm32_exti_h_suspend()
591 for (i = 0; i < stm32_host_data->drv_data->bank_nr; i++) { in stm32_exti_h_resume()
592 chip_data = &stm32_host_data->chips_data[i]; in stm32_exti_h_resume()
593 raw_spin_lock(&chip_data->rlock); in stm32_exti_h_resume()
594 stm32_chip_resume(chip_data, chip_data->mask_cache); in stm32_exti_h_resume()
595 raw_spin_unlock(&chip_data->rlock); in stm32_exti_h_resume()
620 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; in stm32_exti_h_retrigger()
621 void __iomem *base = chip_data->host_data->base; in stm32_exti_h_retrigger()
622 u32 mask = BIT(d->hwirq % IRQS_PER_BANK); in stm32_exti_h_retrigger()
624 writel_relaxed(mask, base + stm32_bank->swier_ofst); in stm32_exti_h_retrigger()
630 .name = "stm32-exti-h",
642 .name = "stm32-exti-h-direct",
658 struct stm32_exti_host_data *host_data = dm->host_data; in stm32_exti_h_domain_alloc()
666 hwirq = fwspec->param[0]; in stm32_exti_h_domain_alloc()
668 chip_data = &host_data->chips_data[bank]; in stm32_exti_h_domain_alloc()
671 desc = stm32_exti_get_desc(host_data->drv_data, hwirq); in stm32_exti_h_domain_alloc()
673 return -EINVAL; in stm32_exti_h_domain_alloc()
675 irq_domain_set_hwirq_and_chip(dm, virq, hwirq, desc->chip, in stm32_exti_h_domain_alloc()
677 if (desc->irq_parent) { in stm32_exti_h_domain_alloc()
678 p_fwspec.fwnode = dm->parent->fwnode; in stm32_exti_h_domain_alloc()
681 p_fwspec.param[1] = desc->irq_parent; in stm32_exti_h_domain_alloc()
700 host_data->drv_data = dd; in stm32_exti_host_init()
701 host_data->chips_data = kcalloc(dd->bank_nr, in stm32_exti_host_init()
704 if (!host_data->chips_data) in stm32_exti_host_init()
707 host_data->base = of_iomap(node, 0); in stm32_exti_host_init()
708 if (!host_data->base) { in stm32_exti_host_init()
718 kfree(host_data->chips_data); in stm32_exti_host_init()
732 void __iomem *base = h_data->base; in stm32_exti_chip_init()
734 stm32_bank = h_data->drv_data->exti_banks[bank_idx]; in stm32_exti_chip_init()
735 chip_data = &h_data->chips_data[bank_idx]; in stm32_exti_chip_init()
736 chip_data->host_data = h_data; in stm32_exti_chip_init()
737 chip_data->reg_bank = stm32_bank; in stm32_exti_chip_init()
739 raw_spin_lock_init(&chip_data->rlock); in stm32_exti_chip_init()
745 writel_relaxed(0, base + stm32_bank->imr_ofst); in stm32_exti_chip_init()
746 writel_relaxed(0, base + stm32_bank->emr_ofst); in stm32_exti_chip_init()
764 return -ENOMEM; in stm32_exti_init()
766 domain = irq_domain_add_linear(node, drv_data->bank_nr * IRQS_PER_BANK, in stm32_exti_init()
771 ret = -ENOMEM; in stm32_exti_init()
783 for (i = 0; i < drv_data->bank_nr; i++) { in stm32_exti_init()
787 stm32_bank = drv_data->exti_banks[i]; in stm32_exti_init()
792 gc->reg_base = host_data->base; in stm32_exti_init()
793 gc->chip_types->type = IRQ_TYPE_EDGE_BOTH; in stm32_exti_init()
794 gc->chip_types->chip.irq_ack = stm32_irq_ack; in stm32_exti_init()
795 gc->chip_types->chip.irq_mask = irq_gc_mask_clr_bit; in stm32_exti_init()
796 gc->chip_types->chip.irq_unmask = irq_gc_mask_set_bit; in stm32_exti_init()
797 gc->chip_types->chip.irq_set_type = stm32_irq_set_type; in stm32_exti_init()
798 gc->chip_types->chip.irq_set_wake = irq_gc_set_wake; in stm32_exti_init()
799 gc->suspend = stm32_irq_suspend; in stm32_exti_init()
800 gc->resume = stm32_irq_resume; in stm32_exti_init()
801 gc->wake_enabled = IRQ_MSK(IRQS_PER_BANK); in stm32_exti_init()
803 gc->chip_types->regs.mask = stm32_bank->imr_ofst; in stm32_exti_init()
804 gc->private = (void *)chip_data; in stm32_exti_init()
820 iounmap(host_data->base); in stm32_exti_init()
821 kfree(host_data->chips_data); in stm32_exti_init()
848 struct device *dev = &pdev->dev; in stm32_exti_probe()
849 struct device_node *np = dev->of_node; in stm32_exti_probe()
857 return -ENOMEM; in stm32_exti_probe()
859 /* check for optional hwspinlock which may be not available yet */ in stm32_exti_probe()
861 if (ret == -EPROBE_DEFER) in stm32_exti_probe()
862 /* hwspinlock framework not yet ready */ in stm32_exti_probe()
866 host_data->hwlock = devm_hwspin_lock_request_specific(dev, ret); in stm32_exti_probe()
867 if (!host_data->hwlock) { in stm32_exti_probe()
868 dev_err(dev, "Failed to request hwspinlock\n"); in stm32_exti_probe()
869 return -EINVAL; in stm32_exti_probe()
871 } else if (ret != -ENOENT) { in stm32_exti_probe()
872 /* note: ENOENT is a valid case (means 'no hwspinlock') */ in stm32_exti_probe()
873 dev_err(dev, "Failed to get hwspinlock\n"); in stm32_exti_probe()
881 return -ENODEV; in stm32_exti_probe()
883 host_data->drv_data = drv_data; in stm32_exti_probe()
885 host_data->chips_data = devm_kcalloc(dev, drv_data->bank_nr, in stm32_exti_probe()
886 sizeof(*host_data->chips_data), in stm32_exti_probe()
888 if (!host_data->chips_data) in stm32_exti_probe()
889 return -ENOMEM; in stm32_exti_probe()
892 host_data->base = devm_ioremap_resource(dev, res); in stm32_exti_probe()
893 if (IS_ERR(host_data->base)) in stm32_exti_probe()
894 return PTR_ERR(host_data->base); in stm32_exti_probe()
896 for (i = 0; i < drv_data->bank_nr; i++) in stm32_exti_probe()
901 dev_err(dev, "GIC interrupt-parent not found\n"); in stm32_exti_probe()
902 return -EINVAL; in stm32_exti_probe()
906 drv_data->bank_nr * IRQS_PER_BANK, in stm32_exti_probe()
912 return -ENOMEM; in stm32_exti_probe()
926 { .compatible = "st,stm32mp1-exti", .data = &stm32mp1_drv_data},
960 IRQCHIP_DECLARE(stm32f4_exti, "st,stm32-exti", stm32f4_exti_of_init);
968 IRQCHIP_DECLARE(stm32h7_exti, "st,stm32h7-exti", stm32h7_exti_of_init);