1 // SPDX-License-Identifier: GPL-2.0-only
3  * ARM GIC v2m MSI(-X) support
5  * implement ARM Generic Interrupt Controller: GICv2m.
16 #include <linux/dma-iommu.h>
26 #include <linux/irqchip/arm-gic.h>
49 /* APM X-Gene with GICv2m MSI_IIDR register value */
66 	void __iomem *base;	/* GICv2m virt address */  member
102 	if (v2m->flags & GICV2M_GRAVITON_ADDRESS_ONLY)  in gicv2m_get_msi_addr()
103 		return v2m->res.start | ((hwirq - 32) << 3);  in gicv2m_get_msi_addr()
105 		return v2m->res.start + V2M_MSI_SETSPI_NS;  in gicv2m_get_msi_addr()
111 	phys_addr_t addr = gicv2m_get_msi_addr(v2m, data->hwirq);  in gicv2m_compose_msi_msg()
113 	msg->address_hi = upper_32_bits(addr);  in gicv2m_compose_msi_msg()
114 	msg->address_lo = lower_32_bits(addr);  in gicv2m_compose_msi_msg()
116 	if (v2m->flags & GICV2M_GRAVITON_ADDRESS_ONLY)  in gicv2m_compose_msi_msg()
117 		msg->data = 0;  in gicv2m_compose_msi_msg()
119 		msg->data = data->hwirq;  in gicv2m_compose_msi_msg()
120 	if (v2m->flags & GICV2M_NEEDS_SPI_OFFSET)  in gicv2m_compose_msi_msg()
121 		msg->data -= v2m->spi_offset;  in gicv2m_compose_msi_msg()
143 	if (is_of_node(domain->parent->fwnode)) {  in gicv2m_irq_gic_domain_alloc()
144 		fwspec.fwnode = domain->parent->fwnode;  in gicv2m_irq_gic_domain_alloc()
147 		fwspec.param[1] = hwirq - 32;  in gicv2m_irq_gic_domain_alloc()
149 	} else if (is_fwnode_irqchip(domain->parent->fwnode)) {  in gicv2m_irq_gic_domain_alloc()
150 		fwspec.fwnode = domain->parent->fwnode;  in gicv2m_irq_gic_domain_alloc()
155 		return -EINVAL;  in gicv2m_irq_gic_domain_alloc()
162 	/* Configure the interrupt line to be edge */  in gicv2m_irq_gic_domain_alloc()
163 	d = irq_domain_get_irq_data(domain->parent, virq);  in gicv2m_irq_gic_domain_alloc()
164 	d->chip->irq_set_type(d, IRQ_TYPE_EDGE_RISING);  in gicv2m_irq_gic_domain_alloc()
172 	bitmap_release_region(v2m->bm, hwirq - v2m->spi_start,  in gicv2m_unalloc_msi()
186 		offset = bitmap_find_free_region(tmp->bm, tmp->nr_spis,  in gicv2m_irq_domain_alloc()
196 		return -ENOSPC;  in gicv2m_irq_domain_alloc()
198 	hwirq = v2m->spi_start + offset;  in gicv2m_irq_domain_alloc()
200 	err = iommu_dma_prepare_msi(info->desc,  in gicv2m_irq_domain_alloc()
228 	gicv2m_unalloc_msi(v2m, d->hwirq, nr_irqs);  in gicv2m_irq_domain_free()
237 static bool is_msi_spi_valid(u32 base, u32 num)  in is_msi_spi_valid()  argument
239 	if (base < V2M_MIN_SPI) {  in is_msi_spi_valid()
240 		pr_err("Invalid MSI base SPI (base:%u)\n", base);  in is_msi_spi_valid()
244 	if ((num == 0) || (base + num > V2M_MAX_SPI)) {  in is_msi_spi_valid()
246 		       num, V2M_MAX_SPI - V2M_MIN_SPI + 1);  in is_msi_spi_valid()
271 		list_del(&v2m->entry);  in gicv2m_teardown()
272 		bitmap_free(v2m->bm);  in gicv2m_teardown()
273 		iounmap(v2m->base);  in gicv2m_teardown()
274 		of_node_put(to_of_node(v2m->fwnode));  in gicv2m_teardown()
275 		if (is_fwnode_irqchip(v2m->fwnode))  in gicv2m_teardown()
276 			irq_domain_free_fwnode(v2m->fwnode);  in gicv2m_teardown()
290 	inner_domain = irq_domain_create_tree(v2m->fwnode,  in gicv2m_allocate_domains()
294 		return -ENOMEM;  in gicv2m_allocate_domains()
298 	inner_domain->parent = parent;  in gicv2m_allocate_domains()
299 	pci_domain = pci_msi_create_irq_domain(v2m->fwnode,  in gicv2m_allocate_domains()
302 	plat_domain = platform_msi_create_irq_domain(v2m->fwnode,  in gicv2m_allocate_domains()
312 		return -ENOMEM;  in gicv2m_allocate_domains()
327 		return -ENOMEM;  in gicv2m_init_one()
329 	INIT_LIST_HEAD(&v2m->entry);  in gicv2m_init_one()
330 	v2m->fwnode = fwnode;  in gicv2m_init_one()
331 	v2m->flags = flags;  in gicv2m_init_one()
333 	memcpy(&v2m->res, res, sizeof(struct resource));  in gicv2m_init_one()
335 	v2m->base = ioremap(v2m->res.start, resource_size(&v2m->res));  in gicv2m_init_one()
336 	if (!v2m->base) {  in gicv2m_init_one()
338 		ret = -ENOMEM;  in gicv2m_init_one()
343 		v2m->spi_start = spi_start;  in gicv2m_init_one()
344 		v2m->nr_spis = nr_spis;  in gicv2m_init_one()
349 		if (v2m->flags & GICV2M_GRAVITON_ADDRESS_ONLY) {  in gicv2m_init_one()
350 			ret = -EINVAL;  in gicv2m_init_one()
353 		typer = readl_relaxed(v2m->base + V2M_MSI_TYPER);  in gicv2m_init_one()
355 		v2m->spi_start = V2M_MSI_TYPER_BASE_SPI(typer);  in gicv2m_init_one()
356 		v2m->nr_spis = V2M_MSI_TYPER_NUM_SPI(typer);  in gicv2m_init_one()
359 	if (!is_msi_spi_valid(v2m->spi_start, v2m->nr_spis)) {  in gicv2m_init_one()
360 		ret = -EINVAL;  in gicv2m_init_one()
365 	 * APM X-Gene GICv2m implementation has an erratum where  in gicv2m_init_one()
367 	 * in order to trigger the correct MSI interrupt. This is  in gicv2m_init_one()
373 	 * is 'spi_number - 32'  in gicv2m_init_one()
377 	if (!(v2m->flags & GICV2M_GRAVITON_ADDRESS_ONLY)) {  in gicv2m_init_one()
378 		switch (readl_relaxed(v2m->base + V2M_MSI_IIDR)) {  in gicv2m_init_one()
380 			v2m->flags |= GICV2M_NEEDS_SPI_OFFSET;  in gicv2m_init_one()
381 			v2m->spi_offset = v2m->spi_start;  in gicv2m_init_one()
384 			v2m->flags |= GICV2M_NEEDS_SPI_OFFSET;  in gicv2m_init_one()
385 			v2m->spi_offset = 32;  in gicv2m_init_one()
389 	v2m->bm = bitmap_zalloc(v2m->nr_spis, GFP_KERNEL);  in gicv2m_init_one()
390 	if (!v2m->bm) {  in gicv2m_init_one()
391 		ret = -ENOMEM;  in gicv2m_init_one()
395 	list_add_tail(&v2m->entry, &v2m_nodes);  in gicv2m_init_one()
398 		v2m->spi_start, (v2m->spi_start + v2m->nr_spis - 1));  in gicv2m_init_one()
402 	iounmap(v2m->base);  in gicv2m_init_one()
409 	{	.compatible	= "arm,gic-v2m-frame",	},
418 	struct device_node *child;  in gicv2m_of_init()  local
420 	for (child = of_find_matching_node(node, gicv2m_device_id); child;  in gicv2m_of_init()
421 	     child = of_find_matching_node(child, gicv2m_device_id)) {  in gicv2m_of_init()
425 		if (!of_find_property(child, "msi-controller", NULL))  in gicv2m_of_init()
428 		ret = of_address_to_resource(child, 0, &res);  in gicv2m_of_init()
434 		if (!of_property_read_u32(child, "arm,msi-base-spi",  in gicv2m_of_init()
436 		    !of_property_read_u32(child, "arm,msi-num-spis", &nr_spis))  in gicv2m_of_init()
437 			pr_info("DT overriding V2M MSI_TYPER (base:%u, num:%u)\n",  in gicv2m_of_init()
440 		ret = gicv2m_init_one(&child->fwnode, spi_start, nr_spis,  in gicv2m_of_init()
443 			of_node_put(child);  in gicv2m_of_init()
470 	return data->fwnode;  in gicv2m_get_fwnode()
486 	rc = !memcmp(madt->header.oem_id, ACPI_AMZN_OEM_ID, ACPI_OEM_ID_SIZE);  in acpi_check_amazon_graviton_quirks()
505 		return -EINVAL;  in acpi_parse_madt_msi()
507 	res.start = m->base_address;  in acpi_parse_madt_msi()
508 	res.end = m->base_address + SZ_4K - 1;  in acpi_parse_madt_msi()
513 		res.end = res.start + SZ_8K - 1;  in acpi_parse_madt_msi()
518 	if (m->flags & ACPI_MADT_OVERRIDE_SPI_VALUES) {  in acpi_parse_madt_msi()
519 		spi_start = m->spi_base;  in acpi_parse_madt_msi()
520 		nr_spis = m->spi_count;  in acpi_parse_madt_msi()
522 		pr_info("ACPI overriding V2M MSI_TYPER (base:%u, num:%u)\n",  in acpi_parse_madt_msi()
529 		return -EINVAL;  in acpi_parse_madt_msi()
562 	return -EINVAL;  in gicv2m_acpi_init()
567 	return -EINVAL;  in gicv2m_acpi_init()