38  *   - <0 nr flags> - hwirq #nr
40  *     - nr=0  Physical HV timer
68 #define AIC_INFO		0x0004
69 #define AIC_INFO_NR_HW		GENMASK(15, 0)
71 #define AIC_CONFIG		0x0010
73 #define AIC_WHOAMI		0x2000
74 #define AIC_EVENT		0x2004
76 #define AIC_EVENT_NUM		GENMASK(15, 0)
83 #define AIC_IPI_SEND		0x2008
84 #define AIC_IPI_ACK		0x200c
85 #define AIC_IPI_MASK_SET	0x2024
86 #define AIC_IPI_MASK_CLR	0x2028
90 #define AIC_IPI_OTHER		BIT(0)
93 #define AIC_TARGET_CPU		0x3000
94 #define AIC_SW_SET		0x4000
95 #define AIC_SW_CLR		0x4080
96 #define AIC_MASK_SET		0x4100
97 #define AIC_MASK_CLR		0x4180
99 #define AIC_CPU_IPI_SET(cpu)	(0x5008 + ((cpu) << 7))
100 #define AIC_CPU_IPI_CLR(cpu)	(0x500c + ((cpu) << 7))
101 #define AIC_CPU_IPI_MASK_SET(cpu) (0x5024 + ((cpu) << 7))
102 #define AIC_CPU_IPI_MASK_CLR(cpu) (0x5028 + ((cpu) << 7))
105 #define MASK_BIT(x)		BIT((x) & GENMASK(4, 0))
113 #define SYS_IMP_APL_PMCR0_EL1		sys_reg(3, 1, 15, 0, 0)
115 #define PMCR0_IMODE_OFF			0
123 #define SYS_IMP_APL_IPI_RR_LOCAL_EL1	sys_reg(3, 5, 15, 0, 0)
124 #define SYS_IMP_APL_IPI_RR_GLOBAL_EL1	sys_reg(3, 5, 15, 0, 1)
125 #define IPI_RR_CPU			GENMASK(7, 0)
129 #define IPI_RR_IMMEDIATE		0
136 #define IPI_SR_PENDING			BIT(0)
140 #define VM_TMR_FIQ_ENABLE_V		BIT(0)
147 #define SYS_IMP_APL_UPMCR0_EL1		sys_reg(3, 7, 15, 0, 4)
149 #define UPMCR0_IMODE_OFF		0
156 #define UPMSR_IACT			BIT(0)
251 		else if (event != 0)  in aic_handle_irq()
262 		read_sysreg_s(SYS_ICH_MISR_EL2) != 0) {  in aic_handle_irq()
264 		sysreg_clear_set_s(SYS_ICH_HCR_EL2, ICH_HCR_EN, 0);  in aic_handle_irq()
292 	return (type == IRQ_TYPE_LEVEL_HIGH || type == IRQ_TYPE_EDGE_RISING) ? 0 : -EINVAL;  in aic_irq_set_type()
320 		sysreg_clear_set_s(SYS_IMP_APL_VM_TMR_FIQ_ENA_EL2, VM_TMR_FIQ_ENABLE_P, 0);  in aic_fiq_set_mask()
324 		sysreg_clear_set_s(SYS_IMP_APL_VM_TMR_FIQ_ENA_EL2, VM_TMR_FIQ_ENABLE_V, 0);  in aic_fiq_set_mask()
336 		sysreg_clear_set_s(SYS_IMP_APL_VM_TMR_FIQ_ENA_EL2, 0, VM_TMR_FIQ_ENABLE_P);  in aic_fiq_clear_mask()
340 		sysreg_clear_set_s(SYS_IMP_APL_VM_TMR_FIQ_ENA_EL2, 0, VM_TMR_FIQ_ENABLE_V);  in aic_fiq_clear_mask()
439 	return (type == IRQ_TYPE_LEVEL_HIGH) ? 0 : -EINVAL;  in aic_fiq_set_type()
470 	return 0;  in aic_irq_domain_map()
483 	switch (fwspec->param[0]) {  in aic_irq_domain_translate()
520 	return 0;  in aic_irq_domain_translate()
535 	for (i = 0; i < nr_irqs; i++) {  in aic_irq_domain_alloc()
541 	return 0;  in aic_irq_domain_alloc()
549 	for (i = 0; i < nr_irqs; i++) {  in aic_irq_domain_free()
600 	u32 send = 0;  in aic_ipi_send_mask()
691 	for (i = 0; i < nr_irqs; i++) {  in aic_ipi_alloc()
697 	return 0;  in aic_ipi_alloc()
735 	return 0;  in aic_init_smp()
746 	sysreg_clear_set(cntp_ctl_el0, 0, ARCH_TIMER_CTRL_IT_MASK);  in aic_init_cpu()
747 	sysreg_clear_set(cntv_ctl_el0, 0, ARCH_TIMER_CTRL_IT_MASK);  in aic_init_cpu()
753 				   VM_TMR_FIQ_ENABLE_V | VM_TMR_FIQ_ENABLE_P, 0);  in aic_init_cpu()
756 		sysreg_clear_set_s(SYS_ICH_HCR_EL2, ICH_HCR_EN, 0);  in aic_init_cpu()
786 	__this_cpu_write(aic_fiq_unmasked, 0);  in aic_init_cpu()
788 	return 0;  in aic_init_cpu()
804 	regs = of_iomap(node, 0);  in aic_of_ic_init()
839 	for (i = 0; i < BITS_TO_U32(irqc->nr_hw); i++)  in aic_of_ic_init()
841 	for (i = 0; i < BITS_TO_U32(irqc->nr_hw); i++)  in aic_of_ic_init()
843 	for (i = 0; i < irqc->nr_hw; i++)  in aic_of_ic_init()
858 	return 0;  in aic_of_ic_init()