18 #include <linux/iommu.h>
54 static int __enable_clocks(struct msm_iommu_dev *iommu)  in __enable_clocks()  argument
58 	ret = clk_enable(iommu->pclk);  in __enable_clocks()
62 	if (iommu->clk) {  in __enable_clocks()
63 		ret = clk_enable(iommu->clk);  in __enable_clocks()
65 			clk_disable(iommu->pclk);  in __enable_clocks()
71 static void __disable_clocks(struct msm_iommu_dev *iommu)  in __disable_clocks()  argument
73 	if (iommu->clk)  in __disable_clocks()
74 		clk_disable(iommu->clk);  in __disable_clocks()
75 	clk_disable(iommu->pclk);  in __disable_clocks()
120 	struct msm_iommu_dev *iommu = NULL;  in __flush_iotlb()  local
124 	list_for_each_entry(iommu, &priv->list_attached, dom_node) {  in __flush_iotlb()
125 		ret = __enable_clocks(iommu);  in __flush_iotlb()
129 		list_for_each_entry(master, &iommu->ctx_list, list)  in __flush_iotlb()
130 			SET_CTX_TLBIALL(iommu->base, master->num, 0);  in __flush_iotlb()
132 		__disable_clocks(iommu);  in __flush_iotlb()
142 	struct msm_iommu_dev *iommu = NULL;  in __flush_iotlb_range()  local
147 	list_for_each_entry(iommu, &priv->list_attached, dom_node) {  in __flush_iotlb_range()
148 		ret = __enable_clocks(iommu);  in __flush_iotlb_range()
152 		list_for_each_entry(master, &iommu->ctx_list, list) {  in __flush_iotlb_range()
156 				iova |= GET_CONTEXTIDR_ASID(iommu->base,  in __flush_iotlb_range()
158 				SET_TLBIVA(iommu->base, master->num, iova);  in __flush_iotlb_range()
163 		__disable_clocks(iommu);  in __flush_iotlb_range()
206 static void config_mids(struct msm_iommu_dev *iommu,  in config_mids()  argument
215 		SET_M2VCBR_N(iommu->base, mid, 0);  in config_mids()
216 		SET_CBACR_N(iommu->base, ctx, 0);  in config_mids()
219 		SET_VMID(iommu->base, mid, 0);  in config_mids()
222 		SET_CBNDX(iommu->base, mid, ctx);  in config_mids()
225 		SET_CBVMID(iommu->base, ctx, 0);  in config_mids()
228 		SET_CONTEXTIDR_ASID(iommu->base, ctx, ctx);  in config_mids()
231 		SET_NSCFG(iommu->base, mid, 3);  in config_mids()
366 	struct msm_iommu_dev *iommu, *ret = NULL;  in find_iommu_for_dev()  local
369 	list_for_each_entry(iommu, &qcom_iommu_devices, dev_node) {  in find_iommu_for_dev()
370 		master = list_first_entry(&iommu->ctx_list,  in find_iommu_for_dev()
374 			ret = iommu;  in find_iommu_for_dev()
384 	struct msm_iommu_dev *iommu;  in msm_iommu_probe_device()  local
388 	iommu = find_iommu_for_dev(dev);  in msm_iommu_probe_device()
391 	if (!iommu)  in msm_iommu_probe_device()
394 	return &iommu->iommu;  in msm_iommu_probe_device()
405 	struct msm_iommu_dev *iommu;  in msm_iommu_attach_dev()  local
413 	list_for_each_entry(iommu, &qcom_iommu_devices, dev_node) {  in msm_iommu_attach_dev()
414 		master = list_first_entry(&iommu->ctx_list,  in msm_iommu_attach_dev()
418 			ret = __enable_clocks(iommu);  in msm_iommu_attach_dev()
422 			list_for_each_entry(master, &iommu->ctx_list, list) {  in msm_iommu_attach_dev()
429 					msm_iommu_alloc_ctx(iommu->context_map,  in msm_iommu_attach_dev()
430 							    0, iommu->ncb);  in msm_iommu_attach_dev()
435 				config_mids(iommu, master);  in msm_iommu_attach_dev()
436 				__program_context(iommu->base, master->num,  in msm_iommu_attach_dev()
439 			__disable_clocks(iommu);  in msm_iommu_attach_dev()
440 			list_add(&iommu->dom_node, &priv->list_attached);  in msm_iommu_attach_dev()
455 	struct msm_iommu_dev *iommu;  in msm_iommu_detach_dev()  local
462 	list_for_each_entry(iommu, &priv->list_attached, dom_node) {  in msm_iommu_detach_dev()
463 		ret = __enable_clocks(iommu);  in msm_iommu_detach_dev()
467 		list_for_each_entry(master, &iommu->ctx_list, list) {  in msm_iommu_detach_dev()
468 			msm_iommu_free_ctx(iommu->context_map, master->num);  in msm_iommu_detach_dev()
469 			__reset_context(iommu->base, master->num);  in msm_iommu_detach_dev()
471 		__disable_clocks(iommu);  in msm_iommu_detach_dev()
516 	struct msm_iommu_dev *iommu;  in msm_iommu_iova_to_phys()  local
525 	iommu = list_first_entry(&priv->list_attached,  in msm_iommu_iova_to_phys()
528 	if (list_empty(&iommu->ctx_list))  in msm_iommu_iova_to_phys()
531 	master = list_first_entry(&iommu->ctx_list,  in msm_iommu_iova_to_phys()
536 	ret = __enable_clocks(iommu);  in msm_iommu_iova_to_phys()
541 	SET_CTX_TLBIALL(iommu->base, master->num, 0);  in msm_iommu_iova_to_phys()
542 	SET_V2PPR(iommu->base, master->num, va & V2Pxx_VA);  in msm_iommu_iova_to_phys()
544 	par = GET_PAR(iommu->base, master->num);  in msm_iommu_iova_to_phys()
547 	if (GET_NOFAULT_SS(iommu->base, master->num))  in msm_iommu_iova_to_phys()
552 	if (GET_FAULT(iommu->base, master->num))  in msm_iommu_iova_to_phys()
555 	__disable_clocks(iommu);  in msm_iommu_iova_to_phys()
592 				struct msm_iommu_dev **iommu,  in insert_iommu_master()  argument
598 	if (list_empty(&(*iommu)->ctx_list)) {  in insert_iommu_master()
601 		list_add(&master->list, &(*iommu)->ctx_list);  in insert_iommu_master()
618 	struct msm_iommu_dev *iommu;  in qcom_iommu_of_xlate()  local
623 	list_for_each_entry(iommu, &qcom_iommu_devices, dev_node)  in qcom_iommu_of_xlate()
624 		if (iommu->dev->of_node == spec->np)  in qcom_iommu_of_xlate()
627 	if (!iommu || iommu->dev->of_node != spec->np) {  in qcom_iommu_of_xlate()
632 	insert_iommu_master(dev, &iommu, spec);  in qcom_iommu_of_xlate()
641 	struct msm_iommu_dev *iommu = dev_id;  in msm_iommu_fault_handler()  local
647 	if (!iommu) {  in msm_iommu_fault_handler()
652 	pr_err("Unexpected IOMMU page fault!\n");  in msm_iommu_fault_handler()
653 	pr_err("base = %08x\n", (unsigned int)iommu->base);  in msm_iommu_fault_handler()
655 	ret = __enable_clocks(iommu);  in msm_iommu_fault_handler()
659 	for (i = 0; i < iommu->ncb; i++) {  in msm_iommu_fault_handler()
660 		fsr = GET_FSR(iommu->base, i);  in msm_iommu_fault_handler()
664 			print_ctx_regs(iommu->base, i);  in msm_iommu_fault_handler()
665 			SET_FSR(iommu->base, i, 0x4000000F);  in msm_iommu_fault_handler()
668 	__disable_clocks(iommu);  in msm_iommu_fault_handler()
685 	 * taken care when the iommu client does a writel before
702 	struct msm_iommu_dev *iommu;  in msm_iommu_probe()  local
705 	iommu = devm_kzalloc(&pdev->dev, sizeof(*iommu), GFP_KERNEL);  in msm_iommu_probe()
706 	if (!iommu)  in msm_iommu_probe()
709 	iommu->dev = &pdev->dev;  in msm_iommu_probe()
710 	INIT_LIST_HEAD(&iommu->ctx_list);  in msm_iommu_probe()
712 	iommu->pclk = devm_clk_get(iommu->dev, "smmu_pclk");  in msm_iommu_probe()
713 	if (IS_ERR(iommu->pclk)) {  in msm_iommu_probe()
714 		dev_err(iommu->dev, "could not get smmu_pclk\n");  in msm_iommu_probe()
715 		return PTR_ERR(iommu->pclk);  in msm_iommu_probe()
718 	ret = clk_prepare(iommu->pclk);  in msm_iommu_probe()
720 		dev_err(iommu->dev, "could not prepare smmu_pclk\n");  in msm_iommu_probe()
724 	iommu->clk = devm_clk_get(iommu->dev, "iommu_clk");  in msm_iommu_probe()
725 	if (IS_ERR(iommu->clk)) {  in msm_iommu_probe()
726 		dev_err(iommu->dev, "could not get iommu_clk\n");  in msm_iommu_probe()
727 		clk_unprepare(iommu->pclk);  in msm_iommu_probe()
728 		return PTR_ERR(iommu->clk);  in msm_iommu_probe()
731 	ret = clk_prepare(iommu->clk);  in msm_iommu_probe()
733 		dev_err(iommu->dev, "could not prepare iommu_clk\n");  in msm_iommu_probe()
734 		clk_unprepare(iommu->pclk);  in msm_iommu_probe()
739 	iommu->base = devm_ioremap_resource(iommu->dev, r);  in msm_iommu_probe()
740 	if (IS_ERR(iommu->base)) {  in msm_iommu_probe()
741 		dev_err(iommu->dev, "could not get iommu base\n");  in msm_iommu_probe()
742 		ret = PTR_ERR(iommu->base);  in msm_iommu_probe()
747 	iommu->irq = platform_get_irq(pdev, 0);  in msm_iommu_probe()
748 	if (iommu->irq < 0) {  in msm_iommu_probe()
753 	ret = of_property_read_u32(iommu->dev->of_node, "qcom,ncb", &val);  in msm_iommu_probe()
755 		dev_err(iommu->dev, "could not get ncb\n");  in msm_iommu_probe()
758 	iommu->ncb = val;  in msm_iommu_probe()
760 	msm_iommu_reset(iommu->base, iommu->ncb);  in msm_iommu_probe()
761 	SET_M(iommu->base, 0, 1);  in msm_iommu_probe()
762 	SET_PAR(iommu->base, 0, 0);  in msm_iommu_probe()
763 	SET_V2PCFG(iommu->base, 0, 1);  in msm_iommu_probe()
764 	SET_V2PPR(iommu->base, 0, 0);  in msm_iommu_probe()
765 	par = GET_PAR(iommu->base, 0);  in msm_iommu_probe()
766 	SET_V2PCFG(iommu->base, 0, 0);  in msm_iommu_probe()
767 	SET_M(iommu->base, 0, 0);  in msm_iommu_probe()
775 	ret = devm_request_threaded_irq(iommu->dev, iommu->irq, NULL,  in msm_iommu_probe()
779 					iommu);  in msm_iommu_probe()
781 		pr_err("Request IRQ %d failed with ret=%d\n", iommu->irq, ret);  in msm_iommu_probe()
785 	list_add(&iommu->dev_node, &qcom_iommu_devices);  in msm_iommu_probe()
787 	ret = iommu_device_sysfs_add(&iommu->iommu, iommu->dev, NULL,  in msm_iommu_probe()
794 	ret = iommu_device_register(&iommu->iommu, &msm_iommu_ops, &pdev->dev);  in msm_iommu_probe()
803 		iommu->base, iommu->irq, iommu->ncb);  in msm_iommu_probe()
807 	clk_unprepare(iommu->clk);  in msm_iommu_probe()
808 	clk_unprepare(iommu->pclk);  in msm_iommu_probe()
813 	{ .compatible = "qcom,apq8064-iommu" },
819 	struct msm_iommu_dev *iommu = platform_get_drvdata(pdev);  in msm_iommu_remove()  local
821 	clk_unprepare(iommu->clk);  in msm_iommu_remove()
822 	clk_unprepare(iommu->pclk);  in msm_iommu_remove()
841 		pr_err("Failed to register IOMMU driver\n");  in msm_iommu_driver_init()