22 #include <linux/intel-iommu.h>
29 #include <linux/iommu.h>
67 static void free_iommu(struct intel_iommu *iommu);
462 	if (dmaru->iommu)  in dmar_free_drhd()
463 		free_iommu(dmaru->iommu);  in dmar_free_drhd()
502 			drhd->iommu->node = node;  in dmar_parse_one_rhsa()
767 	pr_warn("No IOMMU scope found for ANDD enumeration ID %d (%s)\n",  in dmar_acpi_insert_dev_scope()
938 		x86_init.iommu.iommu_init = intel_iommu_init;  in detect_intel_iommu()
953 static void unmap_iommu(struct intel_iommu *iommu)  in unmap_iommu()  argument
955 	iounmap(iommu->reg);  in unmap_iommu()
956 	release_mem_region(iommu->reg_phys, iommu->reg_size);  in unmap_iommu()
960  * map_iommu: map the iommu's registers
961  * @iommu: the iommu to map
964  * Memory map the iommu's registers.  Start w/ a single page, and
967 static int map_iommu(struct intel_iommu *iommu, u64 phys_addr)  in map_iommu()  argument
971 	iommu->reg_phys = phys_addr;  in map_iommu()
972 	iommu->reg_size = VTD_PAGE_SIZE;  in map_iommu()
974 	if (!request_mem_region(iommu->reg_phys, iommu->reg_size, iommu->name)) {  in map_iommu()
980 	iommu->reg = ioremap(iommu->reg_phys, iommu->reg_size);  in map_iommu()
981 	if (!iommu->reg) {  in map_iommu()
987 	iommu->cap = dmar_readq(iommu->reg + DMAR_CAP_REG);  in map_iommu()
988 	iommu->ecap = dmar_readq(iommu->reg + DMAR_ECAP_REG);  in map_iommu()
990 	if (iommu->cap == (uint64_t)-1 && iommu->ecap == (uint64_t)-1) {  in map_iommu()
995 	if (ecap_vcs(iommu->ecap))  in map_iommu()
996 		iommu->vccap = dmar_readq(iommu->reg + DMAR_VCCAP_REG);  in map_iommu()
999 	map_size = max_t(int, ecap_max_iotlb_offset(iommu->ecap),  in map_iommu()
1000 			 cap_max_fault_reg_offset(iommu->cap));  in map_iommu()
1002 	if (map_size > iommu->reg_size) {  in map_iommu()
1003 		iounmap(iommu->reg);  in map_iommu()
1004 		release_mem_region(iommu->reg_phys, iommu->reg_size);  in map_iommu()
1005 		iommu->reg_size = map_size;  in map_iommu()
1006 		if (!request_mem_region(iommu->reg_phys, iommu->reg_size,  in map_iommu()
1007 					iommu->name)) {  in map_iommu()
1012 		iommu->reg = ioremap(iommu->reg_phys, iommu->reg_size);  in map_iommu()
1013 		if (!iommu->reg) {  in map_iommu()
1023 	iounmap(iommu->reg);  in map_iommu()
1025 	release_mem_region(iommu->reg_phys, iommu->reg_size);  in map_iommu()
1030 static int dmar_alloc_seq_id(struct intel_iommu *iommu)  in dmar_alloc_seq_id()  argument
1032 	iommu->seq_id = find_first_zero_bit(dmar_seq_ids,  in dmar_alloc_seq_id()
1034 	if (iommu->seq_id >= DMAR_UNITS_SUPPORTED) {  in dmar_alloc_seq_id()
1035 		iommu->seq_id = -1;  in dmar_alloc_seq_id()
1037 		set_bit(iommu->seq_id, dmar_seq_ids);  in dmar_alloc_seq_id()
1038 		sprintf(iommu->name, "dmar%d", iommu->seq_id);  in dmar_alloc_seq_id()
1041 	return iommu->seq_id;  in dmar_alloc_seq_id()
1044 static void dmar_free_seq_id(struct intel_iommu *iommu)  in dmar_free_seq_id()  argument
1046 	if (iommu->seq_id >= 0) {  in dmar_free_seq_id()
1047 		clear_bit(iommu->seq_id, dmar_seq_ids);  in dmar_free_seq_id()
1048 		iommu->seq_id = -1;  in dmar_free_seq_id()
1054 	struct intel_iommu *iommu;  in alloc_iommu()  local
1065 	iommu = kzalloc(sizeof(*iommu), GFP_KERNEL);  in alloc_iommu()
1066 	if (!iommu)  in alloc_iommu()
1069 	if (dmar_alloc_seq_id(iommu) < 0) {  in alloc_iommu()
1075 	err = map_iommu(iommu, drhd->reg_base_addr);  in alloc_iommu()
1077 		pr_err("Failed to map %s\n", iommu->name);  in alloc_iommu()
1082 	if (cap_sagaw(iommu->cap) == 0) {  in alloc_iommu()
1084 			iommu->name);  in alloc_iommu()
1089 		agaw = iommu_calculate_agaw(iommu);  in alloc_iommu()
1091 			pr_err("Cannot get a valid agaw for iommu (seq_id = %d)\n",  in alloc_iommu()
1092 			       iommu->seq_id);  in alloc_iommu()
1097 		msagaw = iommu_calculate_max_sagaw(iommu);  in alloc_iommu()
1099 			pr_err("Cannot get a valid max agaw for iommu (seq_id = %d)\n",  in alloc_iommu()
1100 			       iommu->seq_id);  in alloc_iommu()
1105 	iommu->agaw = agaw;  in alloc_iommu()
1106 	iommu->msagaw = msagaw;  in alloc_iommu()
1107 	iommu->segment = drhd->segment;  in alloc_iommu()
1109 	iommu->node = NUMA_NO_NODE;  in alloc_iommu()
1111 	ver = readl(iommu->reg + DMAR_VER_REG);  in alloc_iommu()
1113 		iommu->name,  in alloc_iommu()
1116 		(unsigned long long)iommu->cap,  in alloc_iommu()
1117 		(unsigned long long)iommu->ecap);  in alloc_iommu()
1120 	sts = readl(iommu->reg + DMAR_GSTS_REG);  in alloc_iommu()
1122 		iommu->gcmd |= DMA_GCMD_IRE;  in alloc_iommu()
1124 		iommu->gcmd |= DMA_GCMD_TE;  in alloc_iommu()
1126 		iommu->gcmd |= DMA_GCMD_QIE;  in alloc_iommu()
1128 	raw_spin_lock_init(&iommu->register_lock);  in alloc_iommu()
1136 		err = iommu_device_sysfs_add(&iommu->iommu, NULL,  in alloc_iommu()
1138 					     "%s", iommu->name);  in alloc_iommu()
1142 		err = iommu_device_register(&iommu->iommu, &intel_iommu_ops, NULL);  in alloc_iommu()
1147 	drhd->iommu = iommu;  in alloc_iommu()
1148 	iommu->drhd = drhd;  in alloc_iommu()
1153 	iommu_device_sysfs_remove(&iommu->iommu);  in alloc_iommu()
1155 	unmap_iommu(iommu);  in alloc_iommu()
1157 	dmar_free_seq_id(iommu);  in alloc_iommu()
1159 	kfree(iommu);  in alloc_iommu()
1163 static void free_iommu(struct intel_iommu *iommu)  in free_iommu()  argument
1165 	if (intel_iommu_enabled && !iommu->drhd->ignored) {  in free_iommu()
1166 		iommu_device_unregister(&iommu->iommu);  in free_iommu()
1167 		iommu_device_sysfs_remove(&iommu->iommu);  in free_iommu()
1170 	if (iommu->irq) {  in free_iommu()
1171 		if (iommu->pr_irq) {  in free_iommu()
1172 			free_irq(iommu->pr_irq, iommu);  in free_iommu()
1173 			dmar_free_hwirq(iommu->pr_irq);  in free_iommu()
1174 			iommu->pr_irq = 0;  in free_iommu()
1176 		free_irq(iommu->irq, iommu);  in free_iommu()
1177 		dmar_free_hwirq(iommu->irq);  in free_iommu()
1178 		iommu->irq = 0;  in free_iommu()
1181 	if (iommu->qi) {  in free_iommu()
1182 		free_page((unsigned long)iommu->qi->desc);  in free_iommu()
1183 		kfree(iommu->qi->desc_status);  in free_iommu()
1184 		kfree(iommu->qi);  in free_iommu()
1187 	if (iommu->reg)  in free_iommu()
1188 		unmap_iommu(iommu);  in free_iommu()
1190 	dmar_free_seq_id(iommu);  in free_iommu()
1191 	kfree(iommu);  in free_iommu()
1233 static void qi_dump_fault(struct intel_iommu *iommu, u32 fault)  in qi_dump_fault()  argument
1235 	unsigned int head = dmar_readl(iommu->reg + DMAR_IQH_REG);  in qi_dump_fault()
1236 	u64 iqe_err = dmar_readq(iommu->reg + DMAR_IQER_REG);  in qi_dump_fault()
1237 	struct qi_desc *desc = iommu->qi->desc + head;  in qi_dump_fault()
1254 	head = ((head >> qi_shift(iommu)) + QI_LENGTH - 1) % QI_LENGTH;  in qi_dump_fault()
1255 	head <<= qi_shift(iommu);  in qi_dump_fault()
1256 	desc = iommu->qi->desc + head;  in qi_dump_fault()
1264 static int qi_check_fault(struct intel_iommu *iommu, int index, int wait_index)  in qi_check_fault()  argument
1268 	struct q_inval *qi = iommu->qi;  in qi_check_fault()
1269 	int shift = qi_shift(iommu);  in qi_check_fault()
1274 	fault = readl(iommu->reg + DMAR_FSTS_REG);  in qi_check_fault()
1276 		qi_dump_fault(iommu, fault);  in qi_check_fault()
1284 		head = readl(iommu->reg + DMAR_IQH_REG);  in qi_check_fault()
1295 			writel(DMA_FSTS_IQE, iommu->reg + DMAR_FSTS_REG);  in qi_check_fault()
1306 		head = readl(iommu->reg + DMAR_IQH_REG);  in qi_check_fault()
1309 		tail = readl(iommu->reg + DMAR_IQT_REG);  in qi_check_fault()
1312 		writel(DMA_FSTS_ITE, iommu->reg + DMAR_FSTS_REG);  in qi_check_fault()
1326 		writel(DMA_FSTS_ICE, iommu->reg + DMAR_FSTS_REG);  in qi_check_fault()
1340 int qi_submit_sync(struct intel_iommu *iommu, struct qi_desc *desc,  in qi_submit_sync()  argument
1343 	struct q_inval *qi = iommu->qi;  in qi_submit_sync()
1360 	    dmar_latency_enabled(iommu, DMAR_LATENCY_INV_IOTLB))  in qi_submit_sync()
1364 	    dmar_latency_enabled(iommu, DMAR_LATENCY_INV_DEVTLB))  in qi_submit_sync()
1368 	    dmar_latency_enabled(iommu, DMAR_LATENCY_INV_IEC))  in qi_submit_sync()
1388 	shift = qi_shift(iommu);  in qi_submit_sync()
1394 		trace_qi_submit(iommu, desc[i].qw0, desc[i].qw1,  in qi_submit_sync()
1417 	writel(qi->free_head << shift, iommu->reg + DMAR_IQT_REG);  in qi_submit_sync()
1427 		rc = qi_check_fault(iommu, index, wait_index);  in qi_submit_sync()
1446 		dmar_latency_update(iommu, DMAR_LATENCY_INV_IOTLB,  in qi_submit_sync()
1450 		dmar_latency_update(iommu, DMAR_LATENCY_INV_DEVTLB,  in qi_submit_sync()
1454 		dmar_latency_update(iommu, DMAR_LATENCY_INV_IEC,  in qi_submit_sync()
1463 void qi_global_iec(struct intel_iommu *iommu)  in qi_global_iec()  argument
1473 	qi_submit_sync(iommu, &desc, 1, 0);  in qi_global_iec()
1476 void qi_flush_context(struct intel_iommu *iommu, u16 did, u16 sid, u8 fm,  in qi_flush_context()  argument
1487 	qi_submit_sync(iommu, &desc, 1, 0);  in qi_flush_context()
1490 void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,  in qi_flush_iotlb()  argument
1498 	if (cap_write_drain(iommu->cap))  in qi_flush_iotlb()
1501 	if (cap_read_drain(iommu->cap))  in qi_flush_iotlb()
1511 	qi_submit_sync(iommu, &desc, 1, 0);  in qi_flush_iotlb()
1514 void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 pfsid,  in qi_flush_dev_iotlb()  argument
1533 	qi_submit_sync(iommu, &desc, 1, 0);  in qi_flush_dev_iotlb()
1537 void qi_flush_piotlb(struct intel_iommu *iommu, u16 did, u32 pasid, u64 addr,  in qi_flush_piotlb()  argument
1574 	qi_submit_sync(iommu, &desc, 1, 0);  in qi_flush_piotlb()
1578 void qi_flush_dev_iotlb_pasid(struct intel_iommu *iommu, u16 sid, u16 pfsid,  in qi_flush_dev_iotlb_pasid()  argument
1618 	qi_submit_sync(iommu, &desc, 1, 0);  in qi_flush_dev_iotlb_pasid()
1621 void qi_flush_pasid_cache(struct intel_iommu *iommu, u16 did,  in qi_flush_pasid_cache()  argument
1628 	qi_submit_sync(iommu, &desc, 1, 0);  in qi_flush_pasid_cache()
1634 void dmar_disable_qi(struct intel_iommu *iommu)  in dmar_disable_qi()  argument
1640 	if (!ecap_qis(iommu->ecap))  in dmar_disable_qi()
1643 	raw_spin_lock_irqsave(&iommu->register_lock, flags);  in dmar_disable_qi()
1645 	sts =  readl(iommu->reg + DMAR_GSTS_REG);  in dmar_disable_qi()
1652 	while ((readl(iommu->reg + DMAR_IQT_REG) !=  in dmar_disable_qi()
1653 		readl(iommu->reg + DMAR_IQH_REG)) &&  in dmar_disable_qi()
1657 	iommu->gcmd &= ~DMA_GCMD_QIE;  in dmar_disable_qi()
1658 	writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);  in dmar_disable_qi()
1660 	IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl,  in dmar_disable_qi()
1663 	raw_spin_unlock_irqrestore(&iommu->register_lock, flags);  in dmar_disable_qi()
1669 static void __dmar_enable_qi(struct intel_iommu *iommu)  in __dmar_enable_qi()  argument
1673 	struct q_inval *qi = iommu->qi;  in __dmar_enable_qi()
1683 	if (ecap_smts(iommu->ecap))  in __dmar_enable_qi()
1686 	raw_spin_lock_irqsave(&iommu->register_lock, flags);  in __dmar_enable_qi()
1689 	writel(0, iommu->reg + DMAR_IQT_REG);  in __dmar_enable_qi()
1691 	dmar_writeq(iommu->reg + DMAR_IQA_REG, val);  in __dmar_enable_qi()
1693 	iommu->gcmd |= DMA_GCMD_QIE;  in __dmar_enable_qi()
1694 	writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);  in __dmar_enable_qi()
1697 	IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl, (sts & DMA_GSTS_QIES), sts);  in __dmar_enable_qi()
1699 	raw_spin_unlock_irqrestore(&iommu->register_lock, flags);  in __dmar_enable_qi()
1707 int dmar_enable_qi(struct intel_iommu *iommu)  in dmar_enable_qi()  argument
1712 	if (!ecap_qis(iommu->ecap))  in dmar_enable_qi()
1718 	if (iommu->qi)  in dmar_enable_qi()
1721 	iommu->qi = kmalloc(sizeof(*qi), GFP_ATOMIC);  in dmar_enable_qi()
1722 	if (!iommu->qi)  in dmar_enable_qi()
1725 	qi = iommu->qi;  in dmar_enable_qi()
1731 	desc_page = alloc_pages_node(iommu->node, GFP_ATOMIC | __GFP_ZERO,  in dmar_enable_qi()
1732 				     !!ecap_smts(iommu->ecap));  in dmar_enable_qi()
1735 		iommu->qi = NULL;  in dmar_enable_qi()
1745 		iommu->qi = NULL;  in dmar_enable_qi()
1751 	__dmar_enable_qi(iommu);  in dmar_enable_qi()
1756 /* iommu interrupt handling. Most stuff are MSI-like. */
1871 static inline int dmar_msi_reg(struct intel_iommu *iommu, int irq)  in dmar_msi_reg()  argument
1873 	if (iommu->irq == irq)  in dmar_msi_reg()
1875 	else if (iommu->pr_irq == irq)  in dmar_msi_reg()
1883 	struct intel_iommu *iommu = irq_data_get_irq_handler_data(data);  in dmar_msi_unmask()  local
1884 	int reg = dmar_msi_reg(iommu, data->irq);  in dmar_msi_unmask()
1888 	raw_spin_lock_irqsave(&iommu->register_lock, flag);  in dmar_msi_unmask()
1889 	writel(0, iommu->reg + reg);  in dmar_msi_unmask()
1891 	readl(iommu->reg + reg);  in dmar_msi_unmask()
1892 	raw_spin_unlock_irqrestore(&iommu->register_lock, flag);  in dmar_msi_unmask()
1897 	struct intel_iommu *iommu = irq_data_get_irq_handler_data(data);  in dmar_msi_mask()  local
1898 	int reg = dmar_msi_reg(iommu, data->irq);  in dmar_msi_mask()
1902 	raw_spin_lock_irqsave(&iommu->register_lock, flag);  in dmar_msi_mask()
1903 	writel(DMA_FECTL_IM, iommu->reg + reg);  in dmar_msi_mask()
1905 	readl(iommu->reg + reg);  in dmar_msi_mask()
1906 	raw_spin_unlock_irqrestore(&iommu->register_lock, flag);  in dmar_msi_mask()
1911 	struct intel_iommu *iommu = irq_get_handler_data(irq);  in dmar_msi_write()  local
1912 	int reg = dmar_msi_reg(iommu, irq);  in dmar_msi_write()
1915 	raw_spin_lock_irqsave(&iommu->register_lock, flag);  in dmar_msi_write()
1916 	writel(msg->data, iommu->reg + reg + 4);  in dmar_msi_write()
1917 	writel(msg->address_lo, iommu->reg + reg + 8);  in dmar_msi_write()
1918 	writel(msg->address_hi, iommu->reg + reg + 12);  in dmar_msi_write()
1919 	raw_spin_unlock_irqrestore(&iommu->register_lock, flag);  in dmar_msi_write()
1924 	struct intel_iommu *iommu = irq_get_handler_data(irq);  in dmar_msi_read()  local
1925 	int reg = dmar_msi_reg(iommu, irq);  in dmar_msi_read()
1928 	raw_spin_lock_irqsave(&iommu->register_lock, flag);  in dmar_msi_read()
1929 	msg->data = readl(iommu->reg + reg + 4);  in dmar_msi_read()
1930 	msg->address_lo = readl(iommu->reg + reg + 8);  in dmar_msi_read()
1931 	msg->address_hi = readl(iommu->reg + reg + 12);  in dmar_msi_read()
1932 	raw_spin_unlock_irqrestore(&iommu->register_lock, flag);  in dmar_msi_read()
1935 static int dmar_fault_do_one(struct intel_iommu *iommu, int type,  in dmar_fault_do_one()  argument
1968 	struct intel_iommu *iommu = dev_id;  in dmar_fault()  local
1976 	raw_spin_lock_irqsave(&iommu->register_lock, flag);  in dmar_fault()
1977 	fault_status = readl(iommu->reg + DMAR_FSTS_REG);  in dmar_fault()
1986 	reg = cap_fault_reg_offset(iommu->cap);  in dmar_fault()
1999 		data = readl(iommu->reg + reg +  in dmar_fault()
2009 			data = readl(iommu->reg + reg +  in dmar_fault()
2014 			guest_addr = dmar_readq(iommu->reg + reg +  in dmar_fault()
2020 		writel(DMA_FRCD_F, iommu->reg + reg +  in dmar_fault()
2023 		raw_spin_unlock_irqrestore(&iommu->register_lock, flag);  in dmar_fault()
2027 			dmar_fault_do_one(iommu, type, fault_reason,  in dmar_fault()
2032 		if (fault_index >= cap_num_fault_regs(iommu->cap))  in dmar_fault()
2034 		raw_spin_lock_irqsave(&iommu->register_lock, flag);  in dmar_fault()
2038 	       iommu->reg + DMAR_FSTS_REG);  in dmar_fault()
2041 	raw_spin_unlock_irqrestore(&iommu->register_lock, flag);  in dmar_fault()
2045 int dmar_set_interrupt(struct intel_iommu *iommu)  in dmar_set_interrupt()  argument
2052 	if (iommu->irq)  in dmar_set_interrupt()
2055 	irq = dmar_alloc_hwirq(iommu->seq_id, iommu->node, iommu);  in dmar_set_interrupt()
2057 		iommu->irq = irq;  in dmar_set_interrupt()
2063 	ret = request_irq(irq, dmar_fault, IRQF_NO_THREAD, iommu->name, iommu);  in dmar_set_interrupt()
2072 	struct intel_iommu *iommu;  in enable_drhd_fault_handling()  local
2077 	for_each_iommu(iommu, drhd) {  in enable_drhd_fault_handling()
2079 		int ret = dmar_set_interrupt(iommu);  in enable_drhd_fault_handling()
2090 		dmar_fault(iommu->irq, iommu);  in enable_drhd_fault_handling()
2091 		fault_status = readl(iommu->reg + DMAR_FSTS_REG);  in enable_drhd_fault_handling()
2092 		writel(fault_status, iommu->reg + DMAR_FSTS_REG);  in enable_drhd_fault_handling()
2101 int dmar_reenable_qi(struct intel_iommu *iommu)  in dmar_reenable_qi()  argument
2103 	if (!ecap_qis(iommu->ecap))  in dmar_reenable_qi()
2106 	if (!iommu->qi)  in dmar_reenable_qi()
2112 	dmar_disable_qi(iommu);  in dmar_reenable_qi()
2118 	__dmar_enable_qi(iommu);  in dmar_reenable_qi()