Lines Matching +full:m +full:- +full:mode
1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/intel-iommu.h>
114 static int iommu_regset_show(struct seq_file *m, void *unused) in iommu_regset_show() argument
124 if (!drhd->reg_base_addr) { in iommu_regset_show()
125 seq_puts(m, "IOMMU: Invalid base address\n"); in iommu_regset_show()
126 ret = -EINVAL; in iommu_regset_show()
130 seq_printf(m, "IOMMU: %s Register Base Address: %llx\n", in iommu_regset_show()
131 iommu->name, drhd->reg_base_addr); in iommu_regset_show()
132 seq_puts(m, "Name\t\t\tOffset\t\tContents\n"); in iommu_regset_show()
134 * Publish the contents of the 64-bit hardware registers in iommu_regset_show()
137 raw_spin_lock_irqsave(&iommu->register_lock, flag); in iommu_regset_show()
139 value = dmar_readl(iommu->reg + iommu_regs_32[i].offset); in iommu_regset_show()
140 seq_printf(m, "%-16s\t0x%02x\t\t0x%016llx\n", in iommu_regset_show()
145 value = dmar_readq(iommu->reg + iommu_regs_64[i].offset); in iommu_regset_show()
146 seq_printf(m, "%-16s\t0x%02x\t\t0x%016llx\n", in iommu_regset_show()
150 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in iommu_regset_show()
151 seq_putc(m, '\n'); in iommu_regset_show()
160 static inline void print_tbl_walk(struct seq_file *m) in print_tbl_walk() argument
162 struct tbl_walk *tbl_wlk = m->private; in print_tbl_walk()
164 seq_printf(m, "%02x:%02x.%x\t0x%016llx:0x%016llx\t0x%016llx:0x%016llx\t", in print_tbl_walk()
165 tbl_wlk->bus, PCI_SLOT(tbl_wlk->devfn), in print_tbl_walk()
166 PCI_FUNC(tbl_wlk->devfn), tbl_wlk->rt_entry->hi, in print_tbl_walk()
167 tbl_wlk->rt_entry->lo, tbl_wlk->ctx_entry->hi, in print_tbl_walk()
168 tbl_wlk->ctx_entry->lo); in print_tbl_walk()
171 * A legacy mode DMAR doesn't support PASID, hence default it to -1 in print_tbl_walk()
175 if (!tbl_wlk->pasid_tbl_entry) in print_tbl_walk()
176 seq_printf(m, "%-6d\t0x%016llx:0x%016llx:0x%016llx\n", -1, in print_tbl_walk()
179 seq_printf(m, "%-6d\t0x%016llx:0x%016llx:0x%016llx\n", in print_tbl_walk()
180 tbl_wlk->pasid, tbl_wlk->pasid_tbl_entry->val[2], in print_tbl_walk()
181 tbl_wlk->pasid_tbl_entry->val[1], in print_tbl_walk()
182 tbl_wlk->pasid_tbl_entry->val[0]); in print_tbl_walk()
185 static void pasid_tbl_walk(struct seq_file *m, struct pasid_entry *tbl_entry, in pasid_tbl_walk() argument
188 struct tbl_walk *tbl_wlk = m->private; in pasid_tbl_walk()
193 tbl_wlk->pasid_tbl_entry = tbl_entry; in pasid_tbl_walk()
194 tbl_wlk->pasid = (dir_idx << PASID_PDE_SHIFT) + tbl_idx; in pasid_tbl_walk()
195 print_tbl_walk(m); in pasid_tbl_walk()
202 static void pasid_dir_walk(struct seq_file *m, u64 pasid_dir_ptr, in pasid_dir_walk() argument
212 pasid_tbl_walk(m, pasid_tbl, dir_idx); in pasid_dir_walk()
218 static void ctx_tbl_walk(struct seq_file *m, struct intel_iommu *iommu, u16 bus) in ctx_tbl_walk() argument
228 * Scalable mode root entry points to upper scalable mode in ctx_tbl_walk()
229 * context table and lower scalable mode context table. Each in ctx_tbl_walk()
230 * scalable mode context table has 128 context entries where as in ctx_tbl_walk()
231 * legacy mode context table has 256 context entries. So in in ctx_tbl_walk()
232 * scalable mode, the context entries for former 128 devices are in ctx_tbl_walk()
233 * in the lower scalable mode context table, while the latter in ctx_tbl_walk()
234 * 128 devices are in the upper scalable mode context table. in ctx_tbl_walk()
235 * In scalable mode, when devfn > 127, iommu_context_addr() in ctx_tbl_walk()
236 * automatically refers to upper scalable mode context table and in ctx_tbl_walk()
238 * between scalable mode and non scalable mode. in ctx_tbl_walk()
249 tbl_wlk.rt_entry = &iommu->root_entry[bus]; in ctx_tbl_walk()
251 m->private = &tbl_wlk; in ctx_tbl_walk()
253 if (dmar_readq(iommu->reg + DMAR_RTADDR_REG) & DMA_RTADDR_SMT) { in ctx_tbl_walk()
254 pasid_dir_ptr = context->lo & VTD_PAGE_MASK; in ctx_tbl_walk()
256 pasid_dir_walk(m, pasid_dir_ptr, pasid_dir_size); in ctx_tbl_walk()
260 print_tbl_walk(m); in ctx_tbl_walk()
264 static void root_tbl_walk(struct seq_file *m, struct intel_iommu *iommu) in root_tbl_walk() argument
269 spin_lock_irqsave(&iommu->lock, flags); in root_tbl_walk()
270 seq_printf(m, "IOMMU %s: Root Table Address: 0x%llx\n", iommu->name, in root_tbl_walk()
271 (u64)virt_to_phys(iommu->root_entry)); in root_tbl_walk()
272 seq_puts(m, "B.D.F\tRoot_entry\t\t\t\tContext_entry\t\t\t\tPASID\tPASID_table_entry\n"); in root_tbl_walk()
280 ctx_tbl_walk(m, iommu, bus); in root_tbl_walk()
282 spin_unlock_irqrestore(&iommu->lock, flags); in root_tbl_walk()
285 static int dmar_translation_struct_show(struct seq_file *m, void *unused) in dmar_translation_struct_show() argument
293 sts = dmar_readl(iommu->reg + DMAR_GSTS_REG); in dmar_translation_struct_show()
295 seq_printf(m, "DMA Remapping is not enabled on %s\n", in dmar_translation_struct_show()
296 iommu->name); in dmar_translation_struct_show()
299 root_tbl_walk(m, iommu); in dmar_translation_struct_show()
300 seq_putc(m, '\n'); in dmar_translation_struct_show()
310 return BIT_ULL(VTD_PAGE_SHIFT + VTD_STRIDE_SHIFT * (level - 1)); in level_to_directory_size()
314 dump_page_info(struct seq_file *m, unsigned long iova, u64 *path) in dump_page_info() argument
316 seq_printf(m, "0x%013lx |\t0x%016llx\t0x%016llx\t0x%016llx\t0x%016llx\t0x%016llx\n", in dump_page_info()
321 static void pgtable_walk_level(struct seq_file *m, struct dma_pte *pde, in pgtable_walk_level() argument
335 path[level] = pde->val; in pgtable_walk_level()
337 dump_page_info(m, start, path); in pgtable_walk_level()
339 pgtable_walk_level(m, phys_to_virt(dma_pte_addr(pde)), in pgtable_walk_level()
340 level - 1, start, path); in pgtable_walk_level()
348 struct seq_file *m = data; in show_device_domain_translation() local
354 seq_printf(m, "Device %s with pasid %d @0x%llx\n", in show_device_domain_translation()
355 dev_name(dev), domain->default_pasid, in show_device_domain_translation()
356 (u64)virt_to_phys(domain->pgd)); in show_device_domain_translation()
357 seq_puts(m, "IOVA_PFN\t\tPML5E\t\t\tPML4E\t\t\tPDPE\t\t\tPDE\t\t\tPTE\n"); in show_device_domain_translation()
359 pgtable_walk_level(m, domain->pgd, domain->agaw + 2, 0, path); in show_device_domain_translation()
360 seq_putc(m, '\n'); in show_device_domain_translation()
365 static int domain_translation_struct_show(struct seq_file *m, void *unused) in domain_translation_struct_show() argument
371 ret = bus_for_each_dev(&pci_bus_type, NULL, m, in domain_translation_struct_show()
379 static void invalidation_queue_entry_show(struct seq_file *m, in invalidation_queue_entry_show() argument
386 if (ecap_smts(iommu->ecap)) in invalidation_queue_entry_show()
387 seq_puts(m, "Index\t\tqw0\t\t\tqw1\t\t\tqw2\t\t\tqw3\t\t\tstatus\n"); in invalidation_queue_entry_show()
389 seq_puts(m, "Index\t\tqw0\t\t\tqw1\t\t\tstatus\n"); in invalidation_queue_entry_show()
393 desc = iommu->qi->desc + offset; in invalidation_queue_entry_show()
394 if (ecap_smts(iommu->ecap)) in invalidation_queue_entry_show()
395 seq_printf(m, "%5d\t%016llx\t%016llx\t%016llx\t%016llx\t%016x\n", in invalidation_queue_entry_show()
396 index, desc->qw0, desc->qw1, in invalidation_queue_entry_show()
397 desc->qw2, desc->qw3, in invalidation_queue_entry_show()
398 iommu->qi->desc_status[index]); in invalidation_queue_entry_show()
400 seq_printf(m, "%5d\t%016llx\t%016llx\t%016x\n", in invalidation_queue_entry_show()
401 index, desc->qw0, desc->qw1, in invalidation_queue_entry_show()
402 iommu->qi->desc_status[index]); in invalidation_queue_entry_show()
406 static int invalidation_queue_show(struct seq_file *m, void *unused) in invalidation_queue_show() argument
416 qi = iommu->qi; in invalidation_queue_show()
419 if (!qi || !ecap_qis(iommu->ecap)) in invalidation_queue_show()
422 seq_printf(m, "Invalidation queue on IOMMU: %s\n", iommu->name); in invalidation_queue_show()
424 raw_spin_lock_irqsave(&qi->q_lock, flags); in invalidation_queue_show()
425 seq_printf(m, " Base: 0x%llx\tHead: %lld\tTail: %lld\n", in invalidation_queue_show()
426 (u64)virt_to_phys(qi->desc), in invalidation_queue_show()
427 dmar_readq(iommu->reg + DMAR_IQH_REG) >> shift, in invalidation_queue_show()
428 dmar_readq(iommu->reg + DMAR_IQT_REG) >> shift); in invalidation_queue_show()
429 invalidation_queue_entry_show(m, iommu); in invalidation_queue_show()
430 raw_spin_unlock_irqrestore(&qi->q_lock, flags); in invalidation_queue_show()
431 seq_putc(m, '\n'); in invalidation_queue_show()
440 static void ir_tbl_remap_entry_show(struct seq_file *m, in ir_tbl_remap_entry_show() argument
447 seq_puts(m, " Entry SrcID DstID Vct IRTE_high\t\tIRTE_low\n"); in ir_tbl_remap_entry_show()
451 ri_entry = &iommu->ir_table->base[idx]; in ir_tbl_remap_entry_show()
452 if (!ri_entry->present || ri_entry->p_pst) in ir_tbl_remap_entry_show()
455 seq_printf(m, " %-5d %02x:%02x.%01x %08x %02x %016llx\t%016llx\n", in ir_tbl_remap_entry_show()
456 idx, PCI_BUS_NUM(ri_entry->sid), in ir_tbl_remap_entry_show()
457 PCI_SLOT(ri_entry->sid), PCI_FUNC(ri_entry->sid), in ir_tbl_remap_entry_show()
458 ri_entry->dest_id, ri_entry->vector, in ir_tbl_remap_entry_show()
459 ri_entry->high, ri_entry->low); in ir_tbl_remap_entry_show()
464 static void ir_tbl_posted_entry_show(struct seq_file *m, in ir_tbl_posted_entry_show() argument
471 seq_puts(m, " Entry SrcID PDA_high PDA_low Vct IRTE_high\t\tIRTE_low\n"); in ir_tbl_posted_entry_show()
475 pi_entry = &iommu->ir_table->base[idx]; in ir_tbl_posted_entry_show()
476 if (!pi_entry->present || !pi_entry->p_pst) in ir_tbl_posted_entry_show()
479 seq_printf(m, " %-5d %02x:%02x.%01x %08x %08x %02x %016llx\t%016llx\n", in ir_tbl_posted_entry_show()
480 idx, PCI_BUS_NUM(pi_entry->sid), in ir_tbl_posted_entry_show()
481 PCI_SLOT(pi_entry->sid), PCI_FUNC(pi_entry->sid), in ir_tbl_posted_entry_show()
482 pi_entry->pda_h, pi_entry->pda_l << 6, in ir_tbl_posted_entry_show()
483 pi_entry->vector, pi_entry->high, in ir_tbl_posted_entry_show()
484 pi_entry->low); in ir_tbl_posted_entry_show()
494 static int ir_translation_struct_show(struct seq_file *m, void *unused) in ir_translation_struct_show() argument
503 if (!ecap_ir_support(iommu->ecap)) in ir_translation_struct_show()
506 seq_printf(m, "Remapped Interrupt supported on IOMMU: %s\n", in ir_translation_struct_show()
507 iommu->name); in ir_translation_struct_show()
509 sts = dmar_readl(iommu->reg + DMAR_GSTS_REG); in ir_translation_struct_show()
510 if (iommu->ir_table && (sts & DMA_GSTS_IRES)) { in ir_translation_struct_show()
511 irta = virt_to_phys(iommu->ir_table->base); in ir_translation_struct_show()
512 seq_printf(m, " IR table address:%llx\n", irta); in ir_translation_struct_show()
513 ir_tbl_remap_entry_show(m, iommu); in ir_translation_struct_show()
515 seq_puts(m, "Interrupt Remapping is not enabled\n"); in ir_translation_struct_show()
517 seq_putc(m, '\n'); in ir_translation_struct_show()
520 seq_puts(m, "****\n\n"); in ir_translation_struct_show()
523 if (!cap_pi_support(iommu->cap)) in ir_translation_struct_show()
526 seq_printf(m, "Posted Interrupt supported on IOMMU: %s\n", in ir_translation_struct_show()
527 iommu->name); in ir_translation_struct_show()
529 if (iommu->ir_table) { in ir_translation_struct_show()
530 irta = virt_to_phys(iommu->ir_table->base); in ir_translation_struct_show()
531 seq_printf(m, " IR table address:%llx\n", irta); in ir_translation_struct_show()
532 ir_tbl_posted_entry_show(m, iommu); in ir_translation_struct_show()
534 seq_puts(m, "Interrupt Remapping is not enabled\n"); in ir_translation_struct_show()
536 seq_putc(m, '\n'); in ir_translation_struct_show()
545 static void latency_show_one(struct seq_file *m, struct intel_iommu *iommu, in latency_show_one() argument
550 seq_printf(m, "IOMMU: %s Register Base Address: %llx\n", in latency_show_one()
551 iommu->name, drhd->reg_base_addr); in latency_show_one()
555 seq_puts(m, "Failed to get latency snapshot"); in latency_show_one()
557 seq_puts(m, debug_buf); in latency_show_one()
558 seq_puts(m, "\n"); in latency_show_one()
561 static int latency_show(struct seq_file *m, void *v) in latency_show() argument
568 latency_show_one(m, iommu, drhd); in latency_show()
592 return -EFAULT; in dmar_perf_latency_write()
597 return -EINVAL; in dmar_perf_latency_write()
635 return -EINVAL; in dmar_perf_latency_write()