1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/adreno-smmu-priv.h>
11 #include "arm-smmu.h"
36 	if (qsmmu->stall_enabled & BIT(idx))  in qcom_adreno_smmu_write_sctlr()
46 	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;  in qcom_adreno_smmu_get_fault_info()
47 	struct arm_smmu_device *smmu = smmu_domain->smmu;  in qcom_adreno_smmu_get_fault_info()
49 	info->fsr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSR);  in qcom_adreno_smmu_get_fault_info()
50 	info->fsynr0 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR0);  in qcom_adreno_smmu_get_fault_info()
51 	info->fsynr1 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR1);  in qcom_adreno_smmu_get_fault_info()
52 	info->far = arm_smmu_cb_readq(smmu, cfg->cbndx, ARM_SMMU_CB_FAR);  in qcom_adreno_smmu_get_fault_info()
53 	info->cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(cfg->cbndx));  in qcom_adreno_smmu_get_fault_info()
54 	info->ttbr0 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_TTBR0);  in qcom_adreno_smmu_get_fault_info()
55 	info->contextidr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_CONTEXTIDR);  in qcom_adreno_smmu_get_fault_info()
61 	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;  in qcom_adreno_smmu_set_stall()
62 	struct qcom_smmu *qsmmu = to_qcom_smmu(smmu_domain->smmu);  in qcom_adreno_smmu_set_stall()
65 		qsmmu->stall_enabled |= BIT(cfg->cbndx);  in qcom_adreno_smmu_set_stall()
67 		qsmmu->stall_enabled &= ~BIT(cfg->cbndx);  in qcom_adreno_smmu_set_stall()
73 	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;  in qcom_adreno_smmu_resume_translation()
74 	struct arm_smmu_device *smmu = smmu_domain->smmu;  in qcom_adreno_smmu_resume_translation()
80 	arm_smmu_cb_write(smmu, cfg->cbndx, ARM_SMMU_CB_RESUME, reg);  in qcom_adreno_smmu_resume_translation()
92 	 * identify it and configure it for per-instance pagetables  in qcom_adreno_smmu_is_gpu_device()
94 	for (i = 0; i < fwspec->num_ids; i++) {  in qcom_adreno_smmu_is_gpu_device()
95 		u16 sid = FIELD_GET(ARM_SMMU_SMR_ID, fwspec->ids[i]);  in qcom_adreno_smmu_is_gpu_device()
109 		io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops);  in qcom_adreno_smmu_get_ttbr1_cfg()
110 	return &pgtable->cfg;  in qcom_adreno_smmu_get_ttbr1_cfg()
115  * The GPU driver will call this to enable TTBR0 when per-instance pagetables
123 	struct io_pgtable *pgtable = io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops);  in qcom_adreno_smmu_set_ttbr0_cfg()
124 	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;  in qcom_adreno_smmu_set_ttbr0_cfg()
125 	struct arm_smmu_cb *cb = &smmu_domain->smmu->cbs[cfg->cbndx];  in qcom_adreno_smmu_set_ttbr0_cfg()
128 	if (cb->tcr[0] & ARM_SMMU_TCR_EPD1)  in qcom_adreno_smmu_set_ttbr0_cfg()
129 		return -EINVAL;  in qcom_adreno_smmu_set_ttbr0_cfg()
134 		if ((cb->tcr[0] & ARM_SMMU_TCR_EPD0))  in qcom_adreno_smmu_set_ttbr0_cfg()
135 			return -EINVAL;  in qcom_adreno_smmu_set_ttbr0_cfg()
138 		cb->tcr[0] = arm_smmu_lpae_tcr(&pgtable->cfg);  in qcom_adreno_smmu_set_ttbr0_cfg()
139 		cb->ttbr[0] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid);  in qcom_adreno_smmu_set_ttbr0_cfg()
141 		u32 tcr = cb->tcr[0];  in qcom_adreno_smmu_set_ttbr0_cfg()
144 		if (!(cb->tcr[0] & ARM_SMMU_TCR_EPD0))  in qcom_adreno_smmu_set_ttbr0_cfg()
145 			return -EINVAL;  in qcom_adreno_smmu_set_ttbr0_cfg()
150 		cb->tcr[0] = tcr;  in qcom_adreno_smmu_set_ttbr0_cfg()
151 		cb->ttbr[0] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr;  in qcom_adreno_smmu_set_ttbr0_cfg()
152 		cb->ttbr[0] |= FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid);  in qcom_adreno_smmu_set_ttbr0_cfg()
155 	arm_smmu_write_context_bank(smmu_domain->smmu, cb->cfg->cbndx);  in qcom_adreno_smmu_set_ttbr0_cfg()
175 		count = smmu->num_context_banks;  in qcom_adreno_smmu_alloc_context_bank()
178 	return __arm_smmu_alloc_bitmap(smmu->context_map, start, count);  in qcom_adreno_smmu_alloc_context_bank()
183 	const struct device_node *np = smmu->dev->of_node;  in qcom_adreno_can_do_ttbr1()
185 	if (of_device_is_compatible(np, "qcom,msm8996-smmu-v2"))  in qcom_adreno_can_do_ttbr1()
196 	smmu_domain->cfg.flush_walk_prefer_tlbiasid = true;  in qcom_adreno_smmu_init_context()
203 	 * All targets that use the qcom,adreno-smmu compatible string *should*  in qcom_adreno_smmu_init_context()
204 	 * be AARCH64 stage 1 but double check because the arm-smmu code assumes  in qcom_adreno_smmu_init_context()
207 	if (qcom_adreno_can_do_ttbr1(smmu_domain->smmu) &&  in qcom_adreno_smmu_init_context()
208 	    (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) &&  in qcom_adreno_smmu_init_context()
209 	    (smmu_domain->cfg.fmt == ARM_SMMU_CTX_FMT_AARCH64))  in qcom_adreno_smmu_init_context()
210 		pgtbl_cfg->quirks |= IO_PGTABLE_QUIRK_ARM_TTBR1;  in qcom_adreno_smmu_init_context()
217 	priv->cookie = smmu_domain;  in qcom_adreno_smmu_init_context()
218 	priv->get_ttbr1_cfg = qcom_adreno_smmu_get_ttbr1_cfg;  in qcom_adreno_smmu_init_context()
219 	priv->set_ttbr0_cfg = qcom_adreno_smmu_set_ttbr0_cfg;  in qcom_adreno_smmu_init_context()
220 	priv->get_fault_info = qcom_adreno_smmu_get_fault_info;  in qcom_adreno_smmu_init_context()
221 	priv->set_stall = qcom_adreno_smmu_set_stall;  in qcom_adreno_smmu_init_context()
222 	priv->resume_translation = qcom_adreno_smmu_resume_translation;  in qcom_adreno_smmu_init_context()
231 	{ .compatible = "qcom,sc7180-mdss" },
232 	{ .compatible = "qcom,sc7180-mss-pil" },
233 	{ .compatible = "qcom,sc7280-mdss" },
234 	{ .compatible = "qcom,sc8180x-mdss" },
235 	{ .compatible = "qcom,sdm845-mdss" },
236 	{ .compatible = "qcom,sdm845-mss-pil" },
243 	smmu_domain->cfg.flush_walk_prefer_tlbiasid = true;  in qcom_smmu_init_context()
250 	unsigned int last_s2cr = ARM_SMMU_GR0_S2CR(smmu->num_mapping_groups - 1);  in qcom_smmu_cfg_probe()
268 		qsmmu->bypass_quirk = true;  in qcom_smmu_cfg_probe()
269 		qsmmu->bypass_cbndx = smmu->num_context_banks - 1;  in qcom_smmu_cfg_probe()
271 		set_bit(qsmmu->bypass_cbndx, smmu->context_map);  in qcom_smmu_cfg_probe()
273 		arm_smmu_cb_write(smmu, qsmmu->bypass_cbndx, ARM_SMMU_CB_SCTLR, 0);  in qcom_smmu_cfg_probe()
276 		arm_smmu_gr1_write(smmu, ARM_SMMU_GR1_CBAR(qsmmu->bypass_cbndx), reg);  in qcom_smmu_cfg_probe()
279 	for (i = 0; i < smmu->num_mapping_groups; i++) {  in qcom_smmu_cfg_probe()
285 			smmu->smrs[i].id = FIELD_GET(ARM_SMMU_SMR_ID, smr);  in qcom_smmu_cfg_probe()
286 			smmu->smrs[i].mask = FIELD_GET(ARM_SMMU_SMR_MASK, smr);  in qcom_smmu_cfg_probe()
287 			smmu->smrs[i].valid = true;  in qcom_smmu_cfg_probe()
289 			smmu->s2crs[i].type = S2CR_TYPE_BYPASS;  in qcom_smmu_cfg_probe()
290 			smmu->s2crs[i].privcfg = S2CR_PRIVCFG_DEFAULT;  in qcom_smmu_cfg_probe()
291 			smmu->s2crs[i].cbndx = 0xff;  in qcom_smmu_cfg_probe()
300 	struct arm_smmu_s2cr *s2cr = smmu->s2crs + idx;  in qcom_smmu_write_s2cr()
302 	u32 cbndx = s2cr->cbndx;  in qcom_smmu_write_s2cr()
303 	u32 type = s2cr->type;  in qcom_smmu_write_s2cr()
306 	if (qsmmu->bypass_quirk) {  in qcom_smmu_write_s2cr()
315 			cbndx = qsmmu->bypass_cbndx;  in qcom_smmu_write_s2cr()
329 	      FIELD_PREP(ARM_SMMU_S2CR_PRIVCFG, s2cr->privcfg);  in qcom_smmu_write_s2cr()
346 	 * To address performance degradation in non-real time clients,  in qcom_sdm845_smmu500_reset()
347 	 * such as USB and UFS, turn off wait-for-safe on sdm845 based boards,  in qcom_sdm845_smmu500_reset()
349 	 * call handlers to turn on/off the wait-for-safe logic.  in qcom_sdm845_smmu500_reset()
353 		dev_warn(smmu->dev, "Failed to turn off SAFE logic\n");  in qcom_sdm845_smmu500_reset()
360 	const struct device_node *np = smmu->dev->of_node;  in qcom_smmu500_reset()
364 	if (of_device_is_compatible(np, "qcom,sdm845-smmu-500"))  in qcom_smmu500_reset()
393 		return ERR_PTR(-EPROBE_DEFER);  in qcom_smmu_create()
395 	qsmmu = devm_krealloc(smmu->dev, smmu, sizeof(*qsmmu), GFP_KERNEL);  in qcom_smmu_create()
397 		return ERR_PTR(-ENOMEM);  in qcom_smmu_create()
399 	qsmmu->smmu.impl = impl;  in qcom_smmu_create()
401 	return &qsmmu->smmu;  in qcom_smmu_create()
405 	{ .compatible = "qcom,msm8998-smmu-v2" },
406 	{ .compatible = "qcom,sc7180-smmu-500" },
407 	{ .compatible = "qcom,sc7280-smmu-500" },
408 	{ .compatible = "qcom,sc8180x-smmu-500" },
409 	{ .compatible = "qcom,sdm630-smmu-v2" },
410 	{ .compatible = "qcom,sdm845-smmu-500" },
411 	{ .compatible = "qcom,sm6125-smmu-500" },
412 	{ .compatible = "qcom,sm8150-smmu-500" },
413 	{ .compatible = "qcom,sm8250-smmu-500" },
414 	{ .compatible = "qcom,sm8350-smmu-500" },
420 	{ "LENOVO", "CB-01   ", 0x8180, ACPI_SIG_IORT, equal, "QCOM SMMU" },
428 	const struct device_node *np = smmu->dev->of_node;  in qcom_smmu_impl_init()
441 	 * arm,mmu-500 in which case we will miss setting adreno smmu specific  in qcom_smmu_impl_init()
444 	if (of_device_is_compatible(np, "qcom,adreno-smmu"))  in qcom_smmu_impl_init()