Lines Matching +full:broken +full:- +full:prefetch +full:- +full:cmd
1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/dma-iommu.h>
20 #include <linux/io-pgtable.h>
28 #include <linux/pci-ats.h>
33 #include "arm-smmu-v3.h"
34 #include "../../iommu-sva-lib.h"
44 "Disable MSI-based polling for CMD_SYNC completion.");
86 { ARM_SMMU_OPT_SKIP_PREFETCH, "hisilicon,broken-prefetch-cmd" },
87 { ARM_SMMU_OPT_PAGE0_REGS_ONLY, "cavium,cn9900-broken-page1-regspace"},
96 if (of_property_read_bool(smmu->dev->of_node, in parse_driver_options()
98 smmu->options |= arm_smmu_options[i].opt; in parse_driver_options()
99 dev_notice(smmu->dev, "option %s\n", in parse_driver_options()
105 /* Low-level queue manipulation functions */
110 prod = Q_IDX(q, q->prod); in queue_has_space()
111 cons = Q_IDX(q, q->cons); in queue_has_space()
113 if (Q_WRP(q, q->prod) == Q_WRP(q, q->cons)) in queue_has_space()
114 space = (1 << q->max_n_shift) - (prod - cons); in queue_has_space()
116 space = cons - prod; in queue_has_space()
123 return Q_IDX(q, q->prod) == Q_IDX(q, q->cons) && in queue_full()
124 Q_WRP(q, q->prod) != Q_WRP(q, q->cons); in queue_full()
129 return Q_IDX(q, q->prod) == Q_IDX(q, q->cons) && in queue_empty()
130 Q_WRP(q, q->prod) == Q_WRP(q, q->cons); in queue_empty()
135 return ((Q_WRP(q, q->cons) == Q_WRP(q, prod)) && in queue_consumed()
136 (Q_IDX(q, q->cons) > Q_IDX(q, prod))) || in queue_consumed()
137 ((Q_WRP(q, q->cons) != Q_WRP(q, prod)) && in queue_consumed()
138 (Q_IDX(q, q->cons) <= Q_IDX(q, prod))); in queue_consumed()
148 writel_relaxed(q->llq.cons, q->cons_reg); in queue_sync_cons_out()
153 u32 cons = (Q_WRP(q, q->cons) | Q_IDX(q, q->cons)) + 1; in queue_inc_cons()
154 q->cons = Q_OVF(q->cons) | Q_WRP(q, cons) | Q_IDX(q, cons); in queue_inc_cons()
167 prod = readl(q->prod_reg); in queue_sync_prod_in()
169 if (Q_OVF(prod) != Q_OVF(q->llq.prod)) in queue_sync_prod_in()
170 ret = -EOVERFLOW; in queue_sync_prod_in()
172 q->llq.prod = prod; in queue_sync_prod_in()
178 u32 prod = (Q_WRP(q, q->prod) | Q_IDX(q, q->prod)) + n; in queue_inc_prod_n()
179 return Q_OVF(q->prod) | Q_WRP(q, prod) | Q_IDX(q, prod); in queue_inc_prod_n()
185 qp->delay = 1; in queue_poll_init()
186 qp->spin_cnt = 0; in queue_poll_init()
187 qp->wfe = !!(smmu->features & ARM_SMMU_FEAT_SEV); in queue_poll_init()
188 qp->timeout = ktime_add_us(ktime_get(), ARM_SMMU_POLL_TIMEOUT_US); in queue_poll_init()
193 if (ktime_compare(ktime_get(), qp->timeout) > 0) in queue_poll()
194 return -ETIMEDOUT; in queue_poll()
196 if (qp->wfe) { in queue_poll()
198 } else if (++qp->spin_cnt < ARM_SMMU_POLL_SPIN_COUNT) { in queue_poll()
201 udelay(qp->delay); in queue_poll()
202 qp->delay *= 2; in queue_poll()
203 qp->spin_cnt = 0; in queue_poll()
227 if (queue_empty(&q->llq)) in queue_remove_raw()
228 return -EAGAIN; in queue_remove_raw()
230 queue_read(ent, Q_ENT(q, q->llq.cons), q->ent_dwords); in queue_remove_raw()
231 queue_inc_cons(&q->llq); in queue_remove_raw()
236 /* High-level queue accessors */
237 static int arm_smmu_cmdq_build_cmd(u64 *cmd, struct arm_smmu_cmdq_ent *ent) in arm_smmu_cmdq_build_cmd() argument
239 memset(cmd, 0, 1 << CMDQ_ENT_SZ_SHIFT); in arm_smmu_cmdq_build_cmd()
240 cmd[0] |= FIELD_PREP(CMDQ_0_OP, ent->opcode); in arm_smmu_cmdq_build_cmd()
242 switch (ent->opcode) { in arm_smmu_cmdq_build_cmd()
247 cmd[0] |= FIELD_PREP(CMDQ_PREFETCH_0_SID, ent->prefetch.sid); in arm_smmu_cmdq_build_cmd()
250 cmd[0] |= FIELD_PREP(CMDQ_CFGI_0_SSID, ent->cfgi.ssid); in arm_smmu_cmdq_build_cmd()
253 cmd[0] |= FIELD_PREP(CMDQ_CFGI_0_SID, ent->cfgi.sid); in arm_smmu_cmdq_build_cmd()
254 cmd[1] |= FIELD_PREP(CMDQ_CFGI_1_LEAF, ent->cfgi.leaf); in arm_smmu_cmdq_build_cmd()
257 cmd[0] |= FIELD_PREP(CMDQ_CFGI_0_SID, ent->cfgi.sid); in arm_smmu_cmdq_build_cmd()
261 cmd[1] |= FIELD_PREP(CMDQ_CFGI_1_RANGE, 31); in arm_smmu_cmdq_build_cmd()
264 cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_VMID, ent->tlbi.vmid); in arm_smmu_cmdq_build_cmd()
267 cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_NUM, ent->tlbi.num); in arm_smmu_cmdq_build_cmd()
268 cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_SCALE, ent->tlbi.scale); in arm_smmu_cmdq_build_cmd()
269 cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_ASID, ent->tlbi.asid); in arm_smmu_cmdq_build_cmd()
270 cmd[1] |= FIELD_PREP(CMDQ_TLBI_1_LEAF, ent->tlbi.leaf); in arm_smmu_cmdq_build_cmd()
271 cmd[1] |= FIELD_PREP(CMDQ_TLBI_1_TTL, ent->tlbi.ttl); in arm_smmu_cmdq_build_cmd()
272 cmd[1] |= FIELD_PREP(CMDQ_TLBI_1_TG, ent->tlbi.tg); in arm_smmu_cmdq_build_cmd()
273 cmd[1] |= ent->tlbi.addr & CMDQ_TLBI_1_VA_MASK; in arm_smmu_cmdq_build_cmd()
276 cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_NUM, ent->tlbi.num); in arm_smmu_cmdq_build_cmd()
277 cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_SCALE, ent->tlbi.scale); in arm_smmu_cmdq_build_cmd()
278 cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_VMID, ent->tlbi.vmid); in arm_smmu_cmdq_build_cmd()
279 cmd[1] |= FIELD_PREP(CMDQ_TLBI_1_LEAF, ent->tlbi.leaf); in arm_smmu_cmdq_build_cmd()
280 cmd[1] |= FIELD_PREP(CMDQ_TLBI_1_TTL, ent->tlbi.ttl); in arm_smmu_cmdq_build_cmd()
281 cmd[1] |= FIELD_PREP(CMDQ_TLBI_1_TG, ent->tlbi.tg); in arm_smmu_cmdq_build_cmd()
282 cmd[1] |= ent->tlbi.addr & CMDQ_TLBI_1_IPA_MASK; in arm_smmu_cmdq_build_cmd()
285 cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_ASID, ent->tlbi.asid); in arm_smmu_cmdq_build_cmd()
288 cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_VMID, ent->tlbi.vmid); in arm_smmu_cmdq_build_cmd()
291 cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_ASID, ent->tlbi.asid); in arm_smmu_cmdq_build_cmd()
294 cmd[0] |= FIELD_PREP(CMDQ_0_SSV, ent->substream_valid); in arm_smmu_cmdq_build_cmd()
295 cmd[0] |= FIELD_PREP(CMDQ_ATC_0_GLOBAL, ent->atc.global); in arm_smmu_cmdq_build_cmd()
296 cmd[0] |= FIELD_PREP(CMDQ_ATC_0_SSID, ent->atc.ssid); in arm_smmu_cmdq_build_cmd()
297 cmd[0] |= FIELD_PREP(CMDQ_ATC_0_SID, ent->atc.sid); in arm_smmu_cmdq_build_cmd()
298 cmd[1] |= FIELD_PREP(CMDQ_ATC_1_SIZE, ent->atc.size); in arm_smmu_cmdq_build_cmd()
299 cmd[1] |= ent->atc.addr & CMDQ_ATC_1_ADDR_MASK; in arm_smmu_cmdq_build_cmd()
302 cmd[0] |= FIELD_PREP(CMDQ_0_SSV, ent->substream_valid); in arm_smmu_cmdq_build_cmd()
303 cmd[0] |= FIELD_PREP(CMDQ_PRI_0_SSID, ent->pri.ssid); in arm_smmu_cmdq_build_cmd()
304 cmd[0] |= FIELD_PREP(CMDQ_PRI_0_SID, ent->pri.sid); in arm_smmu_cmdq_build_cmd()
305 cmd[1] |= FIELD_PREP(CMDQ_PRI_1_GRPID, ent->pri.grpid); in arm_smmu_cmdq_build_cmd()
306 switch (ent->pri.resp) { in arm_smmu_cmdq_build_cmd()
312 return -EINVAL; in arm_smmu_cmdq_build_cmd()
314 cmd[1] |= FIELD_PREP(CMDQ_PRI_1_RESP, ent->pri.resp); in arm_smmu_cmdq_build_cmd()
317 cmd[0] |= FIELD_PREP(CMDQ_RESUME_0_SID, ent->resume.sid); in arm_smmu_cmdq_build_cmd()
318 cmd[0] |= FIELD_PREP(CMDQ_RESUME_0_RESP, ent->resume.resp); in arm_smmu_cmdq_build_cmd()
319 cmd[1] |= FIELD_PREP(CMDQ_RESUME_1_STAG, ent->resume.stag); in arm_smmu_cmdq_build_cmd()
322 if (ent->sync.msiaddr) { in arm_smmu_cmdq_build_cmd()
323 cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_IRQ); in arm_smmu_cmdq_build_cmd()
324 cmd[1] |= ent->sync.msiaddr & CMDQ_SYNC_1_MSIADDR_MASK; in arm_smmu_cmdq_build_cmd()
326 cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_SEV); in arm_smmu_cmdq_build_cmd()
328 cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_MSH, ARM_SMMU_SH_ISH); in arm_smmu_cmdq_build_cmd()
329 cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_MSIATTR, ARM_SMMU_MEMATTR_OIWB); in arm_smmu_cmdq_build_cmd()
332 return -ENOENT; in arm_smmu_cmdq_build_cmd()
340 return &smmu->cmdq; in arm_smmu_get_cmdq()
343 static void arm_smmu_cmdq_build_sync_cmd(u64 *cmd, struct arm_smmu_device *smmu, in arm_smmu_cmdq_build_sync_cmd() argument
354 if (smmu->options & ARM_SMMU_OPT_MSIPOLL) { in arm_smmu_cmdq_build_sync_cmd()
355 ent.sync.msiaddr = q->base_dma + Q_IDX(&q->llq, prod) * in arm_smmu_cmdq_build_sync_cmd()
356 q->ent_dwords * 8; in arm_smmu_cmdq_build_sync_cmd()
359 arm_smmu_cmdq_build_cmd(cmd, &ent); in arm_smmu_cmdq_build_sync_cmd()
373 u64 cmd[CMDQ_ENT_DWORDS]; in __arm_smmu_cmdq_skip_err() local
374 u32 cons = readl_relaxed(q->cons_reg); in __arm_smmu_cmdq_skip_err()
380 dev_err(smmu->dev, "CMDQ error (cons 0x%08x): %s\n", cons, in __arm_smmu_cmdq_skip_err()
385 dev_err(smmu->dev, "retrying command fetch\n"); in __arm_smmu_cmdq_skip_err()
406 queue_read(cmd, Q_ENT(q, cons), q->ent_dwords); in __arm_smmu_cmdq_skip_err()
407 dev_err(smmu->dev, "skipping command in error state:\n"); in __arm_smmu_cmdq_skip_err()
408 for (i = 0; i < ARRAY_SIZE(cmd); ++i) in __arm_smmu_cmdq_skip_err()
409 dev_err(smmu->dev, "\t0x%016llx\n", (unsigned long long)cmd[i]); in __arm_smmu_cmdq_skip_err()
412 if (arm_smmu_cmdq_build_cmd(cmd, &cmd_sync)) { in __arm_smmu_cmdq_skip_err()
413 dev_err(smmu->dev, "failed to convert to CMD_SYNC\n"); in __arm_smmu_cmdq_skip_err()
417 queue_write(Q_ENT(q, cons), cmd, q->ent_dwords); in __arm_smmu_cmdq_skip_err()
422 __arm_smmu_cmdq_skip_err(smmu, &smmu->cmdq.q); in arm_smmu_cmdq_skip_err()
429 * - The only LOCK routines are exclusive_trylock() and shared_lock().
433 * - The UNLOCK routines are supplemented with shared_tryunlock(), which
447 if (atomic_fetch_inc_relaxed(&cmdq->lock) >= 0) in arm_smmu_cmdq_shared_lock()
451 val = atomic_cond_read_relaxed(&cmdq->lock, VAL >= 0); in arm_smmu_cmdq_shared_lock()
452 } while (atomic_cmpxchg_relaxed(&cmdq->lock, val, val + 1) != val); in arm_smmu_cmdq_shared_lock()
457 (void)atomic_dec_return_release(&cmdq->lock); in arm_smmu_cmdq_shared_unlock()
462 if (atomic_read(&cmdq->lock) == 1) in arm_smmu_cmdq_shared_tryunlock()
473 __ret = !atomic_cmpxchg_relaxed(&cmdq->lock, 0, INT_MIN); \
481 atomic_set_release(&cmdq->lock, 0); \
490 * you like mixed-size concurrency, dependency ordering and relaxed atomics,
530 .max_n_shift = cmdq->q.llq.max_n_shift, in __arm_smmu_cmdq_poll_set_valid_map()
545 ptr = &cmdq->valid_map[swidx]; in __arm_smmu_cmdq_poll_set_valid_map()
550 mask = GENMASK(limit - 1, sbidx); in __arm_smmu_cmdq_poll_set_valid_map()
554 * that a zero-initialised queue is invalid and, after marking in __arm_smmu_cmdq_poll_set_valid_map()
567 llq.prod = queue_inc_prod_n(&llq, limit - sbidx); in __arm_smmu_cmdq_poll_set_valid_map()
585 /* Wait for the command queue to become non-full */
599 WRITE_ONCE(cmdq->q.llq.cons, readl_relaxed(cmdq->q.cons_reg)); in arm_smmu_cmdq_poll_until_not_full()
601 llq->val = READ_ONCE(cmdq->q.llq.val); in arm_smmu_cmdq_poll_until_not_full()
607 llq->val = READ_ONCE(cmdq->q.llq.val); in arm_smmu_cmdq_poll_until_not_full()
627 u32 *cmd = (u32 *)(Q_ENT(&cmdq->q, llq->prod)); in __arm_smmu_cmdq_poll_until_msi() local
636 smp_cond_load_relaxed(cmd, !VAL || (ret = queue_poll(&qp))); in __arm_smmu_cmdq_poll_until_msi()
637 llq->cons = ret ? llq->prod : queue_inc_prod_n(llq, 1); in __arm_smmu_cmdq_poll_until_msi()
642 * Wait until the SMMU cons index passes llq->prod.
650 u32 prod = llq->prod; in __arm_smmu_cmdq_poll_until_consumed()
654 llq->val = READ_ONCE(cmdq->q.llq.val); in __arm_smmu_cmdq_poll_until_consumed()
669 * cmdq->q.llq.cons. Roughly speaking: in __arm_smmu_cmdq_poll_until_consumed()
689 llq->cons = readl(cmdq->q.cons_reg); in __arm_smmu_cmdq_poll_until_consumed()
698 if (smmu->options & ARM_SMMU_OPT_MSIPOLL) in arm_smmu_cmdq_poll_until_sync()
709 .max_n_shift = cmdq->q.llq.max_n_shift, in arm_smmu_cmdq_write_entries()
714 u64 *cmd = &cmds[i * CMDQ_ENT_DWORDS]; in arm_smmu_cmdq_write_entries() local
717 queue_write(Q_ENT(&cmdq->q, prod), cmd, CMDQ_ENT_DWORDS); in arm_smmu_cmdq_write_entries()
725 * - There is a dma_wmb() before publishing any commands to the queue.
729 * - On completion of a CMD_SYNC, there is a control dependency.
733 * - Command insertion is totally ordered, so if two CPUs each race to
748 llq.max_n_shift = cmdq->q.llq.max_n_shift; in arm_smmu_cmdq_issue_cmdlist()
752 llq.val = READ_ONCE(cmdq->q.llq.val); in arm_smmu_cmdq_issue_cmdlist()
759 dev_err_ratelimited(smmu->dev, "CMDQ timeout\n"); in arm_smmu_cmdq_issue_cmdlist()
767 old = cmpxchg_relaxed(&cmdq->q.llq.val, llq.val, head.val); in arm_smmu_cmdq_issue_cmdlist()
784 arm_smmu_cmdq_build_sync_cmd(cmd_sync, smmu, &cmdq->q, prod); in arm_smmu_cmdq_issue_cmdlist()
785 queue_write(Q_ENT(&cmdq->q, prod), cmd_sync, CMDQ_ENT_DWORDS); in arm_smmu_cmdq_issue_cmdlist()
803 atomic_cond_read_relaxed(&cmdq->owner_prod, VAL == llq.prod); in arm_smmu_cmdq_issue_cmdlist()
807 &cmdq->q.llq.atomic.prod); in arm_smmu_cmdq_issue_cmdlist()
821 writel_relaxed(prod, cmdq->q.prod_reg); in arm_smmu_cmdq_issue_cmdlist()
828 atomic_set_release(&cmdq->owner_prod, prod); in arm_smmu_cmdq_issue_cmdlist()
836 dev_err_ratelimited(smmu->dev, in arm_smmu_cmdq_issue_cmdlist()
839 readl_relaxed(cmdq->q.prod_reg), in arm_smmu_cmdq_issue_cmdlist()
840 readl_relaxed(cmdq->q.cons_reg)); in arm_smmu_cmdq_issue_cmdlist()
845 * reader, in which case we can safely update cmdq->q.llq.cons in arm_smmu_cmdq_issue_cmdlist()
848 WRITE_ONCE(cmdq->q.llq.cons, llq.cons); in arm_smmu_cmdq_issue_cmdlist()
861 u64 cmd[CMDQ_ENT_DWORDS]; in __arm_smmu_cmdq_issue_cmd() local
863 if (arm_smmu_cmdq_build_cmd(cmd, ent)) { in __arm_smmu_cmdq_issue_cmd()
864 dev_warn(smmu->dev, "ignoring unknown CMDQ opcode 0x%x\n", in __arm_smmu_cmdq_issue_cmd()
865 ent->opcode); in __arm_smmu_cmdq_issue_cmd()
866 return -EINVAL; in __arm_smmu_cmdq_issue_cmd()
869 return arm_smmu_cmdq_issue_cmdlist(smmu, cmd, 1, sync); in __arm_smmu_cmdq_issue_cmd()
886 struct arm_smmu_cmdq_ent *cmd) in arm_smmu_cmdq_batch_add() argument
888 if (cmds->num == CMDQ_BATCH_ENTRIES) { in arm_smmu_cmdq_batch_add()
889 arm_smmu_cmdq_issue_cmdlist(smmu, cmds->cmds, cmds->num, false); in arm_smmu_cmdq_batch_add()
890 cmds->num = 0; in arm_smmu_cmdq_batch_add()
892 arm_smmu_cmdq_build_cmd(&cmds->cmds[cmds->num * CMDQ_ENT_DWORDS], cmd); in arm_smmu_cmdq_batch_add()
893 cmds->num++; in arm_smmu_cmdq_batch_add()
899 return arm_smmu_cmdq_issue_cmdlist(smmu, cmds->cmds, cmds->num, true); in arm_smmu_cmdq_batch_submit()
906 struct arm_smmu_cmdq_ent cmd = {0}; in arm_smmu_page_response() local
908 int sid = master->streams[0].id; in arm_smmu_page_response()
910 if (master->stall_enabled) { in arm_smmu_page_response()
911 cmd.opcode = CMDQ_OP_RESUME; in arm_smmu_page_response()
912 cmd.resume.sid = sid; in arm_smmu_page_response()
913 cmd.resume.stag = resp->grpid; in arm_smmu_page_response()
914 switch (resp->code) { in arm_smmu_page_response()
917 cmd.resume.resp = CMDQ_RESUME_0_RESP_ABORT; in arm_smmu_page_response()
920 cmd.resume.resp = CMDQ_RESUME_0_RESP_RETRY; in arm_smmu_page_response()
923 return -EINVAL; in arm_smmu_page_response()
926 return -ENODEV; in arm_smmu_page_response()
929 arm_smmu_cmdq_issue_cmd(master->smmu, &cmd); in arm_smmu_page_response()
943 struct arm_smmu_cmdq_ent cmd = { in arm_smmu_tlb_inv_asid() local
944 .opcode = smmu->features & ARM_SMMU_FEAT_E2H ? in arm_smmu_tlb_inv_asid()
949 arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); in arm_smmu_tlb_inv_asid()
959 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_sync_cd()
960 struct arm_smmu_cmdq_ent cmd = { in arm_smmu_sync_cd() local
970 spin_lock_irqsave(&smmu_domain->devices_lock, flags); in arm_smmu_sync_cd()
971 list_for_each_entry(master, &smmu_domain->devices, domain_head) { in arm_smmu_sync_cd()
972 for (i = 0; i < master->num_streams; i++) { in arm_smmu_sync_cd()
973 cmd.cfgi.sid = master->streams[i].id; in arm_smmu_sync_cd()
974 arm_smmu_cmdq_batch_add(smmu, &cmds, &cmd); in arm_smmu_sync_cd()
977 spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); in arm_smmu_sync_cd()
987 l1_desc->l2ptr = dmam_alloc_coherent(smmu->dev, size, in arm_smmu_alloc_cd_leaf_table()
988 &l1_desc->l2ptr_dma, GFP_KERNEL); in arm_smmu_alloc_cd_leaf_table()
989 if (!l1_desc->l2ptr) { in arm_smmu_alloc_cd_leaf_table()
990 dev_warn(smmu->dev, in arm_smmu_alloc_cd_leaf_table()
992 return -ENOMEM; in arm_smmu_alloc_cd_leaf_table()
1000 u64 val = (l1_desc->l2ptr_dma & CTXDESC_L1_DESC_L2PTR_MASK) | in arm_smmu_write_cd_l1_desc()
1013 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_get_cd_ptr()
1014 struct arm_smmu_ctx_desc_cfg *cdcfg = &smmu_domain->s1_cfg.cdcfg; in arm_smmu_get_cd_ptr()
1016 if (smmu_domain->s1_cfg.s1fmt == STRTAB_STE_0_S1FMT_LINEAR) in arm_smmu_get_cd_ptr()
1017 return cdcfg->cdtab + ssid * CTXDESC_CD_DWORDS; in arm_smmu_get_cd_ptr()
1020 l1_desc = &cdcfg->l1_desc[idx]; in arm_smmu_get_cd_ptr()
1021 if (!l1_desc->l2ptr) { in arm_smmu_get_cd_ptr()
1025 l1ptr = cdcfg->cdtab + idx * CTXDESC_L1_DESC_DWORDS; in arm_smmu_get_cd_ptr()
1030 idx = ssid & (CTXDESC_L2_ENTRIES - 1); in arm_smmu_get_cd_ptr()
1031 return l1_desc->l2ptr + idx * CTXDESC_CD_DWORDS; in arm_smmu_get_cd_ptr()
1052 if (WARN_ON(ssid >= (1 << smmu_domain->s1_cfg.s1cdmax))) in arm_smmu_write_ctx_desc()
1053 return -E2BIG; in arm_smmu_write_ctx_desc()
1057 return -ENOMEM; in arm_smmu_write_ctx_desc()
1068 val |= FIELD_PREP(CTXDESC_CD_0_ASID, cd->asid); in arm_smmu_write_ctx_desc()
1074 cdptr[1] = cpu_to_le64(cd->ttbr & CTXDESC_CD_1_TTB0_MASK); in arm_smmu_write_ctx_desc()
1076 cdptr[3] = cpu_to_le64(cd->mair); in arm_smmu_write_ctx_desc()
1085 val = cd->tcr | in arm_smmu_write_ctx_desc()
1090 (cd->mm ? 0 : CTXDESC_CD_0_ASET) | in arm_smmu_write_ctx_desc()
1092 FIELD_PREP(CTXDESC_CD_0_ASID, cd->asid) | in arm_smmu_write_ctx_desc()
1095 if (smmu_domain->stall_enabled) in arm_smmu_write_ctx_desc()
1100 * The SMMU accesses 64-bit values atomically. See IHI0070Ca 3.21.3 in arm_smmu_write_ctx_desc()
1103 * The size of single-copy atomic reads made by the SMMU is in arm_smmu_write_ctx_desc()
1105 * field within an aligned 64-bit span of a structure can be altered in arm_smmu_write_ctx_desc()
1118 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_alloc_cd_tables()
1119 struct arm_smmu_s1_cfg *cfg = &smmu_domain->s1_cfg; in arm_smmu_alloc_cd_tables()
1120 struct arm_smmu_ctx_desc_cfg *cdcfg = &cfg->cdcfg; in arm_smmu_alloc_cd_tables()
1122 max_contexts = 1 << cfg->s1cdmax; in arm_smmu_alloc_cd_tables()
1124 if (!(smmu->features & ARM_SMMU_FEAT_2_LVL_CDTAB) || in arm_smmu_alloc_cd_tables()
1126 cfg->s1fmt = STRTAB_STE_0_S1FMT_LINEAR; in arm_smmu_alloc_cd_tables()
1127 cdcfg->num_l1_ents = max_contexts; in arm_smmu_alloc_cd_tables()
1131 cfg->s1fmt = STRTAB_STE_0_S1FMT_64K_L2; in arm_smmu_alloc_cd_tables()
1132 cdcfg->num_l1_ents = DIV_ROUND_UP(max_contexts, in arm_smmu_alloc_cd_tables()
1135 cdcfg->l1_desc = devm_kcalloc(smmu->dev, cdcfg->num_l1_ents, in arm_smmu_alloc_cd_tables()
1136 sizeof(*cdcfg->l1_desc), in arm_smmu_alloc_cd_tables()
1138 if (!cdcfg->l1_desc) in arm_smmu_alloc_cd_tables()
1139 return -ENOMEM; in arm_smmu_alloc_cd_tables()
1141 l1size = cdcfg->num_l1_ents * (CTXDESC_L1_DESC_DWORDS << 3); in arm_smmu_alloc_cd_tables()
1144 cdcfg->cdtab = dmam_alloc_coherent(smmu->dev, l1size, &cdcfg->cdtab_dma, in arm_smmu_alloc_cd_tables()
1146 if (!cdcfg->cdtab) { in arm_smmu_alloc_cd_tables()
1147 dev_warn(smmu->dev, "failed to allocate context descriptor\n"); in arm_smmu_alloc_cd_tables()
1148 ret = -ENOMEM; in arm_smmu_alloc_cd_tables()
1155 if (cdcfg->l1_desc) { in arm_smmu_alloc_cd_tables()
1156 devm_kfree(smmu->dev, cdcfg->l1_desc); in arm_smmu_alloc_cd_tables()
1157 cdcfg->l1_desc = NULL; in arm_smmu_alloc_cd_tables()
1166 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_free_cd_tables()
1167 struct arm_smmu_ctx_desc_cfg *cdcfg = &smmu_domain->s1_cfg.cdcfg; in arm_smmu_free_cd_tables()
1169 if (cdcfg->l1_desc) { in arm_smmu_free_cd_tables()
1172 for (i = 0; i < cdcfg->num_l1_ents; i++) { in arm_smmu_free_cd_tables()
1173 if (!cdcfg->l1_desc[i].l2ptr) in arm_smmu_free_cd_tables()
1176 dmam_free_coherent(smmu->dev, size, in arm_smmu_free_cd_tables()
1177 cdcfg->l1_desc[i].l2ptr, in arm_smmu_free_cd_tables()
1178 cdcfg->l1_desc[i].l2ptr_dma); in arm_smmu_free_cd_tables()
1180 devm_kfree(smmu->dev, cdcfg->l1_desc); in arm_smmu_free_cd_tables()
1181 cdcfg->l1_desc = NULL; in arm_smmu_free_cd_tables()
1183 l1size = cdcfg->num_l1_ents * (CTXDESC_L1_DESC_DWORDS << 3); in arm_smmu_free_cd_tables()
1185 l1size = cdcfg->num_l1_ents * (CTXDESC_CD_DWORDS << 3); in arm_smmu_free_cd_tables()
1188 dmam_free_coherent(smmu->dev, l1size, cdcfg->cdtab, cdcfg->cdtab_dma); in arm_smmu_free_cd_tables()
1189 cdcfg->cdtab_dma = 0; in arm_smmu_free_cd_tables()
1190 cdcfg->cdtab = NULL; in arm_smmu_free_cd_tables()
1198 if (!cd->asid) in arm_smmu_free_asid()
1201 free = refcount_dec_and_test(&cd->refs); in arm_smmu_free_asid()
1203 old_cd = xa_erase(&arm_smmu_asid_xa, cd->asid); in arm_smmu_free_asid()
1215 val |= FIELD_PREP(STRTAB_L1_DESC_SPAN, desc->span); in arm_smmu_write_strtab_l1_desc()
1216 val |= desc->l2ptr_dma & STRTAB_L1_DESC_L2PTR_MASK; in arm_smmu_write_strtab_l1_desc()
1224 struct arm_smmu_cmdq_ent cmd = { in arm_smmu_sync_ste_for_sid() local
1232 arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); in arm_smmu_sync_ste_for_sid()
1242 * 1. Invalid (all zero) -> bypass/fault (init) in arm_smmu_write_strtab_ent()
1243 * 2. Bypass/fault -> translation/bypass (attach) in arm_smmu_write_strtab_ent()
1244 * 3. Translation/bypass -> bypass/fault (detach) in arm_smmu_write_strtab_ent()
1262 .prefetch = { in arm_smmu_write_strtab_ent()
1268 smmu_domain = master->domain; in arm_smmu_write_strtab_ent()
1269 smmu = master->smmu; in arm_smmu_write_strtab_ent()
1273 switch (smmu_domain->stage) { in arm_smmu_write_strtab_ent()
1275 s1_cfg = &smmu_domain->s1_cfg; in arm_smmu_write_strtab_ent()
1279 s2_cfg = &smmu_domain->s2_cfg; in arm_smmu_write_strtab_ent()
1326 u64 strw = smmu->features & ARM_SMMU_FEAT_E2H ? in arm_smmu_write_strtab_ent()
1337 if (smmu->features & ARM_SMMU_FEAT_STALLS && in arm_smmu_write_strtab_ent()
1338 !master->stall_enabled) in arm_smmu_write_strtab_ent()
1341 val |= (s1_cfg->cdcfg.cdtab_dma & STRTAB_STE_0_S1CTXPTR_MASK) | in arm_smmu_write_strtab_ent()
1343 FIELD_PREP(STRTAB_STE_0_S1CDMAX, s1_cfg->s1cdmax) | in arm_smmu_write_strtab_ent()
1344 FIELD_PREP(STRTAB_STE_0_S1FMT, s1_cfg->s1fmt); in arm_smmu_write_strtab_ent()
1350 FIELD_PREP(STRTAB_STE_2_S2VMID, s2_cfg->vmid) | in arm_smmu_write_strtab_ent()
1351 FIELD_PREP(STRTAB_STE_2_VTCR, s2_cfg->vtcr) | in arm_smmu_write_strtab_ent()
1358 dst[3] = cpu_to_le64(s2_cfg->vttbr & STRTAB_STE_3_S2TTB_MASK); in arm_smmu_write_strtab_ent()
1363 if (master->ats_enabled) in arm_smmu_write_strtab_ent()
1373 if (!(smmu->options & ARM_SMMU_OPT_SKIP_PREFETCH)) in arm_smmu_write_strtab_ent()
1382 arm_smmu_write_strtab_ent(NULL, -1, strtab); in arm_smmu_init_bypass_stes()
1391 struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; in arm_smmu_init_l2_strtab()
1392 struct arm_smmu_strtab_l1_desc *desc = &cfg->l1_desc[sid >> STRTAB_SPLIT]; in arm_smmu_init_l2_strtab()
1394 if (desc->l2ptr) in arm_smmu_init_l2_strtab()
1398 strtab = &cfg->strtab[(sid >> STRTAB_SPLIT) * STRTAB_L1_DESC_DWORDS]; in arm_smmu_init_l2_strtab()
1400 desc->span = STRTAB_SPLIT + 1; in arm_smmu_init_l2_strtab()
1401 desc->l2ptr = dmam_alloc_coherent(smmu->dev, size, &desc->l2ptr_dma, in arm_smmu_init_l2_strtab()
1403 if (!desc->l2ptr) { in arm_smmu_init_l2_strtab()
1404 dev_err(smmu->dev, in arm_smmu_init_l2_strtab()
1407 return -ENOMEM; in arm_smmu_init_l2_strtab()
1410 arm_smmu_init_bypass_stes(desc->l2ptr, 1 << STRTAB_SPLIT); in arm_smmu_init_l2_strtab()
1421 lockdep_assert_held(&smmu->streams_mutex); in arm_smmu_find_master()
1423 node = smmu->streams.rb_node; in arm_smmu_find_master()
1426 if (stream->id < sid) in arm_smmu_find_master()
1427 node = node->rb_right; in arm_smmu_find_master()
1428 else if (stream->id > sid) in arm_smmu_find_master()
1429 node = node->rb_left; in arm_smmu_find_master()
1431 return stream->master; in arm_smmu_find_master()
1463 return -EOPNOTSUPP; in arm_smmu_handle_evt()
1466 /* Stage-2 is always pinned at the moment */ in arm_smmu_handle_evt()
1468 return -EFAULT; in arm_smmu_handle_evt()
1482 flt->type = IOMMU_FAULT_PAGE_REQ; in arm_smmu_handle_evt()
1483 flt->prm = (struct iommu_fault_page_request) { in arm_smmu_handle_evt()
1491 flt->prm.flags |= IOMMU_FAULT_PAGE_REQUEST_PASID_VALID; in arm_smmu_handle_evt()
1492 flt->prm.pasid = FIELD_GET(EVTQ_0_SSID, evt[0]); in arm_smmu_handle_evt()
1495 flt->type = IOMMU_FAULT_DMA_UNRECOV; in arm_smmu_handle_evt()
1496 flt->event = (struct iommu_fault_unrecoverable) { in arm_smmu_handle_evt()
1504 flt->event.flags |= IOMMU_FAULT_UNRECOV_PASID_VALID; in arm_smmu_handle_evt()
1505 flt->event.pasid = FIELD_GET(EVTQ_0_SSID, evt[0]); in arm_smmu_handle_evt()
1509 mutex_lock(&smmu->streams_mutex); in arm_smmu_handle_evt()
1512 ret = -EINVAL; in arm_smmu_handle_evt()
1516 ret = iommu_report_device_fault(master->dev, &fault_evt); in arm_smmu_handle_evt()
1517 if (ret && flt->type == IOMMU_FAULT_PAGE_REQ) { in arm_smmu_handle_evt()
1520 .pasid = flt->prm.pasid, in arm_smmu_handle_evt()
1521 .grpid = flt->prm.grpid, in arm_smmu_handle_evt()
1524 arm_smmu_page_response(master->dev, &fault_evt, &resp); in arm_smmu_handle_evt()
1528 mutex_unlock(&smmu->streams_mutex); in arm_smmu_handle_evt()
1536 struct arm_smmu_queue *q = &smmu->evtq.q; in arm_smmu_evtq_thread()
1537 struct arm_smmu_ll_queue *llq = &q->llq; in arm_smmu_evtq_thread()
1550 dev_info(smmu->dev, "event 0x%02x received:\n", id); in arm_smmu_evtq_thread()
1552 dev_info(smmu->dev, "\t0x%016llx\n", in arm_smmu_evtq_thread()
1561 if (queue_sync_prod_in(q) == -EOVERFLOW) in arm_smmu_evtq_thread()
1562 dev_err(smmu->dev, "EVTQ overflow detected -- events lost\n"); in arm_smmu_evtq_thread()
1566 llq->cons = Q_OVF(llq->prod) | Q_WRP(llq, llq->cons) | in arm_smmu_evtq_thread()
1567 Q_IDX(llq, llq->cons); in arm_smmu_evtq_thread()
1583 dev_info(smmu->dev, "unexpected PRI request received:\n"); in arm_smmu_handle_ppr()
1584 dev_info(smmu->dev, in arm_smmu_handle_ppr()
1594 struct arm_smmu_cmdq_ent cmd = { in arm_smmu_handle_ppr() local
1605 arm_smmu_cmdq_issue_cmd(smmu, &cmd); in arm_smmu_handle_ppr()
1612 struct arm_smmu_queue *q = &smmu->priq.q; in arm_smmu_priq_thread()
1613 struct arm_smmu_ll_queue *llq = &q->llq; in arm_smmu_priq_thread()
1620 if (queue_sync_prod_in(q) == -EOVERFLOW) in arm_smmu_priq_thread()
1621 dev_err(smmu->dev, "PRIQ overflow detected -- requests lost\n"); in arm_smmu_priq_thread()
1625 llq->cons = Q_OVF(llq->prod) | Q_WRP(llq, llq->cons) | in arm_smmu_priq_thread()
1626 Q_IDX(llq, llq->cons); in arm_smmu_priq_thread()
1638 gerror = readl_relaxed(smmu->base + ARM_SMMU_GERROR); in arm_smmu_gerror_handler()
1639 gerrorn = readl_relaxed(smmu->base + ARM_SMMU_GERRORN); in arm_smmu_gerror_handler()
1645 dev_warn(smmu->dev, in arm_smmu_gerror_handler()
1650 dev_err(smmu->dev, "device has entered Service Failure Mode!\n"); in arm_smmu_gerror_handler()
1655 dev_warn(smmu->dev, "GERROR MSI write aborted\n"); in arm_smmu_gerror_handler()
1658 dev_warn(smmu->dev, "PRIQ MSI write aborted\n"); in arm_smmu_gerror_handler()
1661 dev_warn(smmu->dev, "EVTQ MSI write aborted\n"); in arm_smmu_gerror_handler()
1664 dev_warn(smmu->dev, "CMDQ MSI write aborted\n"); in arm_smmu_gerror_handler()
1667 dev_err(smmu->dev, "PRIQ write aborted -- events may have been lost\n"); in arm_smmu_gerror_handler()
1670 dev_err(smmu->dev, "EVTQ write aborted -- events may have been lost\n"); in arm_smmu_gerror_handler()
1675 writel(gerror, smmu->base + ARM_SMMU_GERRORN); in arm_smmu_gerror_handler()
1684 if (smmu->features & ARM_SMMU_FEAT_PRI) in arm_smmu_combined_irq_thread()
1698 struct arm_smmu_cmdq_ent *cmd) in arm_smmu_atc_inv_to_cmd() argument
1702 /* ATC invalidates are always on 4096-bytes pages */ in arm_smmu_atc_inv_to_cmd()
1714 * When using STRTAB_STE_1_S1DSS_SSID0 (reserving CD 0 for non-PASID in arm_smmu_atc_inv_to_cmd()
1717 * This has the unpleasant side-effect of invalidating all PASID-tagged in arm_smmu_atc_inv_to_cmd()
1720 *cmd = (struct arm_smmu_cmdq_ent) { in arm_smmu_atc_inv_to_cmd()
1727 cmd->atc.size = ATC_INV_SIZE_ALL; in arm_smmu_atc_inv_to_cmd()
1732 page_end = (iova + size - 1) >> inval_grain_shift; in arm_smmu_atc_inv_to_cmd()
1737 * thus have to choose between grossly over-invalidating the region, or in arm_smmu_atc_inv_to_cmd()
1755 span_mask = (1ULL << log2_span) - 1; in arm_smmu_atc_inv_to_cmd()
1759 cmd->atc.addr = page_start << inval_grain_shift; in arm_smmu_atc_inv_to_cmd()
1760 cmd->atc.size = log2_span; in arm_smmu_atc_inv_to_cmd()
1766 struct arm_smmu_cmdq_ent cmd; in arm_smmu_atc_inv_master() local
1769 arm_smmu_atc_inv_to_cmd(0, 0, 0, &cmd); in arm_smmu_atc_inv_master()
1771 for (i = 0; i < master->num_streams; i++) { in arm_smmu_atc_inv_master()
1772 cmd.atc.sid = master->streams[i].id; in arm_smmu_atc_inv_master()
1773 arm_smmu_cmdq_batch_add(master->smmu, &cmds, &cmd); in arm_smmu_atc_inv_master()
1776 return arm_smmu_cmdq_batch_submit(master->smmu, &cmds); in arm_smmu_atc_inv_master()
1784 struct arm_smmu_cmdq_ent cmd; in arm_smmu_atc_inv_domain() local
1788 if (!(smmu_domain->smmu->features & ARM_SMMU_FEAT_ATS)) in arm_smmu_atc_inv_domain()
1805 if (!atomic_read(&smmu_domain->nr_ats_masters)) in arm_smmu_atc_inv_domain()
1808 arm_smmu_atc_inv_to_cmd(ssid, iova, size, &cmd); in arm_smmu_atc_inv_domain()
1812 spin_lock_irqsave(&smmu_domain->devices_lock, flags); in arm_smmu_atc_inv_domain()
1813 list_for_each_entry(master, &smmu_domain->devices, domain_head) { in arm_smmu_atc_inv_domain()
1814 if (!master->ats_enabled) in arm_smmu_atc_inv_domain()
1817 for (i = 0; i < master->num_streams; i++) { in arm_smmu_atc_inv_domain()
1818 cmd.atc.sid = master->streams[i].id; in arm_smmu_atc_inv_domain()
1819 arm_smmu_cmdq_batch_add(smmu_domain->smmu, &cmds, &cmd); in arm_smmu_atc_inv_domain()
1822 spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); in arm_smmu_atc_inv_domain()
1824 return arm_smmu_cmdq_batch_submit(smmu_domain->smmu, &cmds); in arm_smmu_atc_inv_domain()
1831 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_tlb_inv_context()
1832 struct arm_smmu_cmdq_ent cmd; in arm_smmu_tlb_inv_context() local
1835 * NOTE: when io-pgtable is in non-strict mode, we may get here with in arm_smmu_tlb_inv_context()
1837 * to the SMMU. We are relying on the dma_wmb() implicit during cmd in arm_smmu_tlb_inv_context()
1841 if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) { in arm_smmu_tlb_inv_context()
1842 arm_smmu_tlb_inv_asid(smmu, smmu_domain->s1_cfg.cd.asid); in arm_smmu_tlb_inv_context()
1844 cmd.opcode = CMDQ_OP_TLBI_S12_VMALL; in arm_smmu_tlb_inv_context()
1845 cmd.tlbi.vmid = smmu_domain->s2_cfg.vmid; in arm_smmu_tlb_inv_context()
1846 arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); in arm_smmu_tlb_inv_context()
1851 static void __arm_smmu_tlb_inv_range(struct arm_smmu_cmdq_ent *cmd, in __arm_smmu_tlb_inv_range() argument
1856 struct arm_smmu_device *smmu = smmu_domain->smmu; in __arm_smmu_tlb_inv_range()
1864 if (smmu->features & ARM_SMMU_FEAT_RANGE_INV) { in __arm_smmu_tlb_inv_range()
1866 tg = __ffs(smmu_domain->domain.pgsize_bitmap); in __arm_smmu_tlb_inv_range()
1869 cmd->tlbi.tg = (tg - 10) / 2; in __arm_smmu_tlb_inv_range()
1872 cmd->tlbi.ttl = 4 - ((ilog2(granule) - 3) / (tg - 3)); in __arm_smmu_tlb_inv_range()
1880 if (smmu->features & ARM_SMMU_FEAT_RANGE_INV) { in __arm_smmu_tlb_inv_range()
1892 cmd->tlbi.scale = scale; in __arm_smmu_tlb_inv_range()
1896 cmd->tlbi.num = num - 1; in __arm_smmu_tlb_inv_range()
1902 num_pages -= num << scale; in __arm_smmu_tlb_inv_range()
1905 cmd->tlbi.addr = iova; in __arm_smmu_tlb_inv_range()
1906 arm_smmu_cmdq_batch_add(smmu, &cmds, cmd); in __arm_smmu_tlb_inv_range()
1916 struct arm_smmu_cmdq_ent cmd = { in arm_smmu_tlb_inv_range_domain() local
1922 if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) { in arm_smmu_tlb_inv_range_domain()
1923 cmd.opcode = smmu_domain->smmu->features & ARM_SMMU_FEAT_E2H ? in arm_smmu_tlb_inv_range_domain()
1925 cmd.tlbi.asid = smmu_domain->s1_cfg.cd.asid; in arm_smmu_tlb_inv_range_domain()
1927 cmd.opcode = CMDQ_OP_TLBI_S2_IPA; in arm_smmu_tlb_inv_range_domain()
1928 cmd.tlbi.vmid = smmu_domain->s2_cfg.vmid; in arm_smmu_tlb_inv_range_domain()
1930 __arm_smmu_tlb_inv_range(&cmd, iova, size, granule, smmu_domain); in arm_smmu_tlb_inv_range_domain()
1933 * Unfortunately, this can't be leaf-only since we may have in arm_smmu_tlb_inv_range_domain()
1943 struct arm_smmu_cmdq_ent cmd = { in arm_smmu_tlb_inv_range_asid() local
1944 .opcode = smmu_domain->smmu->features & ARM_SMMU_FEAT_E2H ? in arm_smmu_tlb_inv_range_asid()
1952 __arm_smmu_tlb_inv_range(&cmd, iova, size, granule, smmu_domain); in arm_smmu_tlb_inv_range_asid()
1960 struct iommu_domain *domain = &smmu_domain->domain; in arm_smmu_tlb_inv_page_nosync()
2009 mutex_init(&smmu_domain->init_mutex); in arm_smmu_domain_alloc()
2010 INIT_LIST_HEAD(&smmu_domain->devices); in arm_smmu_domain_alloc()
2011 spin_lock_init(&smmu_domain->devices_lock); in arm_smmu_domain_alloc()
2012 INIT_LIST_HEAD(&smmu_domain->mmu_notifiers); in arm_smmu_domain_alloc()
2014 return &smmu_domain->domain; in arm_smmu_domain_alloc()
2024 return -ENOSPC; in arm_smmu_bitmap_alloc()
2038 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_domain_free()
2040 free_io_pgtable_ops(smmu_domain->pgtbl_ops); in arm_smmu_domain_free()
2043 if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) { in arm_smmu_domain_free()
2044 struct arm_smmu_s1_cfg *cfg = &smmu_domain->s1_cfg; in arm_smmu_domain_free()
2048 if (cfg->cdcfg.cdtab) in arm_smmu_domain_free()
2050 arm_smmu_free_asid(&cfg->cd); in arm_smmu_domain_free()
2053 struct arm_smmu_s2_cfg *cfg = &smmu_domain->s2_cfg; in arm_smmu_domain_free()
2054 if (cfg->vmid) in arm_smmu_domain_free()
2055 arm_smmu_bitmap_free(smmu->vmid_map, cfg->vmid); in arm_smmu_domain_free()
2067 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_domain_finalise_s1()
2068 struct arm_smmu_s1_cfg *cfg = &smmu_domain->s1_cfg; in arm_smmu_domain_finalise_s1()
2069 typeof(&pgtbl_cfg->arm_lpae_s1_cfg.tcr) tcr = &pgtbl_cfg->arm_lpae_s1_cfg.tcr; in arm_smmu_domain_finalise_s1()
2071 refcount_set(&cfg->cd.refs, 1); in arm_smmu_domain_finalise_s1()
2075 ret = xa_alloc(&arm_smmu_asid_xa, &asid, &cfg->cd, in arm_smmu_domain_finalise_s1()
2076 XA_LIMIT(1, (1 << smmu->asid_bits) - 1), GFP_KERNEL); in arm_smmu_domain_finalise_s1()
2080 cfg->s1cdmax = master->ssid_bits; in arm_smmu_domain_finalise_s1()
2082 smmu_domain->stall_enabled = master->stall_enabled; in arm_smmu_domain_finalise_s1()
2088 cfg->cd.asid = (u16)asid; in arm_smmu_domain_finalise_s1()
2089 cfg->cd.ttbr = pgtbl_cfg->arm_lpae_s1_cfg.ttbr; in arm_smmu_domain_finalise_s1()
2090 cfg->cd.tcr = FIELD_PREP(CTXDESC_CD_0_TCR_T0SZ, tcr->tsz) | in arm_smmu_domain_finalise_s1()
2091 FIELD_PREP(CTXDESC_CD_0_TCR_TG0, tcr->tg) | in arm_smmu_domain_finalise_s1()
2092 FIELD_PREP(CTXDESC_CD_0_TCR_IRGN0, tcr->irgn) | in arm_smmu_domain_finalise_s1()
2093 FIELD_PREP(CTXDESC_CD_0_TCR_ORGN0, tcr->orgn) | in arm_smmu_domain_finalise_s1()
2094 FIELD_PREP(CTXDESC_CD_0_TCR_SH0, tcr->sh) | in arm_smmu_domain_finalise_s1()
2095 FIELD_PREP(CTXDESC_CD_0_TCR_IPS, tcr->ips) | in arm_smmu_domain_finalise_s1()
2097 cfg->cd.mair = pgtbl_cfg->arm_lpae_s1_cfg.mair; in arm_smmu_domain_finalise_s1()
2104 ret = arm_smmu_write_ctx_desc(smmu_domain, 0, &cfg->cd); in arm_smmu_domain_finalise_s1()
2114 arm_smmu_free_asid(&cfg->cd); in arm_smmu_domain_finalise_s1()
2125 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_domain_finalise_s2()
2126 struct arm_smmu_s2_cfg *cfg = &smmu_domain->s2_cfg; in arm_smmu_domain_finalise_s2()
2127 typeof(&pgtbl_cfg->arm_lpae_s2_cfg.vtcr) vtcr; in arm_smmu_domain_finalise_s2()
2129 vmid = arm_smmu_bitmap_alloc(smmu->vmid_map, smmu->vmid_bits); in arm_smmu_domain_finalise_s2()
2133 vtcr = &pgtbl_cfg->arm_lpae_s2_cfg.vtcr; in arm_smmu_domain_finalise_s2()
2134 cfg->vmid = (u16)vmid; in arm_smmu_domain_finalise_s2()
2135 cfg->vttbr = pgtbl_cfg->arm_lpae_s2_cfg.vttbr; in arm_smmu_domain_finalise_s2()
2136 cfg->vtcr = FIELD_PREP(STRTAB_STE_2_VTCR_S2T0SZ, vtcr->tsz) | in arm_smmu_domain_finalise_s2()
2137 FIELD_PREP(STRTAB_STE_2_VTCR_S2SL0, vtcr->sl) | in arm_smmu_domain_finalise_s2()
2138 FIELD_PREP(STRTAB_STE_2_VTCR_S2IR0, vtcr->irgn) | in arm_smmu_domain_finalise_s2()
2139 FIELD_PREP(STRTAB_STE_2_VTCR_S2OR0, vtcr->orgn) | in arm_smmu_domain_finalise_s2()
2140 FIELD_PREP(STRTAB_STE_2_VTCR_S2SH0, vtcr->sh) | in arm_smmu_domain_finalise_s2()
2141 FIELD_PREP(STRTAB_STE_2_VTCR_S2TG, vtcr->tg) | in arm_smmu_domain_finalise_s2()
2142 FIELD_PREP(STRTAB_STE_2_VTCR_S2PS, vtcr->ps); in arm_smmu_domain_finalise_s2()
2158 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_domain_finalise()
2160 if (domain->type == IOMMU_DOMAIN_IDENTITY) { in arm_smmu_domain_finalise()
2161 smmu_domain->stage = ARM_SMMU_DOMAIN_BYPASS; in arm_smmu_domain_finalise()
2166 if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S1)) in arm_smmu_domain_finalise()
2167 smmu_domain->stage = ARM_SMMU_DOMAIN_S2; in arm_smmu_domain_finalise()
2168 if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S2)) in arm_smmu_domain_finalise()
2169 smmu_domain->stage = ARM_SMMU_DOMAIN_S1; in arm_smmu_domain_finalise()
2171 switch (smmu_domain->stage) { in arm_smmu_domain_finalise()
2173 ias = (smmu->features & ARM_SMMU_FEAT_VAX) ? 52 : 48; in arm_smmu_domain_finalise()
2175 oas = smmu->ias; in arm_smmu_domain_finalise()
2181 ias = smmu->ias; in arm_smmu_domain_finalise()
2182 oas = smmu->oas; in arm_smmu_domain_finalise()
2187 return -EINVAL; in arm_smmu_domain_finalise()
2191 .pgsize_bitmap = smmu->pgsize_bitmap, in arm_smmu_domain_finalise()
2194 .coherent_walk = smmu->features & ARM_SMMU_FEAT_COHERENCY, in arm_smmu_domain_finalise()
2196 .iommu_dev = smmu->dev, in arm_smmu_domain_finalise()
2201 return -ENOMEM; in arm_smmu_domain_finalise()
2203 domain->pgsize_bitmap = pgtbl_cfg.pgsize_bitmap; in arm_smmu_domain_finalise()
2204 domain->geometry.aperture_end = (1UL << pgtbl_cfg.ias) - 1; in arm_smmu_domain_finalise()
2205 domain->geometry.force_aperture = true; in arm_smmu_domain_finalise()
2213 smmu_domain->pgtbl_ops = pgtbl_ops; in arm_smmu_domain_finalise()
2220 struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; in arm_smmu_get_step_for_sid()
2222 if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) { in arm_smmu_get_step_for_sid()
2226 /* Two-level walk */ in arm_smmu_get_step_for_sid()
2228 l1_desc = &cfg->l1_desc[idx]; in arm_smmu_get_step_for_sid()
2229 idx = (sid & ((1 << STRTAB_SPLIT) - 1)) * STRTAB_STE_DWORDS; in arm_smmu_get_step_for_sid()
2230 step = &l1_desc->l2ptr[idx]; in arm_smmu_get_step_for_sid()
2233 step = &cfg->strtab[sid * STRTAB_STE_DWORDS]; in arm_smmu_get_step_for_sid()
2242 struct arm_smmu_device *smmu = master->smmu; in arm_smmu_install_ste_for_dev()
2244 for (i = 0; i < master->num_streams; ++i) { in arm_smmu_install_ste_for_dev()
2245 u32 sid = master->streams[i].id; in arm_smmu_install_ste_for_dev()
2250 if (master->streams[j].id == sid) in arm_smmu_install_ste_for_dev()
2261 struct device *dev = master->dev; in arm_smmu_ats_supported()
2262 struct arm_smmu_device *smmu = master->smmu; in arm_smmu_ats_supported()
2265 if (!(smmu->features & ARM_SMMU_FEAT_ATS)) in arm_smmu_ats_supported()
2268 if (!(fwspec->flags & IOMMU_FWSPEC_PCI_RC_ATS)) in arm_smmu_ats_supported()
2278 struct arm_smmu_device *smmu = master->smmu; in arm_smmu_enable_ats()
2279 struct arm_smmu_domain *smmu_domain = master->domain; in arm_smmu_enable_ats()
2282 if (!master->ats_enabled) in arm_smmu_enable_ats()
2286 stu = __ffs(smmu->pgsize_bitmap); in arm_smmu_enable_ats()
2287 pdev = to_pci_dev(master->dev); in arm_smmu_enable_ats()
2289 atomic_inc(&smmu_domain->nr_ats_masters); in arm_smmu_enable_ats()
2292 dev_err(master->dev, "Failed to enable ATS (STU %zu)\n", stu); in arm_smmu_enable_ats()
2297 struct arm_smmu_domain *smmu_domain = master->domain; in arm_smmu_disable_ats()
2299 if (!master->ats_enabled) in arm_smmu_disable_ats()
2302 pci_disable_ats(to_pci_dev(master->dev)); in arm_smmu_disable_ats()
2309 atomic_dec(&smmu_domain->nr_ats_masters); in arm_smmu_disable_ats()
2319 if (!dev_is_pci(master->dev)) in arm_smmu_enable_pasid()
2320 return -ENODEV; in arm_smmu_enable_pasid()
2322 pdev = to_pci_dev(master->dev); in arm_smmu_enable_pasid()
2334 dev_err(&pdev->dev, "Failed to enable PASID\n"); in arm_smmu_enable_pasid()
2338 master->ssid_bits = min_t(u8, ilog2(num_pasids), in arm_smmu_enable_pasid()
2339 master->smmu->ssid_bits); in arm_smmu_enable_pasid()
2347 if (!dev_is_pci(master->dev)) in arm_smmu_disable_pasid()
2350 pdev = to_pci_dev(master->dev); in arm_smmu_disable_pasid()
2352 if (!pdev->pasid_enabled) in arm_smmu_disable_pasid()
2355 master->ssid_bits = 0; in arm_smmu_disable_pasid()
2362 struct arm_smmu_domain *smmu_domain = master->domain; in arm_smmu_detach_dev()
2369 spin_lock_irqsave(&smmu_domain->devices_lock, flags); in arm_smmu_detach_dev()
2370 list_del(&master->domain_head); in arm_smmu_detach_dev()
2371 spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); in arm_smmu_detach_dev()
2373 master->domain = NULL; in arm_smmu_detach_dev()
2374 master->ats_enabled = false; in arm_smmu_detach_dev()
2388 return -ENOENT; in arm_smmu_attach_dev()
2391 smmu = master->smmu; in arm_smmu_attach_dev()
2399 dev_err(dev, "cannot attach - SVA enabled\n"); in arm_smmu_attach_dev()
2400 return -EBUSY; in arm_smmu_attach_dev()
2405 mutex_lock(&smmu_domain->init_mutex); in arm_smmu_attach_dev()
2407 if (!smmu_domain->smmu) { in arm_smmu_attach_dev()
2408 smmu_domain->smmu = smmu; in arm_smmu_attach_dev()
2411 smmu_domain->smmu = NULL; in arm_smmu_attach_dev()
2414 } else if (smmu_domain->smmu != smmu) { in arm_smmu_attach_dev()
2417 dev_name(smmu_domain->smmu->dev), in arm_smmu_attach_dev()
2418 dev_name(smmu->dev)); in arm_smmu_attach_dev()
2419 ret = -ENXIO; in arm_smmu_attach_dev()
2421 } else if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1 && in arm_smmu_attach_dev()
2422 master->ssid_bits != smmu_domain->s1_cfg.s1cdmax) { in arm_smmu_attach_dev()
2425 smmu_domain->s1_cfg.s1cdmax, master->ssid_bits); in arm_smmu_attach_dev()
2426 ret = -EINVAL; in arm_smmu_attach_dev()
2428 } else if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1 && in arm_smmu_attach_dev()
2429 smmu_domain->stall_enabled != master->stall_enabled) { in arm_smmu_attach_dev()
2430 dev_err(dev, "cannot attach to stall-%s domain\n", in arm_smmu_attach_dev()
2431 smmu_domain->stall_enabled ? "enabled" : "disabled"); in arm_smmu_attach_dev()
2432 ret = -EINVAL; in arm_smmu_attach_dev()
2436 master->domain = smmu_domain; in arm_smmu_attach_dev()
2438 if (smmu_domain->stage != ARM_SMMU_DOMAIN_BYPASS) in arm_smmu_attach_dev()
2439 master->ats_enabled = arm_smmu_ats_supported(master); in arm_smmu_attach_dev()
2443 spin_lock_irqsave(&smmu_domain->devices_lock, flags); in arm_smmu_attach_dev()
2444 list_add(&master->domain_head, &smmu_domain->devices); in arm_smmu_attach_dev()
2445 spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); in arm_smmu_attach_dev()
2450 mutex_unlock(&smmu_domain->init_mutex); in arm_smmu_attach_dev()
2458 struct io_pgtable_ops *ops = to_smmu_domain(domain)->pgtbl_ops; in arm_smmu_map_pages()
2461 return -ENODEV; in arm_smmu_map_pages()
2463 return ops->map_pages(ops, iova, paddr, pgsize, pgcount, prot, gfp, mapped); in arm_smmu_map_pages()
2471 struct io_pgtable_ops *ops = smmu_domain->pgtbl_ops; in arm_smmu_unmap_pages()
2476 return ops->unmap_pages(ops, iova, pgsize, pgcount, gather); in arm_smmu_unmap_pages()
2483 if (smmu_domain->smmu) in arm_smmu_flush_iotlb_all()
2492 if (!gather->pgsize) in arm_smmu_iotlb_sync()
2495 arm_smmu_tlb_inv_range_domain(gather->start, in arm_smmu_iotlb_sync()
2496 gather->end - gather->start + 1, in arm_smmu_iotlb_sync()
2497 gather->pgsize, true, smmu_domain); in arm_smmu_iotlb_sync()
2503 struct io_pgtable_ops *ops = to_smmu_domain(domain)->pgtbl_ops; in arm_smmu_iova_to_phys()
2508 return ops->iova_to_phys(ops, iova); in arm_smmu_iova_to_phys()
2524 unsigned long limit = smmu->strtab_cfg.num_l1_ents; in arm_smmu_sid_in_range()
2526 if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) in arm_smmu_sid_in_range()
2539 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(master->dev); in arm_smmu_insert_master()
2541 master->streams = kcalloc(fwspec->num_ids, sizeof(*master->streams), in arm_smmu_insert_master()
2543 if (!master->streams) in arm_smmu_insert_master()
2544 return -ENOMEM; in arm_smmu_insert_master()
2545 master->num_streams = fwspec->num_ids; in arm_smmu_insert_master()
2547 mutex_lock(&smmu->streams_mutex); in arm_smmu_insert_master()
2548 for (i = 0; i < fwspec->num_ids; i++) { in arm_smmu_insert_master()
2549 u32 sid = fwspec->ids[i]; in arm_smmu_insert_master()
2551 new_stream = &master->streams[i]; in arm_smmu_insert_master()
2552 new_stream->id = sid; in arm_smmu_insert_master()
2553 new_stream->master = master; in arm_smmu_insert_master()
2559 ret = -ERANGE; in arm_smmu_insert_master()
2564 if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) { in arm_smmu_insert_master()
2571 new_node = &(smmu->streams.rb_node); in arm_smmu_insert_master()
2576 if (cur_stream->id > new_stream->id) { in arm_smmu_insert_master()
2577 new_node = &((*new_node)->rb_left); in arm_smmu_insert_master()
2578 } else if (cur_stream->id < new_stream->id) { in arm_smmu_insert_master()
2579 new_node = &((*new_node)->rb_right); in arm_smmu_insert_master()
2581 dev_warn(master->dev, in arm_smmu_insert_master()
2583 cur_stream->id); in arm_smmu_insert_master()
2584 ret = -EINVAL; in arm_smmu_insert_master()
2591 rb_link_node(&new_stream->node, parent_node, new_node); in arm_smmu_insert_master()
2592 rb_insert_color(&new_stream->node, &smmu->streams); in arm_smmu_insert_master()
2596 for (i--; i >= 0; i--) in arm_smmu_insert_master()
2597 rb_erase(&master->streams[i].node, &smmu->streams); in arm_smmu_insert_master()
2598 kfree(master->streams); in arm_smmu_insert_master()
2600 mutex_unlock(&smmu->streams_mutex); in arm_smmu_insert_master()
2608 struct arm_smmu_device *smmu = master->smmu; in arm_smmu_remove_master()
2609 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(master->dev); in arm_smmu_remove_master()
2611 if (!smmu || !master->streams) in arm_smmu_remove_master()
2614 mutex_lock(&smmu->streams_mutex); in arm_smmu_remove_master()
2615 for (i = 0; i < fwspec->num_ids; i++) in arm_smmu_remove_master()
2616 rb_erase(&master->streams[i].node, &smmu->streams); in arm_smmu_remove_master()
2617 mutex_unlock(&smmu->streams_mutex); in arm_smmu_remove_master()
2619 kfree(master->streams); in arm_smmu_remove_master()
2631 if (!fwspec || fwspec->ops != &arm_smmu_ops) in arm_smmu_probe_device()
2632 return ERR_PTR(-ENODEV); in arm_smmu_probe_device()
2635 return ERR_PTR(-EBUSY); in arm_smmu_probe_device()
2637 smmu = arm_smmu_get_by_fwnode(fwspec->iommu_fwnode); in arm_smmu_probe_device()
2639 return ERR_PTR(-ENODEV); in arm_smmu_probe_device()
2643 return ERR_PTR(-ENOMEM); in arm_smmu_probe_device()
2645 master->dev = dev; in arm_smmu_probe_device()
2646 master->smmu = smmu; in arm_smmu_probe_device()
2647 INIT_LIST_HEAD(&master->bonds); in arm_smmu_probe_device()
2654 device_property_read_u32(dev, "pasid-num-bits", &master->ssid_bits); in arm_smmu_probe_device()
2655 master->ssid_bits = min(smmu->ssid_bits, master->ssid_bits); in arm_smmu_probe_device()
2659 * PCI Express Base 4.0r1.0 - 10.5.1.3 ATS Control Register in arm_smmu_probe_device()
2667 if (!(smmu->features & ARM_SMMU_FEAT_2_LVL_CDTAB)) in arm_smmu_probe_device()
2668 master->ssid_bits = min_t(u8, master->ssid_bits, in arm_smmu_probe_device()
2671 if ((smmu->features & ARM_SMMU_FEAT_STALLS && in arm_smmu_probe_device()
2672 device_property_read_bool(dev, "dma-can-stall")) || in arm_smmu_probe_device()
2673 smmu->features & ARM_SMMU_FEAT_STALL_FORCE) in arm_smmu_probe_device()
2674 master->stall_enabled = true; in arm_smmu_probe_device()
2676 return &smmu->iommu; in arm_smmu_probe_device()
2689 if (!fwspec || fwspec->ops != &arm_smmu_ops) in arm_smmu_release_device()
2694 iopf_queue_remove_device(master->smmu->evtq.iopf, dev); in arm_smmu_release_device()
2708 * aliases, since the necessary ID-to-device lookup becomes rather in arm_smmu_device_group()
2709 * impractical given a potential sparse 32-bit stream ID space. in arm_smmu_device_group()
2724 mutex_lock(&smmu_domain->init_mutex); in arm_smmu_enable_nesting()
2725 if (smmu_domain->smmu) in arm_smmu_enable_nesting()
2726 ret = -EPERM; in arm_smmu_enable_nesting()
2728 smmu_domain->stage = ARM_SMMU_DOMAIN_NESTED; in arm_smmu_enable_nesting()
2729 mutex_unlock(&smmu_domain->init_mutex); in arm_smmu_enable_nesting()
2736 return iommu_fwspec_add_ids(dev, args->args, 1); in arm_smmu_of_xlate()
2750 list_add_tail(®ion->list, head); in arm_smmu_get_resv_regions()
2783 return master->iopf_enabled; in arm_smmu_dev_feature_enabled()
2797 return -ENODEV; in arm_smmu_dev_enable_feature()
2800 return -EBUSY; in arm_smmu_dev_enable_feature()
2804 master->iopf_enabled = true; in arm_smmu_dev_enable_feature()
2809 return -EINVAL; in arm_smmu_dev_enable_feature()
2819 return -EINVAL; in arm_smmu_dev_disable_feature()
2823 if (master->sva_enabled) in arm_smmu_dev_disable_feature()
2824 return -EBUSY; in arm_smmu_dev_disable_feature()
2825 master->iopf_enabled = false; in arm_smmu_dev_disable_feature()
2830 return -EINVAL; in arm_smmu_dev_disable_feature()
2859 .pgsize_bitmap = -1UL, /* Restricted during device attach */
2874 qsz = ((1 << q->llq.max_n_shift) * dwords) << 3; in arm_smmu_init_one_queue()
2875 q->base = dmam_alloc_coherent(smmu->dev, qsz, &q->base_dma, in arm_smmu_init_one_queue()
2877 if (q->base || qsz < PAGE_SIZE) in arm_smmu_init_one_queue()
2880 q->llq.max_n_shift--; in arm_smmu_init_one_queue()
2883 if (!q->base) { in arm_smmu_init_one_queue()
2884 dev_err(smmu->dev, in arm_smmu_init_one_queue()
2887 return -ENOMEM; in arm_smmu_init_one_queue()
2890 if (!WARN_ON(q->base_dma & (qsz - 1))) { in arm_smmu_init_one_queue()
2891 dev_info(smmu->dev, "allocated %u entries for %s\n", in arm_smmu_init_one_queue()
2892 1 << q->llq.max_n_shift, name); in arm_smmu_init_one_queue()
2895 q->prod_reg = page + prod_off; in arm_smmu_init_one_queue()
2896 q->cons_reg = page + cons_off; in arm_smmu_init_one_queue()
2897 q->ent_dwords = dwords; in arm_smmu_init_one_queue()
2899 q->q_base = Q_BASE_RWA; in arm_smmu_init_one_queue()
2900 q->q_base |= q->base_dma & Q_BASE_ADDR_MASK; in arm_smmu_init_one_queue()
2901 q->q_base |= FIELD_PREP(Q_BASE_LOG2SIZE, q->llq.max_n_shift); in arm_smmu_init_one_queue()
2903 q->llq.prod = q->llq.cons = 0; in arm_smmu_init_one_queue()
2916 struct arm_smmu_cmdq *cmdq = &smmu->cmdq; in arm_smmu_cmdq_init()
2917 unsigned int nents = 1 << cmdq->q.llq.max_n_shift; in arm_smmu_cmdq_init()
2920 atomic_set(&cmdq->owner_prod, 0); in arm_smmu_cmdq_init()
2921 atomic_set(&cmdq->lock, 0); in arm_smmu_cmdq_init()
2925 dev_err(smmu->dev, "failed to allocate cmdq bitmap\n"); in arm_smmu_cmdq_init()
2926 ret = -ENOMEM; in arm_smmu_cmdq_init()
2928 cmdq->valid_map = bitmap; in arm_smmu_cmdq_init()
2929 devm_add_action(smmu->dev, arm_smmu_cmdq_free_bitmap, bitmap); in arm_smmu_cmdq_init()
2940 ret = arm_smmu_init_one_queue(smmu, &smmu->cmdq.q, smmu->base, in arm_smmu_init_queues()
2951 ret = arm_smmu_init_one_queue(smmu, &smmu->evtq.q, smmu->page1, in arm_smmu_init_queues()
2957 if ((smmu->features & ARM_SMMU_FEAT_SVA) && in arm_smmu_init_queues()
2958 (smmu->features & ARM_SMMU_FEAT_STALLS)) { in arm_smmu_init_queues()
2959 smmu->evtq.iopf = iopf_queue_alloc(dev_name(smmu->dev)); in arm_smmu_init_queues()
2960 if (!smmu->evtq.iopf) in arm_smmu_init_queues()
2961 return -ENOMEM; in arm_smmu_init_queues()
2965 if (!(smmu->features & ARM_SMMU_FEAT_PRI)) in arm_smmu_init_queues()
2968 return arm_smmu_init_one_queue(smmu, &smmu->priq.q, smmu->page1, in arm_smmu_init_queues()
2976 struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; in arm_smmu_init_l1_strtab()
2977 size_t size = sizeof(*cfg->l1_desc) * cfg->num_l1_ents; in arm_smmu_init_l1_strtab()
2978 void *strtab = smmu->strtab_cfg.strtab; in arm_smmu_init_l1_strtab()
2980 cfg->l1_desc = devm_kzalloc(smmu->dev, size, GFP_KERNEL); in arm_smmu_init_l1_strtab()
2981 if (!cfg->l1_desc) in arm_smmu_init_l1_strtab()
2982 return -ENOMEM; in arm_smmu_init_l1_strtab()
2984 for (i = 0; i < cfg->num_l1_ents; ++i) { in arm_smmu_init_l1_strtab()
2985 arm_smmu_write_strtab_l1_desc(strtab, &cfg->l1_desc[i]); in arm_smmu_init_l1_strtab()
2997 struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; in arm_smmu_init_strtab_2lvl()
3000 size = STRTAB_L1_SZ_SHIFT - (ilog2(STRTAB_L1_DESC_DWORDS) + 3); in arm_smmu_init_strtab_2lvl()
3001 size = min(size, smmu->sid_bits - STRTAB_SPLIT); in arm_smmu_init_strtab_2lvl()
3002 cfg->num_l1_ents = 1 << size; in arm_smmu_init_strtab_2lvl()
3005 if (size < smmu->sid_bits) in arm_smmu_init_strtab_2lvl()
3006 dev_warn(smmu->dev, in arm_smmu_init_strtab_2lvl()
3007 "2-level strtab only covers %u/%u bits of SID\n", in arm_smmu_init_strtab_2lvl()
3008 size, smmu->sid_bits); in arm_smmu_init_strtab_2lvl()
3010 l1size = cfg->num_l1_ents * (STRTAB_L1_DESC_DWORDS << 3); in arm_smmu_init_strtab_2lvl()
3011 strtab = dmam_alloc_coherent(smmu->dev, l1size, &cfg->strtab_dma, in arm_smmu_init_strtab_2lvl()
3014 dev_err(smmu->dev, in arm_smmu_init_strtab_2lvl()
3017 return -ENOMEM; in arm_smmu_init_strtab_2lvl()
3019 cfg->strtab = strtab; in arm_smmu_init_strtab_2lvl()
3025 cfg->strtab_base_cfg = reg; in arm_smmu_init_strtab_2lvl()
3035 struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; in arm_smmu_init_strtab_linear()
3037 size = (1 << smmu->sid_bits) * (STRTAB_STE_DWORDS << 3); in arm_smmu_init_strtab_linear()
3038 strtab = dmam_alloc_coherent(smmu->dev, size, &cfg->strtab_dma, in arm_smmu_init_strtab_linear()
3041 dev_err(smmu->dev, in arm_smmu_init_strtab_linear()
3044 return -ENOMEM; in arm_smmu_init_strtab_linear()
3046 cfg->strtab = strtab; in arm_smmu_init_strtab_linear()
3047 cfg->num_l1_ents = 1 << smmu->sid_bits; in arm_smmu_init_strtab_linear()
3051 reg |= FIELD_PREP(STRTAB_BASE_CFG_LOG2SIZE, smmu->sid_bits); in arm_smmu_init_strtab_linear()
3052 cfg->strtab_base_cfg = reg; in arm_smmu_init_strtab_linear()
3054 arm_smmu_init_bypass_stes(strtab, cfg->num_l1_ents); in arm_smmu_init_strtab_linear()
3063 if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) in arm_smmu_init_strtab()
3072 reg = smmu->strtab_cfg.strtab_dma & STRTAB_BASE_ADDR_MASK; in arm_smmu_init_strtab()
3074 smmu->strtab_cfg.strtab_base = reg; in arm_smmu_init_strtab()
3076 /* Allocate the first VMID for stage-2 bypass STEs */ in arm_smmu_init_strtab()
3077 set_bit(0, smmu->vmid_map); in arm_smmu_init_strtab()
3085 mutex_init(&smmu->streams_mutex); in arm_smmu_init_structures()
3086 smmu->streams = RB_ROOT; in arm_smmu_init_structures()
3100 writel_relaxed(val, smmu->base + reg_off); in arm_smmu_write_reg_sync()
3101 return readl_relaxed_poll_timeout(smmu->base + ack_off, reg, reg == val, in arm_smmu_write_reg_sync()
3109 u32 reg, __iomem *gbpa = smmu->base + ARM_SMMU_GBPA; in arm_smmu_update_gbpa()
3123 dev_err(smmu->dev, "GBPA not responding to update\n"); in arm_smmu_update_gbpa()
3138 phys_addr_t *cfg = arm_smmu_msi_cfg[desc->platform.msi_index]; in arm_smmu_write_msi_msg()
3140 doorbell = (((u64)msg->address_hi) << 32) | msg->address_lo; in arm_smmu_write_msi_msg()
3143 writeq_relaxed(doorbell, smmu->base + cfg[0]); in arm_smmu_write_msi_msg()
3144 writel_relaxed(msg->data, smmu->base + cfg[1]); in arm_smmu_write_msi_msg()
3145 writel_relaxed(ARM_SMMU_MEMATTR_DEVICE_nGnRE, smmu->base + cfg[2]); in arm_smmu_write_msi_msg()
3152 struct device *dev = smmu->dev; in arm_smmu_setup_msis()
3155 writeq_relaxed(0, smmu->base + ARM_SMMU_GERROR_IRQ_CFG0); in arm_smmu_setup_msis()
3156 writeq_relaxed(0, smmu->base + ARM_SMMU_EVTQ_IRQ_CFG0); in arm_smmu_setup_msis()
3158 if (smmu->features & ARM_SMMU_FEAT_PRI) in arm_smmu_setup_msis()
3159 writeq_relaxed(0, smmu->base + ARM_SMMU_PRIQ_IRQ_CFG0); in arm_smmu_setup_msis()
3161 nvec--; in arm_smmu_setup_msis()
3163 if (!(smmu->features & ARM_SMMU_FEAT_MSI)) in arm_smmu_setup_msis()
3166 if (!dev->msi_domain) { in arm_smmu_setup_msis()
3167 dev_info(smmu->dev, "msi_domain absent - falling back to wired irqs\n"); in arm_smmu_setup_msis()
3174 dev_warn(dev, "failed to allocate MSIs - falling back to wired irqs\n"); in arm_smmu_setup_msis()
3179 switch (desc->platform.msi_index) { in arm_smmu_setup_msis()
3181 smmu->evtq.q.irq = desc->irq; in arm_smmu_setup_msis()
3184 smmu->gerr_irq = desc->irq; in arm_smmu_setup_msis()
3187 smmu->priq.q.irq = desc->irq; in arm_smmu_setup_msis()
3205 irq = smmu->evtq.q.irq; in arm_smmu_setup_unique_irqs()
3207 ret = devm_request_threaded_irq(smmu->dev, irq, NULL, in arm_smmu_setup_unique_irqs()
3210 "arm-smmu-v3-evtq", smmu); in arm_smmu_setup_unique_irqs()
3212 dev_warn(smmu->dev, "failed to enable evtq irq\n"); in arm_smmu_setup_unique_irqs()
3214 dev_warn(smmu->dev, "no evtq irq - events will not be reported!\n"); in arm_smmu_setup_unique_irqs()
3217 irq = smmu->gerr_irq; in arm_smmu_setup_unique_irqs()
3219 ret = devm_request_irq(smmu->dev, irq, arm_smmu_gerror_handler, in arm_smmu_setup_unique_irqs()
3220 0, "arm-smmu-v3-gerror", smmu); in arm_smmu_setup_unique_irqs()
3222 dev_warn(smmu->dev, "failed to enable gerror irq\n"); in arm_smmu_setup_unique_irqs()
3224 dev_warn(smmu->dev, "no gerr irq - errors will not be reported!\n"); in arm_smmu_setup_unique_irqs()
3227 if (smmu->features & ARM_SMMU_FEAT_PRI) { in arm_smmu_setup_unique_irqs()
3228 irq = smmu->priq.q.irq; in arm_smmu_setup_unique_irqs()
3230 ret = devm_request_threaded_irq(smmu->dev, irq, NULL, in arm_smmu_setup_unique_irqs()
3233 "arm-smmu-v3-priq", in arm_smmu_setup_unique_irqs()
3236 dev_warn(smmu->dev, in arm_smmu_setup_unique_irqs()
3239 dev_warn(smmu->dev, "no priq irq - PRI will be broken\n"); in arm_smmu_setup_unique_irqs()
3253 dev_err(smmu->dev, "failed to disable irqs\n"); in arm_smmu_setup_irqs()
3257 irq = smmu->combined_irq; in arm_smmu_setup_irqs()
3263 ret = devm_request_threaded_irq(smmu->dev, irq, in arm_smmu_setup_irqs()
3267 "arm-smmu-v3-combined-irq", smmu); in arm_smmu_setup_irqs()
3269 dev_warn(smmu->dev, "failed to enable combined irq\n"); in arm_smmu_setup_irqs()
3273 if (smmu->features & ARM_SMMU_FEAT_PRI) in arm_smmu_setup_irqs()
3280 dev_warn(smmu->dev, "failed to enable irqs\n"); in arm_smmu_setup_irqs()
3291 dev_err(smmu->dev, "failed to clear cr0\n"); in arm_smmu_device_disable()
3300 struct arm_smmu_cmdq_ent cmd; in arm_smmu_device_reset() local
3303 reg = readl_relaxed(smmu->base + ARM_SMMU_CR0); in arm_smmu_device_reset()
3305 dev_warn(smmu->dev, "SMMU currently enabled! Resetting...\n"); in arm_smmu_device_reset()
3321 writel_relaxed(reg, smmu->base + ARM_SMMU_CR1); in arm_smmu_device_reset()
3326 if (smmu->features & ARM_SMMU_FEAT_E2H) in arm_smmu_device_reset()
3329 writel_relaxed(reg, smmu->base + ARM_SMMU_CR2); in arm_smmu_device_reset()
3332 writeq_relaxed(smmu->strtab_cfg.strtab_base, in arm_smmu_device_reset()
3333 smmu->base + ARM_SMMU_STRTAB_BASE); in arm_smmu_device_reset()
3334 writel_relaxed(smmu->strtab_cfg.strtab_base_cfg, in arm_smmu_device_reset()
3335 smmu->base + ARM_SMMU_STRTAB_BASE_CFG); in arm_smmu_device_reset()
3338 writeq_relaxed(smmu->cmdq.q.q_base, smmu->base + ARM_SMMU_CMDQ_BASE); in arm_smmu_device_reset()
3339 writel_relaxed(smmu->cmdq.q.llq.prod, smmu->base + ARM_SMMU_CMDQ_PROD); in arm_smmu_device_reset()
3340 writel_relaxed(smmu->cmdq.q.llq.cons, smmu->base + ARM_SMMU_CMDQ_CONS); in arm_smmu_device_reset()
3346 dev_err(smmu->dev, "failed to enable command queue\n"); in arm_smmu_device_reset()
3351 cmd.opcode = CMDQ_OP_CFGI_ALL; in arm_smmu_device_reset()
3352 arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); in arm_smmu_device_reset()
3355 if (smmu->features & ARM_SMMU_FEAT_HYP) { in arm_smmu_device_reset()
3356 cmd.opcode = CMDQ_OP_TLBI_EL2_ALL; in arm_smmu_device_reset()
3357 arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); in arm_smmu_device_reset()
3360 cmd.opcode = CMDQ_OP_TLBI_NSNH_ALL; in arm_smmu_device_reset()
3361 arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); in arm_smmu_device_reset()
3364 writeq_relaxed(smmu->evtq.q.q_base, smmu->base + ARM_SMMU_EVTQ_BASE); in arm_smmu_device_reset()
3365 writel_relaxed(smmu->evtq.q.llq.prod, smmu->page1 + ARM_SMMU_EVTQ_PROD); in arm_smmu_device_reset()
3366 writel_relaxed(smmu->evtq.q.llq.cons, smmu->page1 + ARM_SMMU_EVTQ_CONS); in arm_smmu_device_reset()
3372 dev_err(smmu->dev, "failed to enable event queue\n"); in arm_smmu_device_reset()
3377 if (smmu->features & ARM_SMMU_FEAT_PRI) { in arm_smmu_device_reset()
3378 writeq_relaxed(smmu->priq.q.q_base, in arm_smmu_device_reset()
3379 smmu->base + ARM_SMMU_PRIQ_BASE); in arm_smmu_device_reset()
3380 writel_relaxed(smmu->priq.q.llq.prod, in arm_smmu_device_reset()
3381 smmu->page1 + ARM_SMMU_PRIQ_PROD); in arm_smmu_device_reset()
3382 writel_relaxed(smmu->priq.q.llq.cons, in arm_smmu_device_reset()
3383 smmu->page1 + ARM_SMMU_PRIQ_CONS); in arm_smmu_device_reset()
3389 dev_err(smmu->dev, "failed to enable PRI queue\n"); in arm_smmu_device_reset()
3394 if (smmu->features & ARM_SMMU_FEAT_ATS) { in arm_smmu_device_reset()
3399 dev_err(smmu->dev, "failed to enable ATS check\n"); in arm_smmu_device_reset()
3406 dev_err(smmu->dev, "failed to setup irqs\n"); in arm_smmu_device_reset()
3424 dev_err(smmu->dev, "failed to enable SMMU interface\n"); in arm_smmu_device_reset()
3434 bool coherent = smmu->features & ARM_SMMU_FEAT_COHERENCY; in arm_smmu_device_hw_probe()
3437 reg = readl_relaxed(smmu->base + ARM_SMMU_IDR0); in arm_smmu_device_hw_probe()
3439 /* 2-level structures */ in arm_smmu_device_hw_probe()
3441 smmu->features |= ARM_SMMU_FEAT_2_LVL_STRTAB; in arm_smmu_device_hw_probe()
3444 smmu->features |= ARM_SMMU_FEAT_2_LVL_CDTAB; in arm_smmu_device_hw_probe()
3453 smmu->features |= ARM_SMMU_FEAT_TT_LE | ARM_SMMU_FEAT_TT_BE; in arm_smmu_device_hw_probe()
3457 smmu->features |= ARM_SMMU_FEAT_TT_BE; in arm_smmu_device_hw_probe()
3461 smmu->features |= ARM_SMMU_FEAT_TT_LE; in arm_smmu_device_hw_probe()
3465 dev_err(smmu->dev, "unknown/unsupported TT endianness!\n"); in arm_smmu_device_hw_probe()
3466 return -ENXIO; in arm_smmu_device_hw_probe()
3471 smmu->features |= ARM_SMMU_FEAT_PRI; in arm_smmu_device_hw_probe()
3474 smmu->features |= ARM_SMMU_FEAT_ATS; in arm_smmu_device_hw_probe()
3477 smmu->features |= ARM_SMMU_FEAT_SEV; in arm_smmu_device_hw_probe()
3480 smmu->features |= ARM_SMMU_FEAT_MSI; in arm_smmu_device_hw_probe()
3482 smmu->options |= ARM_SMMU_OPT_MSIPOLL; in arm_smmu_device_hw_probe()
3486 smmu->features |= ARM_SMMU_FEAT_HYP; in arm_smmu_device_hw_probe()
3488 smmu->features |= ARM_SMMU_FEAT_E2H; in arm_smmu_device_hw_probe()
3496 dev_warn(smmu->dev, "IDR0.COHACC overridden by FW configuration (%s)\n", in arm_smmu_device_hw_probe()
3501 smmu->features |= ARM_SMMU_FEAT_STALL_FORCE; in arm_smmu_device_hw_probe()
3504 smmu->features |= ARM_SMMU_FEAT_STALLS; in arm_smmu_device_hw_probe()
3508 smmu->features |= ARM_SMMU_FEAT_TRANS_S1; in arm_smmu_device_hw_probe()
3511 smmu->features |= ARM_SMMU_FEAT_TRANS_S2; in arm_smmu_device_hw_probe()
3514 dev_err(smmu->dev, "no translation support!\n"); in arm_smmu_device_hw_probe()
3515 return -ENXIO; in arm_smmu_device_hw_probe()
3521 smmu->ias = 40; in arm_smmu_device_hw_probe()
3526 dev_err(smmu->dev, "AArch64 table format not supported!\n"); in arm_smmu_device_hw_probe()
3527 return -ENXIO; in arm_smmu_device_hw_probe()
3531 smmu->asid_bits = reg & IDR0_ASID16 ? 16 : 8; in arm_smmu_device_hw_probe()
3532 smmu->vmid_bits = reg & IDR0_VMID16 ? 16 : 8; in arm_smmu_device_hw_probe()
3535 reg = readl_relaxed(smmu->base + ARM_SMMU_IDR1); in arm_smmu_device_hw_probe()
3537 dev_err(smmu->dev, "embedded implementation not supported\n"); in arm_smmu_device_hw_probe()
3538 return -ENXIO; in arm_smmu_device_hw_probe()
3542 smmu->cmdq.q.llq.max_n_shift = min_t(u32, CMDQ_MAX_SZ_SHIFT, in arm_smmu_device_hw_probe()
3544 if (smmu->cmdq.q.llq.max_n_shift <= ilog2(CMDQ_BATCH_ENTRIES)) { in arm_smmu_device_hw_probe()
3549 * restrictions on the base pointer for a unit-length queue. in arm_smmu_device_hw_probe()
3551 dev_err(smmu->dev, "command queue size <= %d entries not supported\n", in arm_smmu_device_hw_probe()
3553 return -ENXIO; in arm_smmu_device_hw_probe()
3556 smmu->evtq.q.llq.max_n_shift = min_t(u32, EVTQ_MAX_SZ_SHIFT, in arm_smmu_device_hw_probe()
3558 smmu->priq.q.llq.max_n_shift = min_t(u32, PRIQ_MAX_SZ_SHIFT, in arm_smmu_device_hw_probe()
3562 smmu->ssid_bits = FIELD_GET(IDR1_SSIDSIZE, reg); in arm_smmu_device_hw_probe()
3563 smmu->sid_bits = FIELD_GET(IDR1_SIDSIZE, reg); in arm_smmu_device_hw_probe()
3569 if (smmu->sid_bits <= STRTAB_SPLIT) in arm_smmu_device_hw_probe()
3570 smmu->features &= ~ARM_SMMU_FEAT_2_LVL_STRTAB; in arm_smmu_device_hw_probe()
3573 reg = readl_relaxed(smmu->base + ARM_SMMU_IDR3); in arm_smmu_device_hw_probe()
3575 smmu->features |= ARM_SMMU_FEAT_RANGE_INV; in arm_smmu_device_hw_probe()
3578 reg = readl_relaxed(smmu->base + ARM_SMMU_IDR5); in arm_smmu_device_hw_probe()
3581 smmu->evtq.max_stalls = FIELD_GET(IDR5_STALL_MAX, reg); in arm_smmu_device_hw_probe()
3585 smmu->pgsize_bitmap |= SZ_64K | SZ_512M; in arm_smmu_device_hw_probe()
3587 smmu->pgsize_bitmap |= SZ_16K | SZ_32M; in arm_smmu_device_hw_probe()
3589 smmu->pgsize_bitmap |= SZ_4K | SZ_2M | SZ_1G; in arm_smmu_device_hw_probe()
3593 smmu->features |= ARM_SMMU_FEAT_VAX; in arm_smmu_device_hw_probe()
3598 smmu->oas = 32; in arm_smmu_device_hw_probe()
3601 smmu->oas = 36; in arm_smmu_device_hw_probe()
3604 smmu->oas = 40; in arm_smmu_device_hw_probe()
3607 smmu->oas = 42; in arm_smmu_device_hw_probe()
3610 smmu->oas = 44; in arm_smmu_device_hw_probe()
3613 smmu->oas = 52; in arm_smmu_device_hw_probe()
3614 smmu->pgsize_bitmap |= 1ULL << 42; /* 4TB */ in arm_smmu_device_hw_probe()
3617 dev_info(smmu->dev, in arm_smmu_device_hw_probe()
3618 "unknown output address size. Truncating to 48-bit\n"); in arm_smmu_device_hw_probe()
3621 smmu->oas = 48; in arm_smmu_device_hw_probe()
3624 if (arm_smmu_ops.pgsize_bitmap == -1UL) in arm_smmu_device_hw_probe()
3625 arm_smmu_ops.pgsize_bitmap = smmu->pgsize_bitmap; in arm_smmu_device_hw_probe()
3627 arm_smmu_ops.pgsize_bitmap |= smmu->pgsize_bitmap; in arm_smmu_device_hw_probe()
3630 if (dma_set_mask_and_coherent(smmu->dev, DMA_BIT_MASK(smmu->oas))) in arm_smmu_device_hw_probe()
3631 dev_warn(smmu->dev, in arm_smmu_device_hw_probe()
3634 smmu->ias = max(smmu->ias, smmu->oas); in arm_smmu_device_hw_probe()
3637 smmu->features |= ARM_SMMU_FEAT_SVA; in arm_smmu_device_hw_probe()
3639 dev_info(smmu->dev, "ias %lu-bit, oas %lu-bit (features 0x%08x)\n", in arm_smmu_device_hw_probe()
3640 smmu->ias, smmu->oas, smmu->features); in arm_smmu_device_hw_probe()
3649 smmu->options |= ARM_SMMU_OPT_PAGE0_REGS_ONLY; in acpi_smmu_get_options()
3652 smmu->options |= ARM_SMMU_OPT_SKIP_PREFETCH; in acpi_smmu_get_options()
3656 dev_notice(smmu->dev, "option mask 0x%x\n", smmu->options); in acpi_smmu_get_options()
3663 struct device *dev = smmu->dev; in arm_smmu_device_acpi_probe()
3669 iort_smmu = (struct acpi_iort_smmu_v3 *)node->node_data; in arm_smmu_device_acpi_probe()
3671 acpi_smmu_get_options(iort_smmu->model, smmu); in arm_smmu_device_acpi_probe()
3673 if (iort_smmu->flags & ACPI_IORT_SMMU_V3_COHACC_OVERRIDE) in arm_smmu_device_acpi_probe()
3674 smmu->features |= ARM_SMMU_FEAT_COHERENCY; in arm_smmu_device_acpi_probe()
3682 return -ENODEV; in arm_smmu_device_acpi_probe()
3689 struct device *dev = &pdev->dev; in arm_smmu_device_dt_probe()
3691 int ret = -EINVAL; in arm_smmu_device_dt_probe()
3693 if (of_property_read_u32(dev->of_node, "#iommu-cells", &cells)) in arm_smmu_device_dt_probe()
3694 dev_err(dev, "missing #iommu-cells property\n"); in arm_smmu_device_dt_probe()
3696 dev_err(dev, "invalid #iommu-cells value (%d)\n", cells); in arm_smmu_device_dt_probe()
3702 if (of_dma_is_coherent(dev->of_node)) in arm_smmu_device_dt_probe()
3703 smmu->features |= ARM_SMMU_FEAT_COHERENCY; in arm_smmu_device_dt_probe()
3710 if (smmu->options & ARM_SMMU_OPT_PAGE0_REGS_ONLY) in arm_smmu_resource_size()
3767 struct device *dev = &pdev->dev; in arm_smmu_device_probe()
3772 return -ENOMEM; in arm_smmu_device_probe()
3773 smmu->dev = dev; in arm_smmu_device_probe()
3775 if (dev->of_node) { in arm_smmu_device_probe()
3779 if (ret == -ENODEV) in arm_smmu_device_probe()
3790 return -EINVAL; in arm_smmu_device_probe()
3792 ioaddr = res->start; in arm_smmu_device_probe()
3798 smmu->base = arm_smmu_ioremap(dev, ioaddr, ARM_SMMU_REG_SZ); in arm_smmu_device_probe()
3799 if (IS_ERR(smmu->base)) in arm_smmu_device_probe()
3800 return PTR_ERR(smmu->base); in arm_smmu_device_probe()
3803 smmu->page1 = arm_smmu_ioremap(dev, ioaddr + SZ_64K, in arm_smmu_device_probe()
3805 if (IS_ERR(smmu->page1)) in arm_smmu_device_probe()
3806 return PTR_ERR(smmu->page1); in arm_smmu_device_probe()
3808 smmu->page1 = smmu->base; in arm_smmu_device_probe()
3815 smmu->combined_irq = irq; in arm_smmu_device_probe()
3819 smmu->evtq.q.irq = irq; in arm_smmu_device_probe()
3823 smmu->priq.q.irq = irq; in arm_smmu_device_probe()
3827 smmu->gerr_irq = irq; in arm_smmu_device_probe()
3834 /* Initialise in-memory data structures */ in arm_smmu_device_probe()
3848 ret = iommu_device_sysfs_add(&smmu->iommu, dev, NULL, in arm_smmu_device_probe()
3853 ret = iommu_device_register(&smmu->iommu, &arm_smmu_ops, dev); in arm_smmu_device_probe()
3866 iommu_device_unregister(&smmu->iommu); in arm_smmu_device_probe()
3868 iommu_device_sysfs_remove(&smmu->iommu); in arm_smmu_device_probe()
3877 iommu_device_unregister(&smmu->iommu); in arm_smmu_device_remove()
3878 iommu_device_sysfs_remove(&smmu->iommu); in arm_smmu_device_remove()
3880 iopf_queue_free(smmu->evtq.iopf); in arm_smmu_device_remove()
3891 { .compatible = "arm,smmu-v3", },
3904 .name = "arm-smmu-v3",
3917 MODULE_ALIAS("platform:arm-smmu-v3");