Lines Matching full:iommu
20 #include <linux/amd-iommu.h>
25 #include <asm/iommu.h>
97 * structure describing one IOMMU in the ACPI table. Typically followed by one
117 * A device entry describing which devices a specific IOMMU translates and
133 * An AMD IOMMU memory definition structure. It defines things like exclusion
200 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
206 * The rlookup table is used to find the IOMMU which is responsible
218 * AMD IOMMU allows up to 2^16 different protection domains. This is a bitmap
262 bool translation_pre_enabled(struct amd_iommu *iommu) in translation_pre_enabled() argument
264 return (iommu->flags & AMD_IOMMU_FLAG_TRANS_PRE_ENABLED); in translation_pre_enabled()
267 static void clear_translation_pre_enabled(struct amd_iommu *iommu) in clear_translation_pre_enabled() argument
269 iommu->flags &= ~AMD_IOMMU_FLAG_TRANS_PRE_ENABLED; in clear_translation_pre_enabled()
272 static void init_translation_status(struct amd_iommu *iommu) in init_translation_status() argument
276 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); in init_translation_status()
278 iommu->flags |= AMD_IOMMU_FLAG_TRANS_PRE_ENABLED; in init_translation_status()
304 struct amd_iommu *iommu; in check_feature_on_all_iommus() local
306 for_each_iommu(iommu) { in check_feature_on_all_iommus()
307 ret = iommu_feature(iommu, mask); in check_feature_on_all_iommus()
321 static void __init early_iommu_features_init(struct amd_iommu *iommu, in early_iommu_features_init() argument
325 iommu->features = h->efr_reg; in early_iommu_features_init()
330 static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address) in iommu_read_l1() argument
334 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16)); in iommu_read_l1()
335 pci_read_config_dword(iommu->dev, 0xfc, &val); in iommu_read_l1()
339 static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val) in iommu_write_l1() argument
341 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31)); in iommu_write_l1()
342 pci_write_config_dword(iommu->dev, 0xfc, val); in iommu_write_l1()
343 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16)); in iommu_write_l1()
346 static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address) in iommu_read_l2() argument
350 pci_write_config_dword(iommu->dev, 0xf0, address); in iommu_read_l2()
351 pci_read_config_dword(iommu->dev, 0xf4, &val); in iommu_read_l2()
355 static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val) in iommu_write_l2() argument
357 pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8)); in iommu_write_l2()
358 pci_write_config_dword(iommu->dev, 0xf4, val); in iommu_write_l2()
363 * AMD IOMMU MMIO register space handling functions
365 * These functions are used to program the IOMMU device registers in
371 * This function set the exclusion range in the IOMMU. DMA accesses to the
374 static void iommu_set_exclusion_range(struct amd_iommu *iommu) in iommu_set_exclusion_range() argument
376 u64 start = iommu->exclusion_start & PAGE_MASK; in iommu_set_exclusion_range()
377 u64 limit = (start + iommu->exclusion_length - 1) & PAGE_MASK; in iommu_set_exclusion_range()
380 if (!iommu->exclusion_start) in iommu_set_exclusion_range()
384 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, in iommu_set_exclusion_range()
388 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, in iommu_set_exclusion_range()
392 static void iommu_set_cwwb_range(struct amd_iommu *iommu) in iommu_set_cwwb_range() argument
394 u64 start = iommu_virt_to_phys((void *)iommu->cmd_sem); in iommu_set_cwwb_range()
397 if (!iommu_feature(iommu, FEATURE_SNP)) in iommu_set_cwwb_range()
404 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, in iommu_set_cwwb_range()
411 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, in iommu_set_cwwb_range()
415 /* Programs the physical address of the device table into the IOMMU hardware */
416 static void iommu_set_device_table(struct amd_iommu *iommu) in iommu_set_device_table() argument
420 BUG_ON(iommu->mmio_base == NULL); in iommu_set_device_table()
424 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET, in iommu_set_device_table()
428 /* Generic functions to enable/disable certain features of the IOMMU. */
429 static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit) in iommu_feature_enable() argument
433 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_feature_enable()
435 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_feature_enable()
438 static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit) in iommu_feature_disable() argument
442 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_feature_disable()
444 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_feature_disable()
447 static void iommu_set_inv_tlb_timeout(struct amd_iommu *iommu, int timeout) in iommu_set_inv_tlb_timeout() argument
451 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_set_inv_tlb_timeout()
454 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_set_inv_tlb_timeout()
458 static void iommu_enable(struct amd_iommu *iommu) in iommu_enable() argument
460 iommu_feature_enable(iommu, CONTROL_IOMMU_EN); in iommu_enable()
463 static void iommu_disable(struct amd_iommu *iommu) in iommu_disable() argument
465 if (!iommu->mmio_base) in iommu_disable()
469 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); in iommu_disable()
472 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN); in iommu_disable()
473 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN); in iommu_disable()
475 /* Disable IOMMU GA_LOG */ in iommu_disable()
476 iommu_feature_disable(iommu, CONTROL_GALOG_EN); in iommu_disable()
477 iommu_feature_disable(iommu, CONTROL_GAINT_EN); in iommu_disable()
479 /* Disable IOMMU hardware itself */ in iommu_disable()
480 iommu_feature_disable(iommu, CONTROL_IOMMU_EN); in iommu_disable()
484 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
499 static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu) in iommu_unmap_mmio_space() argument
501 if (iommu->mmio_base) in iommu_unmap_mmio_space()
502 iounmap(iommu->mmio_base); in iommu_unmap_mmio_space()
503 release_mem_region(iommu->mmio_phys, iommu->mmio_phys_end); in iommu_unmap_mmio_space()
524 * The functions below belong to the first pass of AMD IOMMU ACPI table
548 * After reading the highest device id from the IOMMU PCI capability header
638 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
645 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
646 * write commands to that buffer later and the IOMMU will execute them
649 static int __init alloc_command_buffer(struct amd_iommu *iommu) in alloc_command_buffer() argument
651 iommu->cmd_buf = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, in alloc_command_buffer()
654 return iommu->cmd_buf ? 0 : -ENOMEM; in alloc_command_buffer()
658 * This function resets the command buffer if the IOMMU stopped fetching
661 void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu) in amd_iommu_reset_cmd_buffer() argument
663 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); in amd_iommu_reset_cmd_buffer()
665 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); in amd_iommu_reset_cmd_buffer()
666 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); in amd_iommu_reset_cmd_buffer()
667 iommu->cmd_buf_head = 0; in amd_iommu_reset_cmd_buffer()
668 iommu->cmd_buf_tail = 0; in amd_iommu_reset_cmd_buffer()
670 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN); in amd_iommu_reset_cmd_buffer()
677 static void iommu_enable_command_buffer(struct amd_iommu *iommu) in iommu_enable_command_buffer() argument
681 BUG_ON(iommu->cmd_buf == NULL); in iommu_enable_command_buffer()
683 entry = iommu_virt_to_phys(iommu->cmd_buf); in iommu_enable_command_buffer()
686 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET, in iommu_enable_command_buffer()
689 amd_iommu_reset_cmd_buffer(iommu); in iommu_enable_command_buffer()
695 static void iommu_disable_command_buffer(struct amd_iommu *iommu) in iommu_disable_command_buffer() argument
697 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); in iommu_disable_command_buffer()
700 static void __init free_command_buffer(struct amd_iommu *iommu) in free_command_buffer() argument
702 free_pages((unsigned long)iommu->cmd_buf, get_order(CMD_BUFFER_SIZE)); in free_command_buffer()
705 static void *__init iommu_alloc_4k_pages(struct amd_iommu *iommu, in iommu_alloc_4k_pages() argument
712 iommu_feature(iommu, FEATURE_SNP) && in iommu_alloc_4k_pages()
721 /* allocates the memory where the IOMMU will log its events to */
722 static int __init alloc_event_buffer(struct amd_iommu *iommu) in alloc_event_buffer() argument
724 iommu->evt_buf = iommu_alloc_4k_pages(iommu, GFP_KERNEL | __GFP_ZERO, in alloc_event_buffer()
727 return iommu->evt_buf ? 0 : -ENOMEM; in alloc_event_buffer()
730 static void iommu_enable_event_buffer(struct amd_iommu *iommu) in iommu_enable_event_buffer() argument
734 BUG_ON(iommu->evt_buf == NULL); in iommu_enable_event_buffer()
736 entry = iommu_virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK; in iommu_enable_event_buffer()
738 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET, in iommu_enable_event_buffer()
742 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); in iommu_enable_event_buffer()
743 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); in iommu_enable_event_buffer()
745 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN); in iommu_enable_event_buffer()
751 static void iommu_disable_event_buffer(struct amd_iommu *iommu) in iommu_disable_event_buffer() argument
753 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN); in iommu_disable_event_buffer()
756 static void __init free_event_buffer(struct amd_iommu *iommu) in free_event_buffer() argument
758 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE)); in free_event_buffer()
761 /* allocates the memory where the IOMMU will log its events to */
762 static int __init alloc_ppr_log(struct amd_iommu *iommu) in alloc_ppr_log() argument
764 iommu->ppr_log = iommu_alloc_4k_pages(iommu, GFP_KERNEL | __GFP_ZERO, in alloc_ppr_log()
767 return iommu->ppr_log ? 0 : -ENOMEM; in alloc_ppr_log()
770 static void iommu_enable_ppr_log(struct amd_iommu *iommu) in iommu_enable_ppr_log() argument
774 if (iommu->ppr_log == NULL) in iommu_enable_ppr_log()
777 entry = iommu_virt_to_phys(iommu->ppr_log) | PPR_LOG_SIZE_512; in iommu_enable_ppr_log()
779 memcpy_toio(iommu->mmio_base + MMIO_PPR_LOG_OFFSET, in iommu_enable_ppr_log()
783 writel(0x00, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); in iommu_enable_ppr_log()
784 writel(0x00, iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); in iommu_enable_ppr_log()
786 iommu_feature_enable(iommu, CONTROL_PPRLOG_EN); in iommu_enable_ppr_log()
787 iommu_feature_enable(iommu, CONTROL_PPR_EN); in iommu_enable_ppr_log()
790 static void __init free_ppr_log(struct amd_iommu *iommu) in free_ppr_log() argument
792 free_pages((unsigned long)iommu->ppr_log, get_order(PPR_LOG_SIZE)); in free_ppr_log()
795 static void free_ga_log(struct amd_iommu *iommu) in free_ga_log() argument
798 free_pages((unsigned long)iommu->ga_log, get_order(GA_LOG_SIZE)); in free_ga_log()
799 free_pages((unsigned long)iommu->ga_log_tail, get_order(8)); in free_ga_log()
803 static int iommu_ga_log_enable(struct amd_iommu *iommu) in iommu_ga_log_enable() argument
808 if (!iommu->ga_log) in iommu_ga_log_enable()
811 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); in iommu_ga_log_enable()
817 iommu_feature_enable(iommu, CONTROL_GAINT_EN); in iommu_ga_log_enable()
818 iommu_feature_enable(iommu, CONTROL_GALOG_EN); in iommu_ga_log_enable()
821 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); in iommu_ga_log_enable()
832 static int iommu_init_ga_log(struct amd_iommu *iommu) in iommu_init_ga_log() argument
840 iommu->ga_log = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, in iommu_init_ga_log()
842 if (!iommu->ga_log) in iommu_init_ga_log()
845 iommu->ga_log_tail = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, in iommu_init_ga_log()
847 if (!iommu->ga_log_tail) in iommu_init_ga_log()
850 entry = iommu_virt_to_phys(iommu->ga_log) | GA_LOG_SIZE_512; in iommu_init_ga_log()
851 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_BASE_OFFSET, in iommu_init_ga_log()
853 entry = (iommu_virt_to_phys(iommu->ga_log_tail) & in iommu_init_ga_log()
855 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_TAIL_OFFSET, in iommu_init_ga_log()
857 writel(0x00, iommu->mmio_base + MMIO_GA_HEAD_OFFSET); in iommu_init_ga_log()
858 writel(0x00, iommu->mmio_base + MMIO_GA_TAIL_OFFSET); in iommu_init_ga_log()
862 free_ga_log(iommu); in iommu_init_ga_log()
869 static int __init alloc_cwwb_sem(struct amd_iommu *iommu) in alloc_cwwb_sem() argument
871 iommu->cmd_sem = iommu_alloc_4k_pages(iommu, GFP_KERNEL | __GFP_ZERO, 1); in alloc_cwwb_sem()
873 return iommu->cmd_sem ? 0 : -ENOMEM; in alloc_cwwb_sem()
876 static void __init free_cwwb_sem(struct amd_iommu *iommu) in free_cwwb_sem() argument
878 if (iommu->cmd_sem) in free_cwwb_sem()
879 free_page((unsigned long)iommu->cmd_sem); in free_cwwb_sem()
882 static void iommu_enable_xt(struct amd_iommu *iommu) in iommu_enable_xt() argument
891 iommu_feature_enable(iommu, CONTROL_XT_EN); in iommu_enable_xt()
895 static void iommu_enable_gt(struct amd_iommu *iommu) in iommu_enable_gt() argument
897 if (!iommu_feature(iommu, FEATURE_GT)) in iommu_enable_gt()
900 iommu_feature_enable(iommu, CONTROL_GT_EN); in iommu_enable_gt()
927 struct amd_iommu *iommu; in copy_device_table() local
936 for_each_iommu(iommu) { in copy_device_table()
938 lo = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET); in copy_device_table()
939 hi = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET + 4); in copy_device_table()
942 pr_err("IOMMU:%d should use the same dev table as others!\n", in copy_device_table()
943 iommu->index); in copy_device_table()
950 pr_err("The device table size of IOMMU:%d is not expected!\n", in copy_device_table()
951 iommu->index); in copy_device_table()
1032 /* Writes the specific IOMMU for a device into the rlookup table */
1033 static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid) in set_iommu_for_device() argument
1035 amd_iommu_rlookup_table[devid] = iommu; in set_iommu_for_device()
1042 static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu, in set_dev_entry_from_acpi() argument
1062 set_iommu_for_device(iommu, devid); in set_dev_entry_from_acpi()
1173 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
1176 static int __init init_iommu_from_acpi(struct amd_iommu *iommu, in init_iommu_from_acpi() argument
1198 iommu->acpi_flags = h->flags; in init_iommu_from_acpi()
1222 set_dev_entry_from_acpi(iommu, dev_i, e->flags, 0); in init_iommu_from_acpi()
1234 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); in init_iommu_from_acpi()
1264 set_dev_entry_from_acpi(iommu, devid , e->flags, 0); in init_iommu_from_acpi()
1265 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0); in init_iommu_from_acpi()
1297 set_dev_entry_from_acpi(iommu, devid, e->flags, in init_iommu_from_acpi()
1325 set_dev_entry_from_acpi(iommu, in init_iommu_from_acpi()
1328 set_dev_entry_from_acpi(iommu, dev_i, in init_iommu_from_acpi()
1364 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); in init_iommu_from_acpi()
1429 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); in init_iommu_from_acpi()
1443 static void __init free_iommu_one(struct amd_iommu *iommu) in free_iommu_one() argument
1445 free_cwwb_sem(iommu); in free_iommu_one()
1446 free_command_buffer(iommu); in free_iommu_one()
1447 free_event_buffer(iommu); in free_iommu_one()
1448 free_ppr_log(iommu); in free_iommu_one()
1449 free_ga_log(iommu); in free_iommu_one()
1450 iommu_unmap_mmio_space(iommu); in free_iommu_one()
1455 struct amd_iommu *iommu, *next; in free_iommu_all() local
1457 for_each_iommu_safe(iommu, next) { in free_iommu_all()
1458 list_del(&iommu->list); in free_iommu_all()
1459 free_iommu_one(iommu); in free_iommu_all()
1460 kfree(iommu); in free_iommu_all()
1465 * Family15h Model 10h-1fh erratum 746 (IOMMU Logging May Stall Translations)
1470 static void amd_iommu_erratum_746_workaround(struct amd_iommu *iommu) in amd_iommu_erratum_746_workaround() argument
1479 pci_write_config_dword(iommu->dev, 0xf0, 0x90); in amd_iommu_erratum_746_workaround()
1480 pci_read_config_dword(iommu->dev, 0xf4, &value); in amd_iommu_erratum_746_workaround()
1486 pci_write_config_dword(iommu->dev, 0xf0, 0x90 | (1 << 8)); in amd_iommu_erratum_746_workaround()
1488 pci_write_config_dword(iommu->dev, 0xf4, value | 0x4); in amd_iommu_erratum_746_workaround()
1489 pci_info(iommu->dev, "Applying erratum 746 workaround\n"); in amd_iommu_erratum_746_workaround()
1492 pci_write_config_dword(iommu->dev, 0xf0, 0x90); in amd_iommu_erratum_746_workaround()
1496 * Family15h Model 30h-3fh (IOMMU Mishandles ATS Write Permission)
1501 static void amd_iommu_ats_write_check_workaround(struct amd_iommu *iommu) in amd_iommu_ats_write_check_workaround() argument
1511 value = iommu_read_l2(iommu, 0x47); in amd_iommu_ats_write_check_workaround()
1517 iommu_write_l2(iommu, 0x47, value | BIT(0)); in amd_iommu_ats_write_check_workaround()
1519 pci_info(iommu->dev, "Applying ATS write check workaround\n"); in amd_iommu_ats_write_check_workaround()
1523 * This function clues the initialization function for one IOMMU
1525 * hardware. It does NOT enable the IOMMU. This is done afterwards.
1527 static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h) in init_iommu_one() argument
1531 raw_spin_lock_init(&iommu->lock); in init_iommu_one()
1532 iommu->cmd_sem_val = 0; in init_iommu_one()
1534 /* Add IOMMU to internal data structures */ in init_iommu_one()
1535 list_add_tail(&iommu->list, &amd_iommu_list); in init_iommu_one()
1536 iommu->index = amd_iommus_present++; in init_iommu_one()
1538 if (unlikely(iommu->index >= MAX_IOMMUS)) { in init_iommu_one()
1543 /* Index is fine - add IOMMU to the array */ in init_iommu_one()
1544 amd_iommus[iommu->index] = iommu; in init_iommu_one()
1547 * Copy data from ACPI table entry to the iommu struct in init_iommu_one()
1549 iommu->devid = h->devid; in init_iommu_one()
1550 iommu->cap_ptr = h->cap_ptr; in init_iommu_one()
1551 iommu->pci_seg = h->pci_seg; in init_iommu_one()
1552 iommu->mmio_phys = h->mmio_phys; in init_iommu_one()
1560 iommu->mmio_phys_end = MMIO_REG_END_OFFSET; in init_iommu_one()
1562 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET; in init_iommu_one()
1576 iommu->mmio_phys_end = MMIO_REG_END_OFFSET; in init_iommu_one()
1578 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET; in init_iommu_one()
1594 early_iommu_features_init(iommu, h); in init_iommu_one()
1601 iommu->mmio_base = iommu_map_mmio_space(iommu->mmio_phys, in init_iommu_one()
1602 iommu->mmio_phys_end); in init_iommu_one()
1603 if (!iommu->mmio_base) in init_iommu_one()
1606 if (alloc_cwwb_sem(iommu)) in init_iommu_one()
1609 if (alloc_command_buffer(iommu)) in init_iommu_one()
1612 if (alloc_event_buffer(iommu)) in init_iommu_one()
1615 iommu->int_enabled = false; in init_iommu_one()
1617 init_translation_status(iommu); in init_iommu_one()
1618 if (translation_pre_enabled(iommu) && !is_kdump_kernel()) { in init_iommu_one()
1619 iommu_disable(iommu); in init_iommu_one()
1620 clear_translation_pre_enabled(iommu); in init_iommu_one()
1621 pr_warn("Translation was enabled for IOMMU:%d but we are not in kdump mode\n", in init_iommu_one()
1622 iommu->index); in init_iommu_one()
1625 amd_iommu_pre_enabled = translation_pre_enabled(iommu); in init_iommu_one()
1627 ret = init_iommu_from_acpi(iommu, h); in init_iommu_one()
1632 ret = amd_iommu_create_irq_domain(iommu); in init_iommu_one()
1638 * Make sure IOMMU is not considered to translate itself. The IVRS in init_iommu_one()
1641 amd_iommu_rlookup_table[iommu->devid] = NULL; in init_iommu_one()
1673 * Iterates over all IOMMU entries in the ACPI table, allocates the
1674 * IOMMU structure and initializes it with init_iommu_one()
1680 struct amd_iommu *iommu; in init_iommu_all() local
1698 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL); in init_iommu_all()
1699 if (iommu == NULL) in init_iommu_all()
1702 ret = init_iommu_one(iommu, h); in init_iommu_all()
1714 static void init_iommu_perf_ctr(struct amd_iommu *iommu) in init_iommu_perf_ctr() argument
1717 struct pci_dev *pdev = iommu->dev; in init_iommu_perf_ctr()
1719 if (!iommu_feature(iommu, FEATURE_PC)) in init_iommu_perf_ctr()
1724 pci_info(pdev, "IOMMU performance counters supported\n"); in init_iommu_perf_ctr()
1726 val = readl(iommu->mmio_base + MMIO_CNTR_CONF_OFFSET); in init_iommu_perf_ctr()
1727 iommu->max_banks = (u8) ((val >> 12) & 0x3f); in init_iommu_perf_ctr()
1728 iommu->max_counters = (u8) ((val >> 7) & 0xf); in init_iommu_perf_ctr()
1737 struct amd_iommu *iommu = dev_to_amd_iommu(dev); in amd_iommu_show_cap() local
1738 return sprintf(buf, "%x\n", iommu->cap); in amd_iommu_show_cap()
1746 struct amd_iommu *iommu = dev_to_amd_iommu(dev); in amd_iommu_show_features() local
1747 return sprintf(buf, "%llx\n", iommu->features); in amd_iommu_show_features()
1758 .name = "amd-iommu",
1769 * of the IOMMU Extended Feature Register [MMIO Offset 0030h].
1772 static void __init late_iommu_features_init(struct amd_iommu *iommu) in late_iommu_features_init() argument
1776 if (!(iommu->cap & (1 << IOMMU_CAP_EFR))) in late_iommu_features_init()
1780 features = readq(iommu->mmio_base + MMIO_EXT_FEATURES); in late_iommu_features_init()
1782 if (!iommu->features) { in late_iommu_features_init()
1783 iommu->features = features; in late_iommu_features_init()
1791 if (features != iommu->features) in late_iommu_features_init()
1793 features, iommu->features); in late_iommu_features_init()
1796 static int __init iommu_init_pci(struct amd_iommu *iommu) in iommu_init_pci() argument
1798 int cap_ptr = iommu->cap_ptr; in iommu_init_pci()
1801 iommu->dev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(iommu->devid), in iommu_init_pci()
1802 iommu->devid & 0xff); in iommu_init_pci()
1803 if (!iommu->dev) in iommu_init_pci()
1806 /* Prevent binding other PCI device drivers to IOMMU devices */ in iommu_init_pci()
1807 iommu->dev->match_driver = false; in iommu_init_pci()
1809 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET, in iommu_init_pci()
1810 &iommu->cap); in iommu_init_pci()
1812 if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB))) in iommu_init_pci()
1815 late_iommu_features_init(iommu); in iommu_init_pci()
1817 if (iommu_feature(iommu, FEATURE_GT)) { in iommu_init_pci()
1822 pasmax = iommu->features & FEATURE_PASID_MASK; in iommu_init_pci()
1830 glxval = iommu->features & FEATURE_GLXVAL_MASK; in iommu_init_pci()
1839 if (iommu_feature(iommu, FEATURE_GT) && in iommu_init_pci()
1840 iommu_feature(iommu, FEATURE_PPR)) { in iommu_init_pci()
1841 iommu->is_iommu_v2 = true; in iommu_init_pci()
1845 if (iommu_feature(iommu, FEATURE_PPR) && alloc_ppr_log(iommu)) in iommu_init_pci()
1848 ret = iommu_init_ga_log(iommu); in iommu_init_pci()
1852 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE)) { in iommu_init_pci()
1858 init_iommu_perf_ctr(iommu); in iommu_init_pci()
1860 if (is_rd890_iommu(iommu->dev)) { in iommu_init_pci()
1863 iommu->root_pdev = in iommu_init_pci()
1864 pci_get_domain_bus_and_slot(0, iommu->dev->bus->number, in iommu_init_pci()
1872 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4, in iommu_init_pci()
1873 &iommu->stored_addr_lo); in iommu_init_pci()
1874 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8, in iommu_init_pci()
1875 &iommu->stored_addr_hi); in iommu_init_pci()
1878 iommu->stored_addr_lo &= ~1; in iommu_init_pci()
1882 iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j); in iommu_init_pci()
1885 iommu->stored_l2[i] = iommu_read_l2(iommu, i); in iommu_init_pci()
1888 amd_iommu_erratum_746_workaround(iommu); in iommu_init_pci()
1889 amd_iommu_ats_write_check_workaround(iommu); in iommu_init_pci()
1891 iommu_device_sysfs_add(&iommu->iommu, &iommu->dev->dev, in iommu_init_pci()
1892 amd_iommu_groups, "ivhd%d", iommu->index); in iommu_init_pci()
1893 iommu_device_register(&iommu->iommu, &amd_iommu_ops, NULL); in iommu_init_pci()
1895 return pci_enable_device(iommu->dev); in iommu_init_pci()
1904 struct amd_iommu *iommu; in print_iommu_info() local
1906 for_each_iommu(iommu) { in print_iommu_info()
1907 struct pci_dev *pdev = iommu->dev; in print_iommu_info()
1910 pci_info(pdev, "Found IOMMU cap 0x%x\n", iommu->cap_ptr); in print_iommu_info()
1912 if (iommu->cap & (1 << IOMMU_CAP_EFR)) { in print_iommu_info()
1913 pr_info("Extended features (%#llx):", iommu->features); in print_iommu_info()
1916 if (iommu_feature(iommu, (1ULL << i))) in print_iommu_info()
1920 if (iommu->features & FEATURE_GAM_VAPIC) in print_iommu_info()
1937 struct amd_iommu *iommu; in amd_iommu_init_pci() local
1940 for_each_iommu(iommu) { in amd_iommu_init_pci()
1941 ret = iommu_init_pci(iommu); in amd_iommu_init_pci()
1946 iommu_set_cwwb_range(iommu); in amd_iommu_init_pci()
1963 for_each_iommu(iommu) in amd_iommu_init_pci()
1964 iommu_flush_all_caches(iommu); in amd_iommu_init_pci()
1981 static int iommu_setup_msi(struct amd_iommu *iommu) in iommu_setup_msi() argument
1985 r = pci_enable_msi(iommu->dev); in iommu_setup_msi()
1989 r = request_threaded_irq(iommu->dev->irq, in iommu_setup_msi()
1993 iommu); in iommu_setup_msi()
1996 pci_disable_msi(iommu->dev); in iommu_setup_msi()
2034 struct amd_iommu *iommu = irqd->chip_data; in intcapxt_irqdomain_activate() local
2045 * Current IOMMU implemtation uses the same IRQ for all in intcapxt_irqdomain_activate()
2046 * 3 IOMMU interrupts. in intcapxt_irqdomain_activate()
2048 writeq(xt.capxt, iommu->mmio_base + MMIO_INTCAPXT_EVT_OFFSET); in intcapxt_irqdomain_activate()
2049 writeq(xt.capxt, iommu->mmio_base + MMIO_INTCAPXT_PPR_OFFSET); in intcapxt_irqdomain_activate()
2050 writeq(xt.capxt, iommu->mmio_base + MMIO_INTCAPXT_GALOG_OFFSET); in intcapxt_irqdomain_activate()
2105 .name = "IOMMU-MSI",
2145 static int iommu_setup_intcapxt(struct amd_iommu *iommu) in iommu_setup_intcapxt() argument
2157 info.data = iommu; in iommu_setup_intcapxt()
2166 amd_iommu_int_thread, 0, "AMD-Vi", iommu); in iommu_setup_intcapxt()
2173 iommu_feature_enable(iommu, CONTROL_INTCAPXT_EN); in iommu_setup_intcapxt()
2177 static int iommu_init_irq(struct amd_iommu *iommu) in iommu_init_irq() argument
2181 if (iommu->int_enabled) in iommu_init_irq()
2185 ret = iommu_setup_intcapxt(iommu); in iommu_init_irq()
2186 else if (iommu->dev->msi_cap) in iommu_init_irq()
2187 ret = iommu_setup_msi(iommu); in iommu_init_irq()
2194 iommu->int_enabled = true; in iommu_init_irq()
2196 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN); in iommu_init_irq()
2198 if (iommu->ppr_log != NULL) in iommu_init_irq()
2199 iommu_feature_enable(iommu, CONTROL_PPRINT_EN); in iommu_init_irq()
2201 iommu_ga_log_enable(iommu); in iommu_init_irq()
2333 static void iommu_init_flags(struct amd_iommu *iommu) in iommu_init_flags() argument
2335 iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ? in iommu_init_flags()
2336 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) : in iommu_init_flags()
2337 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN); in iommu_init_flags()
2339 iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ? in iommu_init_flags()
2340 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) : in iommu_init_flags()
2341 iommu_feature_disable(iommu, CONTROL_PASSPW_EN); in iommu_init_flags()
2343 iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ? in iommu_init_flags()
2344 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) : in iommu_init_flags()
2345 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN); in iommu_init_flags()
2347 iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ? in iommu_init_flags()
2348 iommu_feature_enable(iommu, CONTROL_ISOC_EN) : in iommu_init_flags()
2349 iommu_feature_disable(iommu, CONTROL_ISOC_EN); in iommu_init_flags()
2352 * make IOMMU memory accesses cache coherent in iommu_init_flags()
2354 iommu_feature_enable(iommu, CONTROL_COHERENT_EN); in iommu_init_flags()
2357 iommu_set_inv_tlb_timeout(iommu, CTRL_INV_TO_1S); in iommu_init_flags()
2360 static void iommu_apply_resume_quirks(struct amd_iommu *iommu) in iommu_apply_resume_quirks() argument
2364 struct pci_dev *pdev = iommu->root_pdev; in iommu_apply_resume_quirks()
2366 /* RD890 BIOSes may not have completely reconfigured the iommu */ in iommu_apply_resume_quirks()
2367 if (!is_rd890_iommu(iommu->dev) || !pdev) in iommu_apply_resume_quirks()
2371 * First, we need to ensure that the iommu is enabled. This is in iommu_apply_resume_quirks()
2379 /* Enable the iommu */ in iommu_apply_resume_quirks()
2383 /* Restore the iommu BAR */ in iommu_apply_resume_quirks()
2384 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4, in iommu_apply_resume_quirks()
2385 iommu->stored_addr_lo); in iommu_apply_resume_quirks()
2386 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8, in iommu_apply_resume_quirks()
2387 iommu->stored_addr_hi); in iommu_apply_resume_quirks()
2392 iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]); in iommu_apply_resume_quirks()
2396 iommu_write_l2(iommu, i, iommu->stored_l2[i]); in iommu_apply_resume_quirks()
2399 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4, in iommu_apply_resume_quirks()
2400 iommu->stored_addr_lo | 1); in iommu_apply_resume_quirks()
2403 static void iommu_enable_ga(struct amd_iommu *iommu) in iommu_enable_ga() argument
2408 iommu_feature_enable(iommu, CONTROL_GAM_EN); in iommu_enable_ga()
2411 iommu_feature_enable(iommu, CONTROL_GA_EN); in iommu_enable_ga()
2412 iommu->irte_ops = &irte_128_ops; in iommu_enable_ga()
2415 iommu->irte_ops = &irte_32_ops; in iommu_enable_ga()
2421 static void early_enable_iommu(struct amd_iommu *iommu) in early_enable_iommu() argument
2423 iommu_disable(iommu); in early_enable_iommu()
2424 iommu_init_flags(iommu); in early_enable_iommu()
2425 iommu_set_device_table(iommu); in early_enable_iommu()
2426 iommu_enable_command_buffer(iommu); in early_enable_iommu()
2427 iommu_enable_event_buffer(iommu); in early_enable_iommu()
2428 iommu_set_exclusion_range(iommu); in early_enable_iommu()
2429 iommu_enable_ga(iommu); in early_enable_iommu()
2430 iommu_enable_xt(iommu); in early_enable_iommu()
2431 iommu_enable(iommu); in early_enable_iommu()
2432 iommu_flush_all_caches(iommu); in early_enable_iommu()
2445 struct amd_iommu *iommu; in early_enable_iommus() local
2460 for_each_iommu(iommu) { in early_enable_iommus()
2461 clear_translation_pre_enabled(iommu); in early_enable_iommus()
2462 early_enable_iommu(iommu); in early_enable_iommus()
2469 for_each_iommu(iommu) { in early_enable_iommus()
2470 iommu_disable_command_buffer(iommu); in early_enable_iommus()
2471 iommu_disable_event_buffer(iommu); in early_enable_iommus()
2472 iommu_enable_command_buffer(iommu); in early_enable_iommus()
2473 iommu_enable_event_buffer(iommu); in early_enable_iommus()
2474 iommu_enable_ga(iommu); in early_enable_iommus()
2475 iommu_enable_xt(iommu); in early_enable_iommus()
2476 iommu_set_device_table(iommu); in early_enable_iommus()
2477 iommu_flush_all_caches(iommu); in early_enable_iommus()
2497 struct amd_iommu *iommu; in enable_iommus_v2() local
2499 for_each_iommu(iommu) { in enable_iommus_v2()
2500 iommu_enable_ppr_log(iommu); in enable_iommus_v2()
2501 iommu_enable_gt(iommu); in enable_iommus_v2()
2514 struct amd_iommu *iommu; in disable_iommus() local
2516 for_each_iommu(iommu) in disable_iommus()
2517 iommu_disable(iommu); in disable_iommus()
2532 struct amd_iommu *iommu; in amd_iommu_resume() local
2534 for_each_iommu(iommu) in amd_iommu_resume()
2535 iommu_apply_resume_quirks(iommu); in amd_iommu_resume()
2648 * This is the hardware init function for AMD IOMMU in the system.
2652 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
2728 * IOMMU see for that device in early_amd_iommu_init()
2735 /* IOMMU rlookup table - find the IOMMU for a specific device */ in early_amd_iommu_init()
2817 struct amd_iommu *iommu; in amd_iommu_enable_interrupts() local
2820 for_each_iommu(iommu) { in amd_iommu_enable_interrupts()
2821 ret = iommu_init_irq(iommu); in amd_iommu_enable_interrupts()
2850 /* Don't use IOMMU if there is Stoney Ridge graphics */ in detect_ivrs()
2856 pr_info("Disable IOMMU on Stoney Ridge\n"); in detect_ivrs()
2870 * AMD IOMMU Initialization State Machine
2934 struct amd_iommu *iommu; in state_next() local
2937 for_each_iommu(iommu) in state_next()
2938 iommu_flush_all_caches(iommu); in state_next()
3007 * This is the core init function for AMD IOMMU hardware in the system.
3013 struct amd_iommu *iommu; in amd_iommu_init() local
3020 * We failed to initialize the AMD IOMMU - try fallback in amd_iommu_init()
3027 for_each_iommu(iommu) in amd_iommu_init()
3028 amd_iommu_debugfs_setup(iommu); in amd_iommu_init()
3046 pr_notice("IOMMU not currently supported when SME is active\n"); in amd_iommu_sme_check()
3053 * Early detect code. This code runs at IOMMU detection time in the DMA
3074 x86_init.iommu.iommu_init = amd_iommu_init; in amd_iommu_detect()
3081 * Parsing functions for the AMD IOMMU specific kernel command line
3112 pr_warn("amd_iommu=fullflush deprecated; use iommu.strict=1 instead\n"); in parse_amd_iommu_options()
3239 struct amd_iommu *iommu; in get_amd_iommu() local
3241 for_each_iommu(iommu) in get_amd_iommu()
3243 return iommu; in get_amd_iommu()
3249 * IOMMU EFR Performance Counter support functionality. This code allows
3250 * access to the IOMMU PC functionality.
3256 struct amd_iommu *iommu = get_amd_iommu(idx); in amd_iommu_pc_get_max_banks() local
3258 if (iommu) in amd_iommu_pc_get_max_banks()
3259 return iommu->max_banks; in amd_iommu_pc_get_max_banks()
3273 struct amd_iommu *iommu = get_amd_iommu(idx); in amd_iommu_pc_get_max_counters() local
3275 if (iommu) in amd_iommu_pc_get_max_counters()
3276 return iommu->max_counters; in amd_iommu_pc_get_max_counters()
3282 static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, in iommu_pc_get_set_reg() argument
3288 /* Make sure the IOMMU PC resource is available */ in iommu_pc_get_set_reg()
3292 /* Check for valid iommu and pc register indexing */ in iommu_pc_get_set_reg()
3293 if (WARN_ON(!iommu || (fxn > 0x28) || (fxn & 7))) in iommu_pc_get_set_reg()
3299 max_offset_lim = (u32)(((0x40 | iommu->max_banks) << 12) | in iommu_pc_get_set_reg()
3300 (iommu->max_counters << 8) | 0x28); in iommu_pc_get_set_reg()
3308 writel((u32)val, iommu->mmio_base + offset); in iommu_pc_get_set_reg()
3309 writel((val >> 32), iommu->mmio_base + offset + 4); in iommu_pc_get_set_reg()
3311 *value = readl(iommu->mmio_base + offset + 4); in iommu_pc_get_set_reg()
3313 *value |= readl(iommu->mmio_base + offset); in iommu_pc_get_set_reg()
3320 int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value) in amd_iommu_pc_get_reg() argument
3322 if (!iommu) in amd_iommu_pc_get_reg()
3325 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, false); in amd_iommu_pc_get_reg()
3328 int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value) in amd_iommu_pc_set_reg() argument
3330 if (!iommu) in amd_iommu_pc_set_reg()
3333 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, true); in amd_iommu_pc_set_reg()