Lines Matching +full:32 +full:- +full:63
1 /* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */
2 /* Copyright (c) 2015 - 2021 Intel Corporation */
122 ((IRDMA_QP_SW_MAX_WQ_QUANTA - IRDMA_SQ_RSVD) / (max_quanta_per_wr))
140 #define IRDMA_QP_WQE_MIN_SIZE 32
197 IRDMA_OP_AH_DESTROY = 32,
359 (((u64)(val) << (dev)->hw_shifts[field ## _S]) & (dev)->hw_masks[field ## _M])
361 ((u64)((val) & (dev)->hw_masks[field ## _M]) >> (dev)->hw_shifts[field ## _S])
363 (((val) << (dev)->hw_shifts[field ## _S]) & (dev)->hw_masks[field ## _M])
365 ((u64)((val) & (dev)->hw_masks[field ## _M]) >> (dev)->hw_shifts[field ## _S])
367 #define IRDMA_STATS_DELTA(a, b, c) ((a) >= (b) ? (a) - (b) : (a) + (c) - (b))
372 #define IRDMA_CQPSQ_QHASH_VLANID GENMASK_ULL(43, 32)
373 #define IRDMA_CQPSQ_QHASH_QPN GENMASK_ULL(49, 32)
377 #define IRDMA_CQPSQ_QHASH_ADDR0 GENMASK_ULL(63, 32)
379 #define IRDMA_CQPSQ_QHASH_ADDR2 GENMASK_ULL(63, 32)
381 #define IRDMA_CQPSQ_QHASH_WQEVALID BIT_ULL(63)
382 #define IRDMA_CQPSQ_QHASH_OPCODE GENMASK_ULL(37, 32)
387 #define IRDMA_CQPSQ_STATS_WQEVALID BIT_ULL(63)
391 #define IRDMA_CQPSQ_STATS_OP GENMASK_ULL(37, 32)
394 #define IRDMA_CQPSQ_WS_WQEVALID BIT_ULL(63)
403 #define IRDMA_CQPSQ_WS_OP GENMASK_ULL(37, 32)
407 #define IRDMA_CQPSQ_WS_WEIGHT GENMASK_ULL(38, 32)
409 #define IRDMA_CQPSQ_UP_WQEVALID BIT_ULL(63)
412 #define IRDMA_CQPSQ_UP_OP GENMASK_ULL(37, 32)
414 #define IRDMA_CQPSQ_UP_CNPOVERRIDE GENMASK_ULL(37, 32)
415 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_WQEVALID BIT_ULL(63)
417 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_OP GENMASK_ULL(37, 32)
418 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MODEL_USED GENMASK_ULL(47, 32)
428 #define IRDMA_CQPHC_HAI_FACTOR GENMASK_ULL(47, 32)
429 #define IRDMA_CQPHC_RAI_FACTOR GENMASK_ULL(63, 48)
433 #define IRDMA_CQPHC_RREDUCE_MPERIOD GENMASK_ULL(63, 32)
440 #define IRDMA_CQPHC_CEQPERVF GENMASK_ULL(39, 32)
442 #define IRDMA_CQPHC_ENABLED_VFS GENMASK_ULL(37, 32)
446 #define IRDMA_CQPHC_SQBASE GENMASK_ULL(63, 9)
448 #define IRDMA_CQPHC_QPCTX GENMASK_ULL(63, 0)
463 #define IRDMA_CQ_WQEIDX GENMASK_ULL(46, 32)
469 #define IRDMA_CQ_VALID BIT_ULL(63)
474 #define IRDMA_CQ_UDVLAN GENMASK_ULL(63, 48)
479 #define IRDMA_CQ_IMMDATAUP32 GENMASK_ULL(63, 32)
481 #define IRDMACQ_TCPSEQNUMRTT GENMASK_ULL(63, 32)
483 #define IRDMACQ_QPID GENMASK_ULL(55, 32)
493 #define IRDMA_CEQE_VALID BIT_ULL(63)
499 #define IRDMA_AEQE_WQDESCIDX GENMASK_ULL(32, 18)
506 #define IRDMA_AEQE_VALID BIT_ULL(63)
509 #define IRDMA_UDA_QPSQ_OPCODE GENMASK_ULL(37, 32)
513 #define IRDMA_UDA_QPSQ_VALID BIT_ULL(63)
526 #define IRDMA_CQPSQ_OPCODE GENMASK_ULL(37, 32)
527 #define IRDMA_CQPSQ_WQEVALID BIT_ULL(63)
537 #define IRDMA_CQPSQ_QP_NEWMSS GENMASK_ULL(45, 32)
545 #define IRDMA_CQPSQ_QP_OP_S 32
570 #define IRDMA_CQPSQ_CQ_OP GENMASK_ULL(37, 32)
586 #define IRDMA_CQPSQ_STAG_PARENTSTAGIDX GENMASK_ULL(55, 32)
611 #define IRDMA_CQPSQ_MLM_MAC4 GENMASK_ULL(39, 32)
621 #define IRDMA_CQPSQ_MVPBP_SD_INX GENMASK_ULL(43, 32)
623 #define IRDMA_CQPSQ_MVPBP_PD_PLPBA GENMASK_ULL(63, 3)
625 /* Manage Push Page - MPP */
635 /* Upload Context - UCTX */
647 #define IRDMA_CQPSQ_SHMCRP_VFNUM GENMASK_ULL(37, 32)
662 #define IRDMA_COMMIT_FPM_BASE_S 32
668 #define IRDMA_CQPSQ_FWQE_SQMNERR GENMASK_ULL(47, 32)
669 #define IRDMA_CQPSQ_FWQE_SQMJERR GENMASK_ULL(63, 48)
679 #define IRDMA_CQPSQ_UPESD_SDDATAHI GENMASK_ULL(63, 32)
681 #define IRDMA_CQPSQ_UPESD_ENTRY_VALID BIT_ULL(63)
687 #define IRDMA_CQPSQ_UPESD_BM GENMASK_ULL(34, 32)
722 #define IRDMAQPC_PPIDX GENMASK_ULL(41, 32)
724 #define IRDMAQPC_RDMAP_VER GENMASK_ULL(63, 62)
725 #define IRDMAQPC_ROCE_TVER GENMASK_ULL(63, 60)
735 #define IRDMAQPC_SRCPORTNUM GENMASK_ULL(47, 32)
736 #define IRDMAQPC_DESTPORTNUM GENMASK_ULL(63, 48)
737 #define IRDMAQPC_DESTIPADDR0 GENMASK_ULL(63, 32)
739 #define IRDMAQPC_DESTIPADDR2 GENMASK_ULL(63, 32)
743 #define IRDMAQPC_VLANTAG GENMASK_ULL(47, 32)
744 #define IRDMAQPC_ARPIDX GENMASK_ULL(63, 48)
751 #define IRDMAQPC_RCVSCALE GENMASK_ULL(35, 32)
753 #define IRDMAQPC_PDIDX GENMASK_ULL(63, 48)
755 #define IRDMAQPC_PKEY GENMASK_ULL(47, 32)
757 #define IRDMAQPC_QKEY GENMASK_ULL(63, 32)
762 #define IRDMAQPC_TIMESTAMP_AGE GENMASK_ULL(63, 32)
764 #define IRDMAQPC_ISN GENMASK_ULL(55, 32)
766 #define IRDMAQPC_LSN GENMASK_ULL(55, 32)
767 #define IRDMAQPC_SNDWND GENMASK_ULL(63, 32)
770 #define IRDMAQPC_RCVWND GENMASK_ULL(63, 32)
772 #define IRDMAQPC_SNDUNA GENMASK_ULL(63, 32)
774 #define IRDMAQPC_PSNUNA GENMASK_ULL(55, 32)
776 #define IRDMAQPC_RTTVAR GENMASK_ULL(63, 32)
778 #define IRDMAQPC_CWND GENMASK_ULL(63, 32)
779 #define IRDMAQPC_CWNDROCE GENMASK_ULL(55, 32)
781 #define IRDMAQPC_SNDWL2 GENMASK_ULL(63, 32)
782 #define IRDMAQPC_ERR_RQ_IDX GENMASK_ULL(45, 32)
783 #define IRDMAQPC_RTOMIN GENMASK_ULL(63, 57)
788 #define IRDMAQPC_RXCQNUM GENMASK_ULL(50, 32)
790 #define IRDMAQPC_Q2ADDR GENMASK_ULL(63, 8)
792 #define IRDMAQPC_MACADDRESS GENMASK_ULL(63, 16)
808 #define IRDMAQPC_THIGH GENMASK_ULL(63, 52)
809 #define IRDMAQPC_TLOW GENMASK_ULL(39, 32)
816 #define IRDMAQPC_RCVMARKOFFSET GENMASK_ULL(40, 32)
823 #define IRDMAQPC_EXCEPTION_LAN_QUEUE GENMASK_ULL(43, 32)
825 #define IRDMAQPC_LOCAL_IPADDR2 GENMASK_ULL(63, 32)
827 #define IRDMAQPC_LOCAL_IPADDR0 GENMASK_ULL(63, 32)
831 #define IRDMA_FEATURE_CNT GENMASK_ULL(47, 32)
832 #define IRDMA_FEATURE_TYPE GENMASK_ULL(63, 48)
834 #define IRDMAQPSQ_OPCODE GENMASK_ULL(37, 32)
845 #define IRDMAQPSQ_VALID BIT_ULL(63)
848 #define IRDMAQPSQ_FRAG_VALID BIT_ULL(63)
849 #define IRDMAQPSQ_FRAG_LEN GENMASK_ULL(62, 32)
852 #define IRDMAQPSQ_GEN1_FRAG_STAG GENMASK_ULL(63, 32)
855 #define IRDMAQPSQ_DESTQPN GENMASK_ULL(55, 32)
864 #define IRDMAQPSQ_IMMDATA GENMASK_ULL(63, 0)
874 #define IRDMAQPSQ_PARENTMRSTAG GENMASK_ULL(63, 32)
887 #define IRDMAQPSQ_FIRSTPMPBLIDXLO GENMASK_ULL(63, 48)
889 #define IRDMAQPSQ_PBLADDR GENMASK_ULL(63, 12)
906 #define IRDMA_QUERY_FPM_MAX_PE_SDS GENMASK_ULL(45, 32)
908 #define IRDMA_QUERY_FPM_XFBLOCKSIZE GENMASK_ULL(63, 32)
909 #define IRDMA_QUERY_FPM_Q1BLOCKSIZE GENMASK_ULL(63, 32)
911 #define IRDMA_QUERY_FPM_TIMERBUCKET GENMASK_ULL(47, 32)
912 #define IRDMA_QUERY_FPM_RRFBLOCKSIZE GENMASK_ULL(63, 32)
913 #define IRDMA_QUERY_FPM_RRFFLBLOCKSIZE GENMASK_ULL(63, 32)
914 #define IRDMA_QUERY_FPM_OOISCFBLOCKSIZE GENMASK_ULL(63, 32)
919 (_aeq)->aeqe_base[IRDMA_RING_CURRENT_TAIL((_aeq)->aeq_ring)].buf \
924 (_ceq)->ceqe_base[IRDMA_RING_CURRENT_TAIL((_ceq)->ceq_ring)].buf \
929 (_ceq)->ceqe_base[_pos].buf \
941 (_cq)->cq_base[IRDMA_RING_CURRENT_HEAD((_cq)->cq_ring)].buf \
946 ((_cq)->cq_base))[IRDMA_RING_CURRENT_HEAD((_cq)->cq_ring)].buf \
996 if ((IRDMA_RING_USED_QUANTA(_ring) + (_count)) < (size - 256)) { \
1020 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 1)) \
1025 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 2)) \
1030 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 3)) \
1035 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 257)) \
1040 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 258)) \
1044 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 259)) \
1053 (((_ring).head + (_ring).size - (_ring).tail) % (_ring).size) \
1058 ((_ring).size - IRDMA_RING_USED_QUANTA(_ring) - 1) \
1063 ((_ring).size - IRDMA_RING_USED_QUANTA(_ring) - 257) \
1073 IRDMA_WQE_SIZE_32 = 32,
1086 enum { IRDMA_Q_ALIGNMENT_M = (128 - 1),
1087 IRDMA_AEQ_ALIGNMENT_M = (256 - 1),
1088 IRDMA_Q2_ALIGNMENT_M = (256 - 1),
1089 IRDMA_CEQ_ALIGNMENT_M = (256 - 1),
1090 IRDMA_CQ0_ALIGNMENT_M = (256 - 1),
1091 IRDMA_HOST_CTX_ALIGNMENT_M = (4 - 1),
1092 IRDMA_SHADOWAREA_M = (128 - 1),
1093 IRDMA_FPM_QUERY_BUF_ALIGNMENT_M = (4 - 1),
1094 IRDMA_FPM_COMMIT_BUF_ALIGNMENT_M = (4 - 1),
1113 * set_64bit_val - set 64 bit value to hw wqe
1124 * set_32bit_val - set 32 bit value to hw wqe
1135 * get_64bit_val - read 64 bit value from wqe
1146 * get_32bit_val - read 32 bit value from wqe
1149 * @val: return 32 bit value